-//===-- SparcV8TargetMachine.h - Define TargetMachine for SparcV8 -*- C++ -*-=//
+//===-- SparcTargetMachine.h - Define TargetMachine for Sparc ---*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
-// This file declares the SparcV8 specific subclass of TargetMachine.
+// This file declares the Sparc specific subclass of TargetMachine.
//
//===----------------------------------------------------------------------===//
-#ifndef SPARCV8TARGETMACHINE_H
-#define SPARCV8TARGETMACHINE_H
+#ifndef SPARCTARGETMACHINE_H
+#define SPARCTARGETMACHINE_H
+#include "SparcInstrInfo.h"
+#include "SparcSubtarget.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetFrameInfo.h"
-#include "llvm/PassManager.h"
-#include "SparcV8InstrInfo.h"
-#include "SparcV8Subtarget.h"
namespace llvm {
-class IntrinsicLowering;
-class Module;
-
-class SparcV8TargetMachine : public TargetMachine {
- SparcV8Subtarget Subtarget;
- SparcV8InstrInfo InstrInfo;
- TargetFrameInfo FrameInfo;
+class SparcTargetMachine : public LLVMTargetMachine {
+ SparcSubtarget Subtarget;
public:
- SparcV8TargetMachine(const Module &M, IntrinsicLowering *IL,
- const std::string &FS);
+ SparcTargetMachine(const Target &T, StringRef TT,
+ StringRef CPU, StringRef FS, const TargetOptions &Options,
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL, bool is64bit);
+
+ const SparcSubtarget *getSubtargetImpl() const override { return &Subtarget; }
- virtual const SparcV8InstrInfo *getInstrInfo() const { return &InstrInfo; }
- virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; }
- virtual const TargetSubtarget *getSubtargetImpl() const{ return &Subtarget; }
- virtual const MRegisterInfo *getRegisterInfo() const {
- return &InstrInfo.getRegisterInfo();
- }
+ // Pass Pipeline Configuration
+ TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
+};
- static unsigned getModuleMatchQuality(const Module &M);
+/// SparcV8TargetMachine - Sparc 32-bit target machine
+///
+class SparcV8TargetMachine : public SparcTargetMachine {
+ virtual void anchor();
+public:
+ SparcV8TargetMachine(const Target &T, StringRef TT,
+ StringRef CPU, StringRef FS,
+ const TargetOptions &Options,
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL);
+};
- virtual bool addPassesToEmitFile(PassManager &PM, std::ostream &Out,
- CodeGenFileType FileType, bool Fast);
+/// SparcV9TargetMachine - Sparc 64-bit target machine
+///
+class SparcV9TargetMachine : public SparcTargetMachine {
+ virtual void anchor();
+public:
+ SparcV9TargetMachine(const Target &T, StringRef TT,
+ StringRef CPU, StringRef FS,
+ const TargetOptions &Options,
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL);
};
} // end namespace llvm