-SparcV8 backend skeleton
-------------------------
-
-This directory houses a 32-bit SPARC V8 backend employing a expander-based
-instruction selector. It is not yet functionally complete. Watch
-this space for more news coming soon!
-
-Current expected test failures
-------------------------------
-
-All SingleSource/Benchmarks tests are expected to pass. Currently, all
-C++ tests and all tests involving varargs intrinsics (use of
-va_start/va_end) are expected to fail. Here are the known SingleSource
-failures:
-
- UnitTests/SetjmpLongjmp/C++/C++Catch
- UnitTests/SetjmpLongjmp/C++/SimpleC++Test
- UnitTests/2003-05-07-VarArgs
- UnitTests/2003-07-09-SignedArgs
- UnitTests/2003-08-11-VaListArg
- Regression/C++/EH/ConditionalExpr
- Regression/C++/EH/ctor_dtor_count-2
- Regression/C++/EH/ctor_dtor_count
- Regression/C++/EH/exception_spec_test
- Regression/C++/EH/function_try_block
- Regression/C++/EH/simple_rethrow
- Regression/C++/EH/simple_throw
- Regression/C++/EH/throw_rethrow_test
- CustomChecked/oopack_v1p8
-
To-do
-----
-* support setcc on longs
-* support basic binary operations on longs
- - use libc procedures instead of open-coding for:
- __div64 __mul64 __rem64 __udiv64 __umul64 __urem64
-* support casting 64-bit integers to FP types
-* support varargs intrinsics (va_start et al.)
-
-$Date$
+* Keep the address of the constant pool in a register instead of forming its
+ address all of the time.
+* We can fold small constant offsets into the %hi/%lo references to constant
+ pool addresses as well.
+* When in V9 mode, register allocate %icc[0-3].
+* Emit the 'Branch on Integer Register with Prediction' instructions. It's
+ not clear how to write a pattern for this though:
+
+float %t1(int %a, int* %p) {
+ %C = seteq int %a, 0
+ br bool %C, label %T, label %F
+T:
+ store int 123, int* %p
+ br label %F
+F:
+ ret float undef
+}
+
+codegens to this:
+
+t1:
+ save -96, %o6, %o6
+1) subcc %i0, 0, %l0
+1) bne .LBBt1_2 ! F
+ nop
+.LBBt1_1: ! T
+ or %g0, 123, %l0
+ st %l0, [%i1]
+.LBBt1_2: ! F
+ restore %g0, %g0, %g0
+ retl
+ nop
+
+1) should be replaced with a brz in V9 mode.
+
+* Same as above, but emit conditional move on register zero (p192) in V9
+ mode. Testcase:
+
+int %t1(int %a, int %b) {
+ %C = seteq int %a, 0
+ %D = select bool %C, int %a, int %b
+ ret int %D
+}
+
+* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling
+ with the Y register, if they are faster.
+
+* Codegen bswap(load)/store(bswap) -> load/store ASI
+
+* Implement frame pointer elimination, e.g. eliminate save/restore for
+ leaf fns.
+* Fill delay slots