#include "SparcV8.h"
#include "SparcV8TargetMachine.h"
+#include "llvm/DerivedTypes.h"
#include "llvm/Function.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
SELECT_ICC, // Select between two values using the current ICC flags.
SELECT_FCC, // Select between two values using the current FCC flags.
+
+ RET_FLAG, // Return with a flag operand.
};
}
namespace {
class SparcV8TargetLowering : public TargetLowering {
+ int VarArgsFrameOffset; // Frame offset to start of varargs area.
public:
SparcV8TargetLowering(TargetMachine &TM);
virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
SelectionDAG &DAG);
virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *MBB);
+
+ virtual const char *getTargetNodeName(unsigned Opcode) const;
};
}
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
+ setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
+ setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
+
+ // Turn FP extload into load/fextend
setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
// Sparc has no select or setcc: expand to SELECT_CC.
setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
+ // V8 has no intrinsics for these particular operations.
+ setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
+ setOperationAction(ISD::MEMSET, MVT::Other, Expand);
+ setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
+
+ setOperationAction(ISD::FSIN , MVT::f64, Expand);
+ setOperationAction(ISD::FCOS , MVT::f64, Expand);
+ setOperationAction(ISD::FSIN , MVT::f32, Expand);
+ setOperationAction(ISD::FCOS , MVT::f32, Expand);
+ setOperationAction(ISD::CTPOP, MVT::i32, Expand);
+ setOperationAction(ISD::CTTZ , MVT::i32, Expand);
+ setOperationAction(ISD::CTLZ , MVT::i32, Expand);
+ setOperationAction(ISD::ROTL , MVT::i32, Expand);
+ setOperationAction(ISD::ROTR , MVT::i32, Expand);
+ setOperationAction(ISD::BSWAP, MVT::i32, Expand);
+
+ setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
+ setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
+ setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
+
+ // We don't have line number support yet.
+ setOperationAction(ISD::LOCATION, MVT::Other, Expand);
+ setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
+ setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
+
+ // Expand these to their default code.
+ setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
+ setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
+ setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
+
+ setStackPointerRegisterToSaveRestore(V8::O6);
+
computeRegisterProperties();
}
+const char *SparcV8TargetLowering::getTargetNodeName(unsigned Opcode) const {
+ switch (Opcode) {
+ default: return 0;
+ case V8ISD::CMPICC: return "V8ISD::CMPICC";
+ case V8ISD::CMPFCC: return "V8ISD::CMPFCC";
+ case V8ISD::BRICC: return "V8ISD::BRICC";
+ case V8ISD::BRFCC: return "V8ISD::BRFCC";
+ case V8ISD::Hi: return "V8ISD::Hi";
+ case V8ISD::Lo: return "V8ISD::Lo";
+ case V8ISD::FTOI: return "V8ISD::FTOI";
+ case V8ISD::ITOF: return "V8ISD::ITOF";
+ case V8ISD::SELECT_ICC: return "V8ISD::SELECT_ICC";
+ case V8ISD::SELECT_FCC: return "V8ISD::SELECT_FCC";
+ case V8ISD::RET_FLAG: return "V8ISD::RET_FLAG";
+ }
+}
+
+/// LowerArguments - V8 uses a very simple ABI, where all values are passed in
+/// either one or two GPRs, including FP values. TODO: we should pass FP values
+/// in FP registers for fastcc functions.
std::vector<SDOperand>
SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
MachineFunction &MF = DAG.getMachineFunction();
SSARegMap *RegMap = MF.getSSARegMap();
std::vector<SDOperand> ArgValues;
- static const unsigned GPR[] = {
+ static const unsigned ArgRegs[] = {
V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5
};
- unsigned ArgNo = 0;
+
+ const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
+ unsigned ArgOffset = 68;
+
+ SDOperand Root = DAG.getRoot();
+ std::vector<SDOperand> OutChains;
+
for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
MVT::ValueType ObjectVT = getValueType(I->getType());
- assert(ArgNo < 6 && "Only args in regs for now");
switch (ObjectVT) {
default: assert(0 && "Unhandled argument type!");
- // TODO: MVT::i64 & FP
case MVT::i1:
case MVT::i8:
case MVT::i16:
- case MVT::i32: {
- unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
- MF.addLiveIn(GPR[ArgNo++], VReg);
- SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
- DAG.setRoot(Arg.getValue(1));
- if (ObjectVT != MVT::i32) {
- unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
- : ISD::AssertZext;
- Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
- DAG.getValueType(ObjectVT));
- Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
+ case MVT::i32:
+ if (I->use_empty()) { // Argument is dead.
+ if (CurArgReg < ArgRegEnd) ++CurArgReg;
+ ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
+ } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
+ unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
+ MF.addLiveIn(*CurArgReg++, VReg);
+ SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
+ if (ObjectVT != MVT::i32) {
+ unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
+ : ISD::AssertZext;
+ Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
+ DAG.getValueType(ObjectVT));
+ Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
+ }
+ ArgValues.push_back(Arg);
+ } else {
+ int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
+ SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
+ SDOperand Load;
+ if (ObjectVT == MVT::i32) {
+ Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
+ } else {
+ unsigned LoadOp =
+ I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
+
+ Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
+ DAG.getSrcValue(0), ObjectVT);
+ }
+ ArgValues.push_back(Load);
}
- ArgValues.push_back(Arg);
+
+ ArgOffset += 4;
break;
- }
- case MVT::i64: {
- unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
- MF.addLiveIn(GPR[ArgNo++], VRegHi);
- unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
- MF.addLiveIn(GPR[ArgNo++], VRegLo);
- SDOperand ArgLo = DAG.getCopyFromReg(DAG.getRoot(), VRegLo, MVT::i32);
- SDOperand ArgHi = DAG.getCopyFromReg(ArgLo.getValue(1), VRegHi, MVT::i32);
- DAG.setRoot(ArgHi.getValue(1));
- ArgValues.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgLo, ArgHi));
+ case MVT::f32:
+ if (I->use_empty()) { // Argument is dead.
+ if (CurArgReg < ArgRegEnd) ++CurArgReg;
+ ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
+ } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
+ // FP value is passed in an integer register.
+ unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
+ MF.addLiveIn(*CurArgReg++, VReg);
+ SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
+
+ Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
+ ArgValues.push_back(Arg);
+ }
+ ArgOffset += 4;
+ break;
+
+ case MVT::i64:
+ case MVT::f64:
+ if (I->use_empty()) { // Argument is dead.
+ if (CurArgReg < ArgRegEnd) ++CurArgReg;
+ if (CurArgReg < ArgRegEnd) ++CurArgReg;
+ ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
+ } else if (CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 &&
+ ((CurArgReg-ArgRegs) & 1) == 0) {
+ // If this is a double argument and the whole thing lives on the stack,
+ // and the argument is aligned, load the double straight from the stack.
+ // We can't do a load in cases like void foo([6ints], int,double),
+ // because the double wouldn't be aligned!
+ int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset);
+ SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
+ ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr,
+ DAG.getSrcValue(0)));
+ } else {
+ SDOperand HiVal;
+ if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
+ unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
+ MF.addLiveIn(*CurArgReg++, VRegHi);
+ HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
+ } else {
+ int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
+ SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
+ HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
+ }
+
+ SDOperand LoVal;
+ if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
+ unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
+ MF.addLiveIn(*CurArgReg++, VRegLo);
+ LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
+ } else {
+ int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
+ SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
+ LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
+ }
+
+ // Compose the two halves together into an i64 unit.
+ SDOperand WholeValue =
+ DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
+
+ // If we want a double, do a bit convert.
+ if (ObjectVT == MVT::f64)
+ WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue);
+
+ ArgValues.push_back(WholeValue);
+ }
+ ArgOffset += 8;
break;
}
+ }
+
+ // Store remaining ArgRegs to the stack if this is a varargs function.
+ if (F.getFunctionType()->isVarArg()) {
+ // Remember the vararg offset for the va_start implementation.
+ VarArgsFrameOffset = ArgOffset;
+
+ for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
+ unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
+ MF.addLiveIn(*CurArgReg, VReg);
+ SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
+
+ int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
+ SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
+
+ OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(),
+ Arg, FIPtr, DAG.getSrcValue(0)));
+ ArgOffset += 4;
}
}
- assert(!F.isVarArg() && "Unimp");
+ if (!OutChains.empty())
+ DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains));
// Finally, inform the code generator which regs we return values in.
switch (getValueType(F.getReturnType())) {
bool isVarArg, unsigned CC,
bool isTailCall, SDOperand Callee,
ArgListTy &Args, SelectionDAG &DAG) {
- assert(0 && "Unimp");
- abort();
+ MachineFunction &MF = DAG.getMachineFunction();
+ // Count the size of the outgoing arguments.
+ unsigned ArgsSize = 0;
+ for (unsigned i = 0, e = Args.size(); i != e; ++i) {
+ switch (getValueType(Args[i].second)) {
+ default: assert(0 && "Unknown value type!");
+ case MVT::i1:
+ case MVT::i8:
+ case MVT::i16:
+ case MVT::i32:
+ case MVT::f32:
+ ArgsSize += 4;
+ break;
+ case MVT::i64:
+ case MVT::f64:
+ ArgsSize += 8;
+ break;
+ }
+ }
+ if (ArgsSize > 4*6)
+ ArgsSize -= 4*6; // Space for first 6 arguments is prereserved.
+ else
+ ArgsSize = 0;
+
+ // Keep stack frames 8-byte aligned.
+ ArgsSize = (ArgsSize+7) & ~7;
+
+ Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
+ DAG.getConstant(ArgsSize, getPointerTy()));
+
+ SDOperand StackPtr, NullSV;
+ std::vector<SDOperand> Stores;
+ std::vector<SDOperand> RegValuesToPass;
+ unsigned ArgOffset = 68;
+ for (unsigned i = 0, e = Args.size(); i != e; ++i) {
+ SDOperand Val = Args[i].first;
+ MVT::ValueType ObjectVT = Val.getValueType();
+ SDOperand ValToStore(0, 0);
+ unsigned ObjSize;
+ switch (ObjectVT) {
+ default: assert(0 && "Unhandled argument type!");
+ case MVT::i1:
+ case MVT::i8:
+ case MVT::i16:
+ // Promote the integer to 32-bits. If the input type is signed, use a
+ // sign extend, otherwise use a zero extend.
+ if (Args[i].second->isSigned())
+ Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val);
+ else
+ Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val);
+ // FALL THROUGH
+ case MVT::i32:
+ ObjSize = 4;
+
+ if (RegValuesToPass.size() >= 6) {
+ ValToStore = Val;
+ } else {
+ RegValuesToPass.push_back(Val);
+ }
+ break;
+ case MVT::f32:
+ ObjSize = 4;
+ if (RegValuesToPass.size() >= 6) {
+ ValToStore = Val;
+ } else {
+ // Convert this to a FP value in an int reg.
+ Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
+ RegValuesToPass.push_back(Val);
+ }
+ break;
+ case MVT::f64:
+ ObjSize = 8;
+ // If we can store this directly into the outgoing slot, do so. We can
+ // do this when all ArgRegs are used and if the outgoing slot is aligned.
+ // FIXME: McGill/misr fails with this.
+ if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) {
+ ValToStore = Val;
+ break;
+ }
+
+ // Otherwise, convert this to a FP value in int regs.
+ Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val);
+ // FALL THROUGH
+ case MVT::i64:
+ ObjSize = 8;
+ if (RegValuesToPass.size() >= 6) {
+ ValToStore = Val; // Whole thing is passed in memory.
+ break;
+ }
+
+ // Split the value into top and bottom part. Top part goes in a reg.
+ SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
+ DAG.getConstant(1, MVT::i32));
+ SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
+ DAG.getConstant(0, MVT::i32));
+ RegValuesToPass.push_back(Hi);
+
+ if (RegValuesToPass.size() >= 6) {
+ ValToStore = Lo;
+ ArgOffset += 4;
+ ObjSize = 4;
+ } else {
+ RegValuesToPass.push_back(Lo);
+ }
+ break;
+ }
+
+ if (ValToStore.Val) {
+ if (!StackPtr.Val) {
+ StackPtr = DAG.getRegister(V8::O6, MVT::i32);
+ NullSV = DAG.getSrcValue(NULL);
+ }
+ SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
+ PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
+ Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
+ ValToStore, PtrOff, NullSV));
+ }
+ ArgOffset += ObjSize;
+ }
+
+ // Emit all stores, make sure the occur before any copies into physregs.
+ if (!Stores.empty())
+ Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
+
+ static const unsigned ArgRegs[] = {
+ V8::O0, V8::O1, V8::O2, V8::O3, V8::O4, V8::O5
+ };
+
+ // Build a sequence of copy-to-reg nodes chained together with token chain
+ // and flag operands which copy the outgoing args into O[0-5].
+ SDOperand InFlag;
+ for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
+ Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag);
+ InFlag = Chain.getValue(1);
+ }
+
+ // If the callee is a GlobalAddress node (quite common, every direct call is)
+ // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
+ if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
+ Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
+
+ std::vector<MVT::ValueType> NodeTys;
+ NodeTys.push_back(MVT::Other); // Returns a chain
+ NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
+ if (InFlag.Val)
+ Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee, InFlag), 0);
+ else
+ Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee), 0);
+ InFlag = Chain.getValue(1);
+
+ MVT::ValueType RetTyVT = getValueType(RetTy);
+ SDOperand RetVal;
+ if (RetTyVT != MVT::isVoid) {
+ switch (RetTyVT) {
+ default: assert(0 && "Unknown value type to return!");
+ case MVT::i1:
+ case MVT::i8:
+ case MVT::i16:
+ RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag);
+ Chain = RetVal.getValue(1);
+
+ // Add a note to keep track of whether it is sign or zero extended.
+ RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
+ MVT::i32, RetVal, DAG.getValueType(RetTyVT));
+ RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
+ break;
+ case MVT::i32:
+ RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag);
+ Chain = RetVal.getValue(1);
+ break;
+ case MVT::f32:
+ RetVal = DAG.getCopyFromReg(Chain, V8::F0, MVT::f32, InFlag);
+ Chain = RetVal.getValue(1);
+ break;
+ case MVT::f64:
+ RetVal = DAG.getCopyFromReg(Chain, V8::D0, MVT::f64, InFlag);
+ Chain = RetVal.getValue(1);
+ break;
+ case MVT::i64:
+ SDOperand Lo = DAG.getCopyFromReg(Chain, V8::O1, MVT::i32, InFlag);
+ SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), V8::O0, MVT::i32,
+ Lo.getValue(2));
+ RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
+ Chain = Hi.getValue(1);
+ break;
+ }
+ }
+
+ Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
+ DAG.getConstant(ArgsSize, getPointerTy()));
+
+ return std::make_pair(RetVal, Chain);
}
SDOperand SparcV8TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
SelectionDAG &DAG) {
- if (Op.getValueType() == MVT::i64) {
+ SDOperand Copy;
+ switch (Op.getValueType()) {
+ default: assert(0 && "Unknown type to return!");
+ case MVT::i32:
+ Copy = DAG.getCopyToReg(Chain, V8::I0, Op, SDOperand());
+ break;
+ case MVT::f32:
+ Copy = DAG.getCopyToReg(Chain, V8::F0, Op, SDOperand());
+ break;
+ case MVT::f64:
+ Copy = DAG.getCopyToReg(Chain, V8::D0, Op, SDOperand());
+ break;
+ case MVT::i64:
SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
DAG.getConstant(1, MVT::i32));
SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
DAG.getConstant(0, MVT::i32));
- return DAG.getNode(ISD::RET, MVT::Other, Chain, Lo, Hi);
- } else {
- return DAG.getNode(ISD::RET, MVT::Other, Chain, Op);
+ Copy = DAG.getCopyToReg(Chain, V8::I0, Hi, SDOperand());
+ Copy = DAG.getCopyToReg(Copy, V8::I1, Lo, Copy.getValue(1));
+ break;
}
+ return DAG.getNode(V8ISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
}
SDOperand SparcV8TargetLowering::
LowerVAStart(SDOperand Chain, SDOperand VAListP, Value *VAListV,
SelectionDAG &DAG) {
- assert(0 && "Unimp");
- abort();
+ SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
+ DAG.getRegister(V8::I6, MVT::i32),
+ DAG.getConstant(VarArgsFrameOffset, MVT::i32));
+ return DAG.getNode(ISD::STORE, MVT::Other, Chain, Offset,
+ VAListP, DAG.getSrcValue(VAListV));
}
std::pair<SDOperand,SDOperand> SparcV8TargetLowering::
LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
const Type *ArgTy, SelectionDAG &DAG) {
- assert(0 && "Unimp");
- abort();
+ // Load the pointer out of the valist.
+ SDOperand Ptr = DAG.getLoad(MVT::i32, Chain,
+ VAListP, DAG.getSrcValue(VAListV));
+ MVT::ValueType ArgVT = getValueType(ArgTy);
+ SDOperand Val = DAG.getLoad(ArgVT, Ptr.getValue(1),
+ Ptr, DAG.getSrcValue(NULL));
+ // Increment the pointer.
+ Ptr = DAG.getNode(ISD::ADD, MVT::i32, Ptr,
+ DAG.getConstant(MVT::getSizeInBits(ArgVT)/8, MVT::i32));
+ // Store it back to the valist.
+ Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Ptr,
+ VAListP, DAG.getSrcValue(VAListV));
+ return std::make_pair(Val, Chain);
}
std::pair<SDOperand, SDOperand> SparcV8TargetLowering::
SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP);
return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
}
- case ISD::FP_TO_SINT: {
+ case ISD::FP_TO_SINT:
// Convert the fp value to integer in an FP register.
- Op = DAG.getNode(V8ISD::FTOI, Op.getOperand(0).getValueType(),
- Op.getOperand(0));
- int Size = Op.getOperand(0).getValueType() == MVT::f32 ? 4 : 8;
- int FrameIdx =
- DAG.getMachineFunction().getFrameInfo()->CreateStackObject(Size, Size);
- SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32);
- SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
- Op, FI, DAG.getSrcValue(0));
- return DAG.getLoad(MVT::i32, ST, FI, DAG.getSrcValue(0));
- }
+ assert(Op.getValueType() == MVT::i32);
+ Op = DAG.getNode(V8ISD::FTOI, MVT::f32, Op.getOperand(0));
+ return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
case ISD::SINT_TO_FP: {
- int Size = Op.getOperand(0).getValueType() == MVT::f32 ? 4 : 8;
- int FrameIdx =
- DAG.getMachineFunction().getFrameInfo()->CreateStackObject(Size, Size);
- SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32);
- SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
- Op.getOperand(0), FI, DAG.getSrcValue(0));
-
- Op = DAG.getLoad(Op.getValueType(), ST, FI, DAG.getSrcValue(0));
-
+ assert(Op.getOperand(0).getValueType() == MVT::i32);
+ SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
// Convert the int value to FP in an FP register.
- return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Op);
+ return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Tmp);
}
case ISD::BR_CC: {
SDOperand Chain = Op.getOperand(0);
// Get the condition flag.
if (LHS.getValueType() == MVT::i32) {
- SDOperand Cond = DAG.getNode(V8ISD::CMPICC, MVT::Flag, LHS, RHS);
+ std::vector<MVT::ValueType> VTs;
+ VTs.push_back(MVT::i32);
+ VTs.push_back(MVT::Flag);
+ std::vector<SDOperand> Ops;
+ Ops.push_back(LHS);
+ Ops.push_back(RHS);
+ SDOperand Cond = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1);
return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond);
} else {
SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS);
SDOperand TrueVal = Op.getOperand(2);
SDOperand FalseVal = Op.getOperand(3);
+ SDOperand CompareFlag;
unsigned Opc;
- Opc = LHS.getValueType() == MVT::i32 ? V8ISD::CMPICC : V8ISD::CMPFCC;
- SDOperand CompareFlag = DAG.getNode(Opc, MVT::Flag, LHS, RHS);
-
- Opc = LHS.getValueType() == MVT::i32 ?
- V8ISD::SELECT_ICC : V8ISD::SELECT_FCC;
+ if (LHS.getValueType() == MVT::i32) {
+ std::vector<MVT::ValueType> VTs;
+ VTs.push_back(LHS.getValueType()); // subcc returns a value
+ VTs.push_back(MVT::Flag);
+ std::vector<SDOperand> Ops;
+ Ops.push_back(LHS);
+ Ops.push_back(RHS);
+ CompareFlag = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1);
+ Opc = V8ISD::SELECT_ICC;
+ } else {
+ CompareFlag = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS);
+ Opc = V8ISD::SELECT_FCC;
+ }
return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
DAG.getConstant(CC, MVT::i32), CompareFlag);
}
- }
+ }
}
MachineBasicBlock *
switch (N->getOpcode()) {
default: break;
- case ISD::BasicBlock: return CodeGenMap[Op] = Op;
case ISD::FrameIndex: {
int FI = cast<FrameIndexSDNode>(N)->getIndex();
if (N->hasOneUse())
CurDAG->getTargetFrameIndex(FI, MVT::i32),
CurDAG->getTargetConstant(0, MVT::i32));
}
- case V8ISD::CMPICC: {
- // FIXME: Handle compare with immediate.
- SDOperand LHS = Select(N->getOperand(0));
- SDOperand RHS = Select(N->getOperand(1));
- SDOperand Result = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag,
- LHS, RHS);
- return CodeGenMap[Op] = Result.getValue(1);
- }
case ISD::ADD_PARTS: {
SDOperand LHSL = Select(N->getOperand(0));
SDOperand LHSH = Select(N->getOperand(1));
// The high part is in the Y register.
return CurDAG->SelectNodeTo(N, V8::RDY, MVT::i32, Mul.getValue(1));
}
-
- case ISD::RET: {
- if (N->getNumOperands() == 2) {
- SDOperand Chain = Select(N->getOperand(0)); // Token chain.
- SDOperand Val = Select(N->getOperand(1));
- if (N->getOperand(1).getValueType() == MVT::i32) {
- Chain = CurDAG->getCopyToReg(Chain, V8::I0, Val);
- } else if (N->getOperand(1).getValueType() == MVT::f32) {
- Chain = CurDAG->getCopyToReg(Chain, V8::F0, Val);
- } else {
- assert(N->getOperand(1).getValueType() == MVT::f64);
- Chain = CurDAG->getCopyToReg(Chain, V8::D0, Val);
- }
- return CurDAG->SelectNodeTo(N, V8::RETL, MVT::Other, Chain);
- } else if (N->getNumOperands() > 1) {
- SDOperand Chain = Select(N->getOperand(0)); // Token chain.
- assert(N->getOperand(1).getValueType() == MVT::i32 &&
- N->getOperand(2).getValueType() == MVT::i32 &&
- N->getNumOperands() == 3 && "Unknown two-register ret value!");
- Chain = CurDAG->getCopyToReg(Chain, V8::I1, Select(N->getOperand(1)));
- Chain = CurDAG->getCopyToReg(Chain, V8::I0, Select(N->getOperand(2)));
- return CurDAG->SelectNodeTo(N, V8::RETL, MVT::Other, Chain);
+ case ISD::CALL:
+ // FIXME: This is a workaround for a bug in tblgen.
+ { // Pattern #47: (call:Flag (tglobaladdr:i32):$dst, ICC:Flag)
+ // Emits: (CALL:void (tglobaladdr:i32):$dst)
+ // Pattern complexity = 2 cost = 1
+ SDOperand N1 = N->getOperand(1);
+ if (N1.getOpcode() != ISD::TargetGlobalAddress &&
+ N1.getOpcode() != ISD::ExternalSymbol) goto P47Fail;
+ SDOperand InFlag = SDOperand(0, 0);
+ SDOperand Chain = N->getOperand(0);
+ SDOperand Tmp0 = N1;
+ Chain = Select(Chain);
+ SDOperand Result;
+ if (N->getNumOperands() == 3) {
+ InFlag = Select(N->getOperand(2));
+ Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0,
+ Chain, InFlag);
+ } else {
+ Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0,
+ Chain);
}
- break; // Generated code handles the void case.
+ Chain = CodeGenMap[SDOperand(N, 0)] = Result.getValue(0);
+ CodeGenMap[SDOperand(N, 1)] = Result.getValue(1);
+ return Result.getValue(Op.ResNo);
}
+ P47Fail:;
+
}
return SelectCode(Op);
projects / oota-llvm.git / blobdiff