SelectionDAG &DAG);
virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *MBB);
+
+ virtual const char *getTargetNodeName(unsigned Opcode) const;
};
}
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
+ setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
+ setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
+
// Turn FP extload into load/fextend
setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
setOperationAction(ISD::CTPOP, MVT::i32, Expand);
setOperationAction(ISD::CTTZ , MVT::i32, Expand);
setOperationAction(ISD::CTLZ , MVT::i32, Expand);
+ setOperationAction(ISD::ROTL , MVT::i32, Expand);
+ setOperationAction(ISD::ROTR , MVT::i32, Expand);
setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
+ setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
+
+ // Not implemented yet.
+ setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
+ setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
computeRegisterProperties();
}
+const char *SparcV8TargetLowering::getTargetNodeName(unsigned Opcode) const {
+ switch (Opcode) {
+ default: return 0;
+ case V8ISD::CMPICC: return "V8ISD::CMPICC";
+ case V8ISD::CMPFCC: return "V8ISD::CMPFCC";
+ case V8ISD::BRICC: return "V8ISD::BRICC";
+ case V8ISD::BRFCC: return "V8ISD::BRFCC";
+ case V8ISD::Hi: return "V8ISD::Hi";
+ case V8ISD::Lo: return "V8ISD::Lo";
+ case V8ISD::FTOI: return "V8ISD::FTOI";
+ case V8ISD::ITOF: return "V8ISD::ITOF";
+ case V8ISD::SELECT_ICC: return "V8ISD::SELECT_ICC";
+ case V8ISD::SELECT_FCC: return "V8ISD::SELECT_FCC";
+ case V8ISD::RET_FLAG: return "V8ISD::RET_FLAG";
+ }
+}
+
/// LowerArguments - V8 uses a very simple ABI, where all values are passed in
/// either one or two GPRs, including FP values. TODO: we should pass FP values
/// in FP registers for fastcc functions.
for (unsigned i = 0, e = Args.size(); i != e; ++i) {
SDOperand Val = Args[i].first;
MVT::ValueType ObjectVT = Val.getValueType();
- SDOperand ValToStore;
+ SDOperand ValToStore(0, 0);
unsigned ObjSize;
switch (ObjectVT) {
default: assert(0 && "Unhandled argument type!");
InFlag = Chain.getValue(1);
}
- std::vector<MVT::ValueType> RetVals;
- RetVals.push_back(MVT::Other);
- RetVals.push_back(MVT::Flag);
-
// If the callee is a GlobalAddress node (quite common, every direct call is)
// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
LowerVAStart(SDOperand Chain, SDOperand VAListP, Value *VAListV,
SelectionDAG &DAG) {
- assert(0 && "Unimp");
- abort();
+ SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
+ DAG.getRegister(V8::I6, MVT::i32),
+ DAG.getConstant(VarArgsFrameOffset, MVT::i32));
+ return DAG.getNode(ISD::STORE, MVT::Other, Chain, Offset,
+ VAListP, DAG.getSrcValue(VAListV));
}
std::pair<SDOperand,SDOperand> SparcV8TargetLowering::
LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
const Type *ArgTy, SelectionDAG &DAG) {
- assert(0 && "Unimp");
- abort();
+ // Load the pointer out of the valist.
+ SDOperand Ptr = DAG.getLoad(MVT::i32, Chain,
+ VAListP, DAG.getSrcValue(VAListV));
+ MVT::ValueType ArgVT = getValueType(ArgTy);
+ SDOperand Val = DAG.getLoad(ArgVT, Ptr.getValue(1),
+ Ptr, DAG.getSrcValue(NULL));
+ // Increment the pointer.
+ Ptr = DAG.getNode(ISD::ADD, MVT::i32, Ptr,
+ DAG.getConstant(MVT::getSizeInBits(ArgVT)/8, MVT::i32));
+ // Store it back to the valist.
+ Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Ptr,
+ VAListP, DAG.getSrcValue(VAListV));
+ return std::make_pair(Val, Chain);
}
std::pair<SDOperand, SDOperand> SparcV8TargetLowering::
return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
case ISD::SINT_TO_FP: {
assert(Op.getOperand(0).getValueType() == MVT::i32);
- Op = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op);
+ SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
// Convert the int value to FP in an FP register.
- return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Op);
+ return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Tmp);
}
case ISD::BR_CC: {
SDOperand Chain = Op.getOperand(0);
// Get the condition flag.
if (LHS.getValueType() == MVT::i32) {
- SDOperand Cond = DAG.getNode(V8ISD::CMPICC, MVT::Flag, LHS, RHS);
+ std::vector<MVT::ValueType> VTs;
+ VTs.push_back(MVT::i32);
+ VTs.push_back(MVT::Flag);
+ std::vector<SDOperand> Ops;
+ Ops.push_back(LHS);
+ Ops.push_back(RHS);
+ SDOperand Cond = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1);
return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond);
} else {
SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS);
SDOperand TrueVal = Op.getOperand(2);
SDOperand FalseVal = Op.getOperand(3);
+ SDOperand CompareFlag;
unsigned Opc;
- Opc = LHS.getValueType() == MVT::i32 ? V8ISD::CMPICC : V8ISD::CMPFCC;
- SDOperand CompareFlag = DAG.getNode(Opc, MVT::Flag, LHS, RHS);
-
- Opc = LHS.getValueType() == MVT::i32 ?
- V8ISD::SELECT_ICC : V8ISD::SELECT_FCC;
+ if (LHS.getValueType() == MVT::i32) {
+ std::vector<MVT::ValueType> VTs;
+ VTs.push_back(LHS.getValueType()); // subcc returns a value
+ VTs.push_back(MVT::Flag);
+ std::vector<SDOperand> Ops;
+ Ops.push_back(LHS);
+ Ops.push_back(RHS);
+ CompareFlag = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1);
+ Opc = V8ISD::SELECT_ICC;
+ } else {
+ CompareFlag = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS);
+ Opc = V8ISD::SELECT_FCC;
+ }
return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
DAG.getConstant(CC, MVT::i32), CompareFlag);
}
switch (N->getOpcode()) {
default: break;
- case ISD::Register: return Op;
case ISD::FrameIndex: {
int FI = cast<FrameIndexSDNode>(N)->getIndex();
if (N->hasOneUse())
CurDAG->getTargetFrameIndex(FI, MVT::i32),
CurDAG->getTargetConstant(0, MVT::i32));
}
- case V8ISD::CMPICC: {
- // FIXME: Handle compare with immediate.
- SDOperand LHS = Select(N->getOperand(0));
- SDOperand RHS = Select(N->getOperand(1));
- SDOperand Result = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag,
- LHS, RHS);
- return CodeGenMap[Op] = Result.getValue(1);
- }
case ISD::ADD_PARTS: {
SDOperand LHSL = Select(N->getOperand(0));
SDOperand LHSH = Select(N->getOperand(1));
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