setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
+ setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
+ setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
+
// Turn FP extload into load/fextend
setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
+
+ // We don't have line number support yet.
+ setOperationAction(ISD::LOCATION, MVT::Other, Expand);
+ setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
+
computeRegisterProperties();
}
MF.addLiveIn(*CurArgReg++, VReg);
SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
- // We use the stack space that is already reserved for this reg.
- int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
- SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
-
- SDOperand SV = DAG.getSrcValue(0);
- SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Root,
- Arg, FIPtr, SV);
- ArgValues.push_back(DAG.getLoad(MVT::f32, Store, FIPtr, SV));
+ Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
+ ArgValues.push_back(Arg);
}
ArgOffset += 4;
break;
// Compose the two halves together into an i64 unit.
SDOperand WholeValue =
DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
-
- if (ObjectVT == MVT::i64) {
- // If we are emitting an i64, this is what we want.
- ArgValues.push_back(WholeValue);
- } else {
- assert(ObjectVT == MVT::f64);
- // Otherwise, emit a store to the stack and reload into FPR.
- int FrameIdx = MF.getFrameInfo()->CreateStackObject(8, 8);
- SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
- SDOperand SV = DAG.getSrcValue(0);
- SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Root,
- WholeValue, FIPtr, SV);
- ArgValues.push_back(DAG.getLoad(MVT::f64, Store, FIPtr, SV));
- }
+
+ // If we want a double, do a bit convert.
+ if (ObjectVT == MVT::f64)
+ WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue);
+
+ ArgValues.push_back(WholeValue);
}
ArgOffset += 8;
break;
ValToStore = Val;
} else {
// Convert this to a FP value in an int reg.
- int FrameIdx = MF.getFrameInfo()->CreateStackObject(4, 4);
- SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
- SDOperand SV = DAG.getSrcValue(0);
- SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
- Val, FIPtr, SV);
- Val = DAG.getLoad(MVT::i32, Store, FIPtr, SV);
+ Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
RegValuesToPass.push_back(Val);
}
break;
- case MVT::f64: {
+ case MVT::f64:
ObjSize = 8;
// If we can store this directly into the outgoing slot, do so. We can
// do this when all ArgRegs are used and if the outgoing slot is aligned.
}
// Otherwise, convert this to a FP value in int regs.
- int FrameIdx = MF.getFrameInfo()->CreateStackObject(8, 8);
- SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
- SDOperand SV = DAG.getSrcValue(0);
- SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
- Val, FIPtr, SV);
- Val = DAG.getLoad(MVT::i64, Store, FIPtr, SV);
- }
+ Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val);
// FALL THROUGH
case MVT::i64:
ObjSize = 8;
if (RegValuesToPass.size() >= 6) {
ValToStore = Lo;
+ ArgOffset += 4;
+ ObjSize = 4;
} else {
RegValuesToPass.push_back(Lo);
}
if (ValToStore.Val) {
if (!StackPtr.Val) {
- StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(), V8::O6, MVT::i32);
+ StackPtr = DAG.getRegister(V8::O6, MVT::i32);
NullSV = DAG.getSrcValue(NULL);
}
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
DAG.getConstant(ArgsSize, getPointerTy()));
- MVT::ValueType ActualRetTyVT = RetTyVT;
- if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i16)
- ActualRetTyVT = MVT::i32; // Promote result to i32.
-
return std::make_pair(RetVal, Chain);
}
LowerVAStart(SDOperand Chain, SDOperand VAListP, Value *VAListV,
SelectionDAG &DAG) {
- assert(0 && "Unimp");
- abort();
+ SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
+ DAG.getRegister(V8::I6, MVT::i32),
+ DAG.getConstant(VarArgsFrameOffset, MVT::i32));
+ return DAG.getNode(ISD::STORE, MVT::Other, Chain, Offset,
+ VAListP, DAG.getSrcValue(VAListV));
}
std::pair<SDOperand,SDOperand> SparcV8TargetLowering::
LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
const Type *ArgTy, SelectionDAG &DAG) {
- assert(0 && "Unimp");
- abort();
+ // Load the pointer out of the valist.
+ SDOperand Ptr = DAG.getLoad(MVT::i32, Chain,
+ VAListP, DAG.getSrcValue(VAListV));
+ MVT::ValueType ArgVT = getValueType(ArgTy);
+ SDOperand Val = DAG.getLoad(ArgVT, Ptr.getValue(1),
+ Ptr, DAG.getSrcValue(NULL));
+ // Increment the pointer.
+ Ptr = DAG.getNode(ISD::ADD, MVT::i32, Ptr,
+ DAG.getConstant(MVT::getSizeInBits(ArgVT)/8, MVT::i32));
+ // Store it back to the valist.
+ Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Ptr,
+ VAListP, DAG.getSrcValue(VAListV));
+ return std::make_pair(Val, Chain);
}
std::pair<SDOperand, SDOperand> SparcV8TargetLowering::
SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP);
return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
}
- case ISD::FP_TO_SINT: {
+ case ISD::FP_TO_SINT:
// Convert the fp value to integer in an FP register.
- Op = DAG.getNode(V8ISD::FTOI, Op.getOperand(0).getValueType(),
- Op.getOperand(0));
- int Size = Op.getOperand(0).getValueType() == MVT::f32 ? 4 : 8;
- int FrameIdx =
- DAG.getMachineFunction().getFrameInfo()->CreateStackObject(Size, Size);
- SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32);
- SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
- Op, FI, DAG.getSrcValue(0));
- return DAG.getLoad(MVT::i32, ST, FI, DAG.getSrcValue(0));
- }
+ assert(Op.getValueType() == MVT::i32);
+ Op = DAG.getNode(V8ISD::FTOI, MVT::f32, Op.getOperand(0));
+ return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
case ISD::SINT_TO_FP: {
- int Size = Op.getOperand(0).getValueType() == MVT::f32 ? 4 : 8;
- int FrameIdx =
- DAG.getMachineFunction().getFrameInfo()->CreateStackObject(Size, Size);
- SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32);
- SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
- Op.getOperand(0), FI, DAG.getSrcValue(0));
-
- Op = DAG.getLoad(Op.getValueType(), ST, FI, DAG.getSrcValue(0));
-
+ assert(Op.getOperand(0).getValueType() == MVT::i32);
+ Op = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
// Convert the int value to FP in an FP register.
return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Op);
}
switch (N->getOpcode()) {
default: break;
+ case ISD::Register: return Op;
case ISD::FrameIndex: {
int FI = cast<FrameIndexSDNode>(N)->getIndex();
if (N->hasOneUse())