fix something-o

[oota-llvm.git] / lib / Target / SparcV8 / SparcV8InstrInfo.h

diff --git a/lib/Target/SparcV8/SparcV8InstrInfo.h b/lib/Target/SparcV8/SparcV8InstrInfo.h
index b76ab035abb16e5700ecf9390b2c9cec14fcfe7b..dc4cf0f65bcf18cf6cb49a34c857dae5c7c3f77f 100644 (file)
--- a/lib/Target/SparcV8/SparcV8InstrInfo.h
+++ b/lib/Target/SparcV8/SparcV8InstrInfo.h
@@ -1,10 +1,10 @@
 //===- SparcV8InstrInfo.h - SparcV8 Instruction Information -----*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file contains the SparcV8 implementation of the TargetInstrInfo class.
@@ -19,6 +19,18 @@
 
 namespace llvm {
 
+/// V8II - This namespace holds all of the target specific flags that
+/// instruction info tracks.
+///
+namespace V8II {
+  enum {
+    Pseudo = (1<<0),
+    Load = (1<<1),
+    Store = (1<<2),
+    DelaySlot = (1<<3)
+  };
+};
+
 class SparcV8InstrInfo : public TargetInstrInfo {
   const SparcV8RegisterInfo RI;
 public:
@@ -30,17 +42,11 @@ public:
   ///
   virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
 
-  /// createNOPinstr - returns the target's implementation of NOP, which is
-  /// usually a pseudo-instruction, implemented by a degenerate version of
-  /// another instruction.
-  ///
-  MachineInstr* createNOPinstr() const;
-
-  /// isNOPinstr - not having a special NOP opcode, we need to know if a given
-  /// instruction is interpreted as an `official' NOP instr, i.e., there may be
-  /// more than one way to `do nothing' but only one canonical way to slack off.
+  /// Return true if the instruction is a register to register move and
+  /// leave the source and dest operands in the passed parameters.
   ///
-  bool isNOPinstr(const MachineInstr &MI) const;
+  virtual bool isMoveInstr(const MachineInstr &MI,
+                           unsigned &SrcReg, unsigned &DstReg) const;
 };
 
 }