// Instruction format superclass
//===----------------------------------------------------------------------===//
-class InstV8 : Instruction { // SparcV8 instruction baseline
- field bits<32> Inst;
-
- let Namespace = "V8";
-
- bits<2> op;
- let Inst{31-30} = op; // Top two bits are the 'op' field
-
- // Bit attributes specific to SparcV8 instructions
- bit isPasi = 0; // Does this instruction affect an alternate addr space?
- bit isPrivileged = 0; // Is this a privileged instruction?
-}
-
include "SparcV8InstrFormats.td"
//===----------------------------------------------------------------------===//
let MIOperandInfo = (ops IntRegs, i32imm);
}
+// Branch targets have OtherVT type.
+def brtarget : Operand<OtherVT>;
+def calltarget : Operand<i32>;
+
+def SDTV8cmpfcc :
+SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisFP<1>, SDTCisSameAs<1, 2>]>;
+def SDTV8brcc :
+SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>, SDTCisVT<1, OtherVT>,
+ SDTCisVT<2, FlagVT>]>;
+def SDTV8selectcc :
+SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
+ SDTCisVT<3, i32>, SDTCisVT<4, FlagVT>]>;
+def SDTV8FTOI :
+SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
+def SDTV8ITOF :
+SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
+
+def V8cmpicc : SDNode<"V8ISD::CMPICC", SDTIntBinOp, [SDNPOutFlag]>;
+def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc, [SDNPOutFlag]>;
+def V8bricc : SDNode<"V8ISD::BRICC", SDTV8brcc, [SDNPHasChain]>;
+def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>;
+
+def V8hi : SDNode<"V8ISD::Hi", SDTIntUnaryOp>;
+def V8lo : SDNode<"V8ISD::Lo", SDTIntUnaryOp>;
+
+def V8ftoi : SDNode<"V8ISD::FTOI", SDTV8FTOI>;
+def V8itof : SDNode<"V8ISD::ITOF", SDTV8ITOF>;
+
+def V8selecticc : SDNode<"V8ISD::SELECT_ICC", SDTV8selectcc>;
+def V8selectfcc : SDNode<"V8ISD::SELECT_FCC", SDTV8selectcc>;
+
+// These are target-independent nodes, but have target-specific formats.
+def SDT_V8CallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
+def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_V8CallSeq, [SDNPHasChain]>;
+def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_V8CallSeq, [SDNPHasChain]>;
+
+def SDT_V8Call : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
+def call : SDNode<"ISD::CALL", SDT_V8Call,
+ [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
+
+def SDT_V8RetFlag : SDTypeProfile<0, 0, []>;
+def retflag : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag,
+ [SDNPHasChain, SDNPOptInFlag]>;
+
//===----------------------------------------------------------------------===//
// Instructions
//===----------------------------------------------------------------------===//
// Pseudo instructions.
-class PseudoInstV8<string asmstr, dag ops> : InstV8 {
- let AsmString = asmstr;
- dag OperandList = ops;
+class Pseudo<dag ops, string asmstr, list<dag> pattern>
+ : InstV8<ops, asmstr, pattern>;
+
+def PHI : Pseudo<(ops variable_ops), "PHI", []>;
+def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt),
+ "!ADJCALLSTACKDOWN $amt",
+ [(callseq_start imm:$amt)]>;
+def ADJCALLSTACKUP : Pseudo<(ops i32imm:$amt),
+ "!ADJCALLSTACKUP $amt",
+ [(callseq_end imm:$amt)]>;
+def IMPLICIT_DEF_Int : Pseudo<(ops IntRegs:$dst),
+ "!IMPLICIT_DEF $dst",
+ [(set IntRegs:$dst, (undef))]>;
+def IMPLICIT_DEF_FP : Pseudo<(ops FPRegs:$dst), "!IMPLICIT_DEF $dst",
+ [(set FPRegs:$dst, (undef))]>;
+def IMPLICIT_DEF_DFP : Pseudo<(ops DFPRegs:$dst), "!IMPLICIT_DEF $dst",
+ [(set DFPRegs:$dst, (undef))]>;
+
+// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the
+// fpmover pass.
+def FpMOVD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
+ "!FpMOVD $src, $dst", []>; // pseudo 64-bit double move
+def FpNEGD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
+ "!FpNEGD $src, $dst",
+ [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
+def FpABSD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
+ "!FpABSD $src, $dst",
+ [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>;
+
+// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
+// scheduler into a branch sequence. This has to handle all permutations of
+// selection between i32/f32/f64 on ICC and FCC.
+let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
+ def SELECT_CC_Int_ICC
+ : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
+ "; SELECT_CC_Int_ICC PSEUDO!",
+ [(set IntRegs:$dst, (V8selecticc IntRegs:$T, IntRegs:$F,
+ imm:$Cond, ICC))]>;
+ def SELECT_CC_Int_FCC
+ : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
+ "; SELECT_CC_Int_FCC PSEUDO!",
+ [(set IntRegs:$dst, (V8selectfcc IntRegs:$T, IntRegs:$F,
+ imm:$Cond, FCC))]>;
+ def SELECT_CC_FP_ICC
+ : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond),
+ "; SELECT_CC_FP_ICC PSEUDO!",
+ [(set FPRegs:$dst, (V8selecticc FPRegs:$T, FPRegs:$F,
+ imm:$Cond, ICC))]>;
+ def SELECT_CC_FP_FCC
+ : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond),
+ "; SELECT_CC_FP_FCC PSEUDO!",
+ [(set FPRegs:$dst, (V8selectfcc FPRegs:$T, FPRegs:$F,
+ imm:$Cond, FCC))]>;
+ def SELECT_CC_DFP_ICC
+ : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
+ "; SELECT_CC_DFP_ICC PSEUDO!",
+ [(set DFPRegs:$dst, (V8selecticc DFPRegs:$T, DFPRegs:$F,
+ imm:$Cond, ICC))]>;
+ def SELECT_CC_DFP_FCC
+ : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
+ "; SELECT_CC_DFP_FCC PSEUDO!",
+ [(set DFPRegs:$dst, (V8selectfcc DFPRegs:$T, DFPRegs:$F,
+ imm:$Cond, FCC))]>;
}
-def PHI : PseudoInstV8<"PHI", (ops variable_ops)>;
-def ADJCALLSTACKDOWN : PseudoInstV8<"!ADJCALLSTACKDOWN $amt",
- (ops i32imm:$amt)>;
-def ADJCALLSTACKUP : PseudoInstV8<"!ADJCALLSTACKUP $amt",
- (ops i32imm:$amt)>;
-//def IMPLICIT_USE : PseudoInstV8<"!IMPLICIT_USE",(ops variable_ops)>;
-def IMPLICIT_DEF : PseudoInstV8<"!IMPLICIT_DEF $dst",
- (ops IntRegs:$dst)>;
-def FpMOVD : PseudoInstV8<"!FpMOVD", (ops)>; // pseudo 64-bit double move
// Section A.3 - Synthetic Instructions, p. 85
// special cases of JMPL:
-let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
+let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, noResults = 1 in {
let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
- def RETL: F3_2<2, 0b111000, (ops),
- "retl", [(ret)]>;
+ def RETL: F3_2<2, 0b111000, (ops), "retl", [(retflag)]>;
}
-// CMP is a special case of SUBCC where destination is ignored, by setting it to
-// %g0 (hardwired zero).
-// FIXME: should keep track of the fact that it defs the integer condition codes
-let rd = 0 in
- def CMPri: F3_2<2, 0b010100,
- (ops IntRegs:$b, i32imm:$c),
- "cmp $b, $c", []>;
// Section B.1 - Load Integer Instructions, p. 90
def LDSBrr : F3_1<3, 0b001001,
(ops IntRegs:$dst, MEMri:$addr),
"ld [$addr], $dst",
[(set IntRegs:$dst, (load ADDRri:$addr))]>;
-def LDDrr : F3_1<3, 0b000011,
- (ops IntRegs:$dst, MEMrr:$addr),
- "ldd [$addr], $dst", []>;
-def LDDri : F3_2<3, 0b000011,
- (ops IntRegs:$dst, MEMri:$addr),
- "ldd [$addr], $dst", []>;
// Section B.2 - Load Floating-point Instructions, p. 92
def LDFrr : F3_1<3, 0b100000,
(ops MEMri:$addr, IntRegs:$src),
"st $src, [$addr]",
[(store IntRegs:$src, ADDRri:$addr)]>;
-def STDrr : F3_1<3, 0b000111,
- (ops MEMrr:$addr, IntRegs:$src),
- "std $src, [$addr]", []>;
-def STDri : F3_2<3, 0b000111,
- (ops MEMri:$addr, IntRegs:$src),
- "std $src, [$addr]", []>;
// Section B.5 - Store Floating-point Instructions, p. 97
def STFrr : F3_1<3, 0b100100,
def XNORrr : F3_1<2, 0b000111,
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
"xnor $b, $c, $dst",
- [(set IntRegs:$dst, (xor IntRegs:$b, (not IntRegs:$c)))]>;
+ [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>;
def XNORri : F3_2<2, 0b000111,
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
"xnor $b, $c, $dst", []>;
"subx $b, $c, $dst", []>;
def SUBCCrr : F3_1<2, 0b010100,
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "subcc $b, $c, $dst", []>;
+ "subcc $b, $c, $dst",
+ [(set IntRegs:$dst, (V8cmpicc IntRegs:$b, IntRegs:$c))]>;
def SUBCCri : F3_2<2, 0b010100,
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "subcc $b, $c, $dst", []>;
+ "subcc $b, $c, $dst",
+ [(set IntRegs:$dst, (V8cmpicc IntRegs:$b, simm13:$c))]>;
def SUBXCCrr: F3_1<2, 0b011100,
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
"subxcc $b, $c, $dst", []>;
// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
// conditional branch class:
-class BranchV8<bits<4> cc, dag ops, string asmstr>
- : F2_2<cc, 0b010, ops, asmstr> {
+class BranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
+ : F2_2<cc, 0b010, ops, asmstr, pattern> {
let isBranch = 1;
let isTerminator = 1;
let hasDelaySlot = 1;
+ let noResults = 1;
}
let isBarrier = 1 in
- def BA : BranchV8<0b1000, (ops IntRegs:$dst), "ba $dst">;
-def BN : BranchV8<0b0000, (ops IntRegs:$dst), "bn $dst">;
-def BNE : BranchV8<0b1001, (ops IntRegs:$dst), "bne $dst">;
-def BE : BranchV8<0b0001, (ops IntRegs:$dst), "be $dst">;
-def BG : BranchV8<0b1010, (ops IntRegs:$dst), "bg $dst">;
-def BLE : BranchV8<0b0010, (ops IntRegs:$dst), "ble $dst">;
-def BGE : BranchV8<0b1011, (ops IntRegs:$dst), "bge $dst">;
-def BL : BranchV8<0b0011, (ops IntRegs:$dst), "bl $dst">;
-def BGU : BranchV8<0b1100, (ops IntRegs:$dst), "bgu $dst">;
-def BLEU : BranchV8<0b0100, (ops IntRegs:$dst), "bleu $dst">;
-def BCC : BranchV8<0b1101, (ops IntRegs:$dst), "bcc $dst">;
-def BCS : BranchV8<0b0101, (ops IntRegs:$dst), "bcs $dst">;
+ def BA : BranchV8<0b1000, (ops brtarget:$dst),
+ "ba $dst",
+ [(br bb:$dst)]>;
+def BNE : BranchV8<0b1001, (ops brtarget:$dst),
+ "bne $dst",
+ [(V8bricc bb:$dst, SETNE, ICC)]>;
+def BE : BranchV8<0b0001, (ops brtarget:$dst),
+ "be $dst",
+ [(V8bricc bb:$dst, SETEQ, ICC)]>;
+def BG : BranchV8<0b1010, (ops brtarget:$dst),
+ "bg $dst",
+ [(V8bricc bb:$dst, SETGT, ICC)]>;
+def BLE : BranchV8<0b0010, (ops brtarget:$dst),
+ "ble $dst",
+ [(V8bricc bb:$dst, SETLE, ICC)]>;
+def BGE : BranchV8<0b1011, (ops brtarget:$dst),
+ "bge $dst",
+ [(V8bricc bb:$dst, SETGE, ICC)]>;
+def BL : BranchV8<0b0011, (ops brtarget:$dst),
+ "bl $dst",
+ [(V8bricc bb:$dst, SETLT, ICC)]>;
+def BGU : BranchV8<0b1100, (ops brtarget:$dst),
+ "bgu $dst",
+ [(V8bricc bb:$dst, SETUGT, ICC)]>;
+def BLEU : BranchV8<0b0100, (ops brtarget:$dst),
+ "bleu $dst",
+ [(V8bricc bb:$dst, SETULE, ICC)]>;
+def BCC : BranchV8<0b1101, (ops brtarget:$dst),
+ "bcc $dst",
+ [(V8bricc bb:$dst, SETUGE, ICC)]>;
+def BCS : BranchV8<0b0101, (ops brtarget:$dst),
+ "bcs $dst",
+ [(V8bricc bb:$dst, SETULT, ICC)]>;
// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
// floating-point conditional branch class:
-class FPBranchV8<bits<4> cc, dag ops, string asmstr>
- : F2_2<cc, 0b110, ops, asmstr> {
+class FPBranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
+ : F2_2<cc, 0b110, ops, asmstr, pattern> {
let isBranch = 1;
let isTerminator = 1;
let hasDelaySlot = 1;
+ let noResults = 1;
}
-def FBA : FPBranchV8<0b1000, (ops IntRegs:$dst), "fba $dst">;
-def FBN : FPBranchV8<0b0000, (ops IntRegs:$dst), "fbn $dst">;
-def FBU : FPBranchV8<0b0111, (ops IntRegs:$dst), "fbu $dst">;
-def FBG : FPBranchV8<0b0110, (ops IntRegs:$dst), "fbg $dst">;
-def FBUG : FPBranchV8<0b0101, (ops IntRegs:$dst), "fbug $dst">;
-def FBL : FPBranchV8<0b0100, (ops IntRegs:$dst), "fbl $dst">;
-def FBUL : FPBranchV8<0b0011, (ops IntRegs:$dst), "fbul $dst">;
-def FBLG : FPBranchV8<0b0010, (ops IntRegs:$dst), "fblg $dst">;
-def FBNE : FPBranchV8<0b0001, (ops IntRegs:$dst), "fbne $dst">;
-def FBE : FPBranchV8<0b1001, (ops IntRegs:$dst), "fbe $dst">;
-def FBUE : FPBranchV8<0b1010, (ops IntRegs:$dst), "fbue $dst">;
-def FBGE : FPBranchV8<0b1011, (ops IntRegs:$dst), "fbge $dst">;
-def FBUGE: FPBranchV8<0b1100, (ops IntRegs:$dst), "fbuge $dst">;
-def FBLE : FPBranchV8<0b1101, (ops IntRegs:$dst), "fble $dst">;
-def FBULE: FPBranchV8<0b1110, (ops IntRegs:$dst), "fbule $dst">;
-def FBO : FPBranchV8<0b1111, (ops IntRegs:$dst), "fbo $dst">;
+def FBU : FPBranchV8<0b0111, (ops brtarget:$dst),
+ "fbu $dst",
+ [(V8brfcc bb:$dst, SETUO, FCC)]>;
+def FBG : FPBranchV8<0b0110, (ops brtarget:$dst),
+ "fbg $dst",
+ [(V8brfcc bb:$dst, SETGT, FCC)]>;
+def FBUG : FPBranchV8<0b0101, (ops brtarget:$dst),
+ "fbug $dst",
+ [(V8brfcc bb:$dst, SETUGT, FCC)]>;
+def FBL : FPBranchV8<0b0100, (ops brtarget:$dst),
+ "fbl $dst",
+ [(V8brfcc bb:$dst, SETLT, FCC)]>;
+def FBUL : FPBranchV8<0b0011, (ops brtarget:$dst),
+ "fbul $dst",
+ [(V8brfcc bb:$dst, SETULT, FCC)]>;
+def FBLG : FPBranchV8<0b0010, (ops brtarget:$dst),
+ "fblg $dst",
+ [(V8brfcc bb:$dst, SETONE, FCC)]>;
+def FBNE : FPBranchV8<0b0001, (ops brtarget:$dst),
+ "fbne $dst",
+ [(V8brfcc bb:$dst, SETNE, FCC)]>;
+def FBE : FPBranchV8<0b1001, (ops brtarget:$dst),
+ "fbe $dst",
+ [(V8brfcc bb:$dst, SETEQ, FCC)]>;
+def FBUE : FPBranchV8<0b1010, (ops brtarget:$dst),
+ "fbue $dst",
+ [(V8brfcc bb:$dst, SETUEQ, FCC)]>;
+def FBGE : FPBranchV8<0b1011, (ops brtarget:$dst),
+ "fbge $dst",
+ [(V8brfcc bb:$dst, SETGE, FCC)]>;
+def FBUGE: FPBranchV8<0b1100, (ops brtarget:$dst),
+ "fbuge $dst",
+ [(V8brfcc bb:$dst, SETUGE, FCC)]>;
+def FBLE : FPBranchV8<0b1101, (ops brtarget:$dst),
+ "fble $dst",
+ [(V8brfcc bb:$dst, SETLE, FCC)]>;
+def FBULE: FPBranchV8<0b1110, (ops brtarget:$dst),
+ "fbule $dst",
+ [(V8brfcc bb:$dst, SETULE, FCC)]>;
+def FBO : FPBranchV8<0b1111, (ops brtarget:$dst),
+ "fbo $dst",
+ [(V8brfcc bb:$dst, SETO, FCC)]>;
// Section B.24 - Call and Link Instruction, p. 125
// This is the only Format 1 instruction
-let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in {
- // pc-relative call:
- let Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
- D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
- def CALL : InstV8 {
- let OperandList = (ops IntRegs:$dst);
+let Uses = [O0, O1, O2, O3, O4, O5],
+ hasDelaySlot = 1, isCall = 1, noResults = 1,
+ Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
+ D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in {
+ def CALL : InstV8<(ops calltarget:$dst),
+ "call $dst", []> {
bits<30> disp;
let op = 1;
let Inst{29-0} = disp;
- let AsmString = "call $dst";
}
-
- // indirect call (O7 is an EXPLICIT def in indirect calls, so it cannot also
- // be an implicit def):
- let Defs = [O0, O1, O2, O3, O4, O5, G1, G2, G3, G4, G5, G6, G7,
- D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
+
+ // indirect calls
def JMPLrr : F3_1<2, 0b111000,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "jmpl $b+$c, $dst", []>;
+ (ops MEMrr:$ptr),
+ "call $ptr",
+ [(call ADDRrr:$ptr)]>;
+ def JMPLri : F3_2<2, 0b111000,
+ (ops MEMri:$ptr),
+ "call $ptr",
+ [(call ADDRri:$ptr)]>;
}
// Section B.28 - Read State Register Instructions
def RDY : F3_1<2, 0b101000,
(ops IntRegs:$dst),
- "rdy $dst", []>;
+ "rd %y, $dst", []>;
// Section B.29 - Write State Register Instructions
def WRYrr : F3_1<2, 0b110000,
// Convert Integer to Floating-point Instructions, p. 141
def FITOS : F3_3<2, 0b110100, 0b011000100,
(ops FPRegs:$dst, FPRegs:$src),
- "fitos $src, $dst", []>;
+ "fitos $src, $dst",
+ [(set FPRegs:$dst, (V8itof FPRegs:$src))]>;
def FITOD : F3_3<2, 0b110100, 0b011001000,
- (ops DFPRegs:$dst, DFPRegs:$src),
- "fitod $src, $dst", []>;
+ (ops DFPRegs:$dst, FPRegs:$src),
+ "fitod $src, $dst",
+ [(set DFPRegs:$dst, (V8itof FPRegs:$src))]>;
// Convert Floating-point to Integer Instructions, p. 142
def FSTOI : F3_3<2, 0b110100, 0b011010001,
(ops FPRegs:$dst, FPRegs:$src),
- "fstoi $src, $dst", []>;
+ "fstoi $src, $dst",
+ [(set FPRegs:$dst, (V8ftoi FPRegs:$src))]>;
def FDTOI : F3_3<2, 0b110100, 0b011010010,
- (ops DFPRegs:$dst, DFPRegs:$src),
- "fdtoi $src, $dst", []>;
+ (ops FPRegs:$dst, DFPRegs:$src),
+ "fdtoi $src, $dst",
+ [(set FPRegs:$dst, (V8ftoi DFPRegs:$src))]>;
// Convert between Floating-point Formats Instructions, p. 143
def FSTOD : F3_3<2, 0b110100, 0b011001001,
"fabss $src, $dst",
[(set FPRegs:$dst, (fabs FPRegs:$src))]>;
+
// Floating-point Square Root Instructions, p.145
def FSQRTS : F3_3<2, 0b110100, 0b000101001,
(ops FPRegs:$dst, FPRegs:$src),
// is modelled with a forced noop after the instruction.
def FCMPS : F3_3<2, 0b110101, 0b001010001,
(ops FPRegs:$src1, FPRegs:$src2),
- "fcmps $src1, $src2\n\tnop", []>;
+ "fcmps $src1, $src2\n\tnop",
+ [(set FCC, (V8cmpfcc FPRegs:$src1, FPRegs:$src2))]>;
def FCMPD : F3_3<2, 0b110101, 0b001010010,
(ops DFPRegs:$src1, DFPRegs:$src2),
- "fcmpd $src1, $src2\n\tnop", []>;
+ "fcmpd $src1, $src2\n\tnop",
+ [(set FCC, (V8cmpfcc DFPRegs:$src1, DFPRegs:$src2))]>;
//===----------------------------------------------------------------------===//
// Non-Instruction Patterns
// Arbitrary immediates.
def : Pat<(i32 imm:$val),
(ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
+
+// Global addresses, constant pool entries
+def : Pat<(V8hi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
+def : Pat<(V8lo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;
+def : Pat<(V8hi tconstpool:$in), (SETHIi tconstpool:$in)>;
+def : Pat<(V8lo tconstpool:$in), (ORri G0, tconstpool:$in)>;
+
+// Add reg, lo. This is used when taking the addr of a global/constpool entry.
+def : Pat<(add IntRegs:$r, (V8lo tglobaladdr:$in)),
+ (ADDri IntRegs:$r, tglobaladdr:$in)>;
+def : Pat<(add IntRegs:$r, (V8lo tconstpool:$in)),
+ (ADDri IntRegs:$r, tconstpool:$in)>;
+
+
+// Calls:
+def : Pat<(call tglobaladdr:$dst),
+ (CALL tglobaladdr:$dst)>;
+def : Pat<(call externalsym:$dst),
+ (CALL externalsym:$dst)>;
+
+def : Pat<(ret), (RETL)>;
+
+// Map integer extload's to zextloads.
+def : Pat<(i32 (extload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>;
+def : Pat<(i32 (extload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>;
+def : Pat<(i32 (extload ADDRrr:$src, i8)), (LDUBrr ADDRrr:$src)>;
+def : Pat<(i32 (extload ADDRri:$src, i8)), (LDUBri ADDRri:$src)>;
+def : Pat<(i32 (extload ADDRrr:$src, i16)), (LDUHrr ADDRrr:$src)>;
+def : Pat<(i32 (extload ADDRri:$src, i16)), (LDUHri ADDRri:$src)>;
+
+// zextload bool -> zextload byte
+def : Pat<(i32 (zextload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>;
+def : Pat<(i32 (zextload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>;
+
+// truncstore bool -> truncstore byte.
+def : Pat<(truncstore IntRegs:$src, ADDRrr:$addr, i1),
+ (STBrr ADDRrr:$addr, IntRegs:$src)>;
+def : Pat<(truncstore IntRegs:$src, ADDRri:$addr, i1),
+ (STBri ADDRri:$addr, IntRegs:$src)>;
projects / oota-llvm.git / blobdiff