Disable a broken optimization

[oota-llvm.git] / lib / Target / SparcV8 / SparcV8InstrInfo.td

diff --git a/lib/Target/SparcV8/SparcV8InstrInfo.td b/lib/Target/SparcV8/SparcV8InstrInfo.td
index 79c054eab57e648a29acd6b8f4f48bf84a53d92c..9613bc5fd466eaeb2cd1c2ba71d8b40685f43d22 100644 (file)
--- a/lib/Target/SparcV8/SparcV8InstrInfo.td
+++ b/lib/Target/SparcV8/SparcV8InstrInfo.td
@@ -59,8 +59,6 @@ def MEMri : Operand<i32> {
 def brtarget : Operand<OtherVT>;
 def calltarget : Operand<i32>;
 
-def SDTV8cmpicc : 
-SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
 def SDTV8cmpfcc : 
 SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisFP<1>, SDTCisSameAs<1, 2>]>;
 def SDTV8brcc : 
@@ -74,8 +72,8 @@ SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
 def SDTV8ITOF :
 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
 
-def V8cmpicc : SDNode<"V8ISD::CMPICC", SDTV8cmpicc>;
-def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc>;
+def V8cmpicc : SDNode<"V8ISD::CMPICC", SDTIntBinOp, [SDNPOutFlag]>;
+def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc, [SDNPOutFlag]>;
 def V8bricc : SDNode<"V8ISD::BRICC", SDTV8brcc, [SDNPHasChain]>;
 def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>;
 
@@ -94,10 +92,12 @@ def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_V8CallSeq, [SDNPHasChain]>;
 def callseq_end   : SDNode<"ISD::CALLSEQ_END",   SDT_V8CallSeq, [SDNPHasChain]>;
 
 def SDT_V8Call    : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
-def call          : SDNode<"ISD::CALL", SDT_V8Call, [SDNPHasChain]>;
+def call          : SDNode<"ISD::CALL", SDT_V8Call,
+                          [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
 
 def SDT_V8RetFlag : SDTypeProfile<0, 0, []>;
-def retflag       : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag, [SDNPHasChain]>;
+def retflag       : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag,
+                          [SDNPHasChain, SDNPOptInFlag]>;
 
 //===----------------------------------------------------------------------===//
 // Instructions
@@ -171,12 +171,9 @@ let usesCustomDAGSchedInserter = 1 in {  // Expanded by the scheduler.
 
 // Section A.3 - Synthetic Instructions, p. 85
 // special cases of JMPL:
-let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
+let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, noResults = 1 in {
   let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
-    // FIXME: temporary workaround for return without an incoming flag.
-    def RETVOID: F3_2<2, 0b111000, (ops), "retl", [(ret)]>;
-    let hasInFlag = 1 in
-      def RETL: F3_2<2, 0b111000, (ops), "retl", []>;
+    def RETL: F3_2<2, 0b111000, (ops), "retl", [(retflag)]>;
 }
 
 // Section B.1 - Load Integer Instructions, p. 90
@@ -336,7 +333,7 @@ def XORri   : F3_2<2, 0b000011,
 def XNORrr  : F3_1<2, 0b000111,
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "xnor $b, $c, $dst",
-                   [(set IntRegs:$dst, (xor IntRegs:$b, (not IntRegs:$c)))]>;
+                   [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>;
 def XNORri  : F3_2<2, 0b000111,
                    (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
                    "xnor $b, $c, $dst", []>;
@@ -406,10 +403,12 @@ def SUBXri  : F3_2<2, 0b001100,
                    "subx $b, $c, $dst", []>;
 def SUBCCrr : F3_1<2, 0b010100, 
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
-                   "subcc $b, $c, $dst", []>;
+                   "subcc $b, $c, $dst",
+                   [(set IntRegs:$dst, (V8cmpicc IntRegs:$b, IntRegs:$c))]>;
 def SUBCCri : F3_2<2, 0b010100,
                    (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
-                   "subcc $b, $c, $dst", []>;
+                   "subcc $b, $c, $dst",
+                   [(set IntRegs:$dst, (V8cmpicc IntRegs:$b, simm13:$c))]>;
 def SUBXCCrr: F3_1<2, 0b011100, 
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "subxcc $b, $c, $dst", []>;
@@ -466,6 +465,7 @@ class BranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
   let isBranch = 1;
   let isTerminator = 1;
   let hasDelaySlot = 1;
+  let noResults = 1;
 }
 
 let isBarrier = 1 in
@@ -511,6 +511,7 @@ class FPBranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
   let isBranch = 1;
   let isTerminator = 1;
   let hasDelaySlot = 1;
+  let noResults = 1;
 }
 
 def FBU  : FPBranchV8<0b0111, (ops brtarget:$dst),
@@ -561,7 +562,7 @@ def FBO  : FPBranchV8<0b1111, (ops brtarget:$dst),
 // Section B.24 - Call and Link Instruction, p. 125
 // This is the only Format 1 instruction
 let Uses = [O0, O1, O2, O3, O4, O5],
-    hasDelaySlot = 1, isCall = 1, hasInFlag = 1, hasOutFlag = 1,
+    hasDelaySlot = 1, isCall = 1, noResults = 1,
     Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
     D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in { 
   def CALL : InstV8<(ops calltarget:$dst),
@@ -723,8 +724,11 @@ def : Pat<(V8lo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;
 def : Pat<(V8hi tconstpool:$in), (SETHIi tconstpool:$in)>;
 def : Pat<(V8lo tconstpool:$in), (ORri G0, tconstpool:$in)>;
 
-// Return of a value, which has an input flag.
-def : Pat<(retflag), (RETL)>;
+// Add reg, lo.  This is used when taking the addr of a global/constpool entry.
+def : Pat<(add IntRegs:$r, (V8lo tglobaladdr:$in)),
+          (ADDri IntRegs:$r, tglobaladdr:$in)>;
+def : Pat<(add IntRegs:$r, (V8lo tconstpool:$in)),
+          (ADDri IntRegs:$r, tconstpool:$in)>;
 
 
 // Calls: 
@@ -733,6 +737,7 @@ def : Pat<(call tglobaladdr:$dst),
 def : Pat<(call externalsym:$dst),
           (CALL externalsym:$dst)>;
 
+def : Pat<(ret), (RETL)>;
 
 // Map integer extload's to zextloads.
 def : Pat<(i32 (extload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>;