add fneg/fabs support for doubles

[oota-llvm.git] / lib / Target / SparcV8 / SparcV8RegisterInfo.cpp

diff --git a/lib/Target/SparcV8/SparcV8RegisterInfo.cpp b/lib/Target/SparcV8/SparcV8RegisterInfo.cpp
index 5e371bd87a3b2fba6cb6f878b27c421f63dca9dd..f781ee92a5ce87728f94065091f263cf7756ef2e 100644 (file)
--- a/lib/Target/SparcV8/SparcV8RegisterInfo.cpp
+++ b/lib/Target/SparcV8/SparcV8RegisterInfo.cpp
@@ -1,10 +1,10 @@
 //===- SparcV8RegisterInfo.cpp - SparcV8 Register Information ---*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file contains the SparcV8 implementation of the MRegisterInfo class.
@@ -17,7 +17,7 @@
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/Type.h"
-#include "Support/STLExtras.h"
+#include "llvm/ADT/STLExtras.h"
 #include <iostream>
 using namespace llvm;
 
@@ -27,17 +27,16 @@ SparcV8RegisterInfo::SparcV8RegisterInfo()
 
 void SparcV8RegisterInfo::
 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
-                    unsigned SrcReg, int FrameIdx) const {
-  const TargetRegisterClass *RC = getRegClass(SrcReg);
-
+                    unsigned SrcReg, int FrameIdx,
+                    const TargetRegisterClass *RC) const {
   // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
-  if (RC == SparcV8::IntRegsRegisterClass) 
-    BuildMI (MBB, I, V8::ST, 3).addFrameIndex (FrameIdx).addSImm (0)
+  if (RC == V8::IntRegsRegisterClass)
+    BuildMI (MBB, I, V8::STri, 3).addFrameIndex (FrameIdx).addSImm (0)
       .addReg (SrcReg);
-  else if (RC == SparcV8::FPRegsRegisterClass)
+  else if (RC == V8::FPRegsRegisterClass)
     BuildMI (MBB, I, V8::STFri, 3).addFrameIndex (FrameIdx).addSImm (0)
       .addReg (SrcReg);
-  else if (RC == SparcV8::DFPRegsRegisterClass)
+  else if (RC == V8::DFPRegsRegisterClass)
     BuildMI (MBB, I, V8::STDFri, 3).addFrameIndex (FrameIdx).addSImm (0)
       .addReg (SrcReg);
   else
@@ -46,14 +45,14 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
 
 void SparcV8RegisterInfo::
 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
-                     unsigned DestReg, int FrameIdx) const {
-  const TargetRegisterClass *RC = getRegClass(DestReg);
-  if (RC == SparcV8::IntRegsRegisterClass) 
-    BuildMI (MBB, I, V8::LD, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
-  else if (RC == SparcV8::FPRegsRegisterClass)
+                     unsigned DestReg, int FrameIdx,
+                     const TargetRegisterClass *RC) const {
+  if (RC == V8::IntRegsRegisterClass)
+    BuildMI (MBB, I, V8::LDri, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
+  else if (RC == V8::FPRegsRegisterClass)
     BuildMI (MBB, I, V8::LDFri, 2, DestReg).addFrameIndex (FrameIdx)
       .addSImm (0);
-  else if (RC == SparcV8::DFPRegsRegisterClass)
+  else if (RC == V8::DFPRegsRegisterClass)
     BuildMI (MBB, I, V8::LDDFri, 2, DestReg).addFrameIndex (FrameIdx)
       .addSImm (0);
   else
@@ -64,10 +63,12 @@ void SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
                                        MachineBasicBlock::iterator I,
                                        unsigned DestReg, unsigned SrcReg,
                                        const TargetRegisterClass *RC) const {
-  if (RC == SparcV8::IntRegsRegisterClass) 
+  if (RC == V8::IntRegsRegisterClass)
     BuildMI (MBB, I, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (SrcReg);
-  else if (RC == SparcV8::FPRegsRegisterClass)
+  else if (RC == V8::FPRegsRegisterClass)
     BuildMI (MBB, I, V8::FMOVS, 1, DestReg).addReg (SrcReg);
+  else if (RC == V8::DFPRegsRegisterClass)
+    BuildMI (MBB, I, V8::FpMOVD, 1, DestReg).addReg (SrcReg);
   else
     assert (0 && "Can't copy this register");
 }
@@ -75,10 +76,12 @@ void SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
 void SparcV8RegisterInfo::
 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
                               MachineBasicBlock::iterator I) const {
-  std::cerr
-    << "Sorry, I don't know how to eliminate call frame pseudo instrs yet, in\n"
-    << __FUNCTION__ << " at " << __FILE__ << ":" << __LINE__ << "\n";
-  abort();
+  MachineInstr &MI = *I;
+  int size = MI.getOperand (0).getImmedValue ();
+  if (MI.getOpcode () == V8::ADJCALLSTACKDOWN)
+    size = -size;
+  BuildMI (MBB, I, V8::ADDri, 2, V8::O6).addReg (V8::O6).addSImm (size);
+  MBB.erase (I);
 }
 
 void
@@ -93,7 +96,7 @@ SparcV8RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
   int FrameIndex = MI.getOperand(i).getFrameIndex();
 
   // Replace frame index with a frame pointer reference
-  MI.SetMachineOperandReg (i, V8::FP);
+  MI.SetMachineOperandReg (i, V8::I6);
 
   // Addressable stack objects are accessed using neg. offsets from %fp
   MachineFunction &MF = *MI.getParent()->getParent();
@@ -113,8 +116,8 @@ void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
   // Get the number of bytes to allocate from the FrameInfo
   int NumBytes = (int) MFI->getStackSize();
 
-  // Emit the correct save instruction based on the number of bytes in the frame.
-  // Minimum stack frame size according to V8 ABI is:
+  // Emit the correct save instruction based on the number of bytes in
+  // the frame. Minimum stack frame size according to V8 ABI is:
   //   16 words for register window spill
   //    1 word for address of returned aggregate-value
   // +  6 words for passing parameters on the stack
@@ -125,7 +128,7 @@ void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
   // is required by the ABI.
   NumBytes = (NumBytes + 7) & ~7;
   BuildMI(MBB, MBB.begin(), V8::SAVEri, 2,
-          V8::SP).addImm(-NumBytes).addReg(V8::SP);
+          V8::O6).addImm(-NumBytes).addReg(V8::O6);
 }
 
 void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
@@ -141,8 +144,8 @@ void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
 const TargetRegisterClass*
 SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const {
   switch (Ty->getTypeID()) {
-  case Type::FloatTyID:  return &FPRegsInstance;
-  case Type::DoubleTyID: return &DFPRegsInstance;
+  case Type::FloatTyID:  return V8::FPRegsRegisterClass;
+  case Type::DoubleTyID: return V8::DFPRegsRegisterClass;
   case Type::LongTyID:
   case Type::ULongTyID:  assert(0 && "Long values do not fit in registers!");
   default:               assert(0 && "Invalid type to getClass!");
@@ -153,7 +156,7 @@ SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const {
   case Type::UShortTyID:
   case Type::IntTyID:
   case Type::UIntTyID:
-  case Type::PointerTyID: return &IntRegsInstance;
+  case Type::PointerTyID: return V8::IntRegsRegisterClass;
   }
 }