Make sure that bool,byte and short arguments are the right type when loaded

[oota-llvm.git] / lib / Target / SparcV8 / SparcV8RegisterInfo.td

diff --git a/lib/Target/SparcV8/SparcV8RegisterInfo.td b/lib/Target/SparcV8/SparcV8RegisterInfo.td
index 52ddf59721a1fb6befbf333de98254739a2eb0ac..07012b1626fef513cd8451e790ed9a5deb72749e 100644 (file)
--- a/lib/Target/SparcV8/SparcV8RegisterInfo.td
+++ b/lib/Target/SparcV8/SparcV8RegisterInfo.td
@@ -45,9 +45,6 @@ def I0 : Ri<24, "I0">; def I1 : Ri<25, "I1">; def I2 : Ri<26, "I2">;
 def I3 : Ri<27, "I3">; def I4 : Ri<28, "I4">; def I5 : Ri<29, "I5">; 
 def I6 : Ri<30, "I6">; def I7 : Ri<31, "I7">;
 
-// Standard register aliases
-def SP : Ri<14, "SP">; def FP : Ri<30, "FP">;
-
 // Floating-point registers
 def F0  : Rf< 0,  "F0">; def F1  : Rf< 1,  "F1">; def F2  : Rf< 2,  "F2">; 
 def F3  : Rf< 3,  "F3">; def F4  : Rf< 4,  "F4">; def F5  : Rf< 5,  "F5">; 
@@ -71,6 +68,14 @@ def D10 : Rd<20, "F20", [F20, F21]>; def D11 : Rd<22, "F22", [F22, F23]>;
 def D12 : Rd<24, "F24", [F24, F25]>; def D13 : Rd<26, "F26", [F26, F27]>; 
 def D14 : Rd<28, "F28", [F28, F29]>; def D15 : Rd<30, "F30", [F30, F31]>;
 
+/// Integer and FP Condition codes.
+let Namespace = "V8" in {
+  def ICC : Register<"ICC">;
+  def FCC : Register<"FCC">;
+}
+def FLAGS_REGS : RegisterClass<"V8", [FlagVT], 32, [ICC, FCC]> {
+    let Size = 32;
+}
 
 // Register classes.
 //
@@ -79,8 +84,10 @@ def D14 : Rd<28, "F28", [F28, F29]>; def D15 : Rd<30, "F30", [F30, F31]>;
 //
 def IntRegs : RegisterClass<"V8", [i32], 32, [L0, L1, L2, L3, L4, L5, L6, L7,
                                      I0, I1, I2, I3, I4, I5,
-                                     G1,
                                      O0, O1, O2, O3, O4, O5, O7,
+
+   // FIXME: G1 reserved for now for large imm generation by frame code.
+                                     G1,
                                      // Non-allocatable regs:
                                      G2, G3, G4, // FIXME: OK for use only in
                                                  // applications, not libraries.
@@ -97,7 +104,8 @@ def IntRegs : RegisterClass<"V8", [i32], 32, [L0, L1, L2, L3, L4, L5, L6, L7,
     IntRegsClass::iterator
     IntRegsClass::allocation_order_end(MachineFunction &MF) const {
       // FIXME: These special regs should be taken out of the regclass!
-      return end()-10;  // Don't allocate special registers
+      return end()-10  // Don't allocate special registers
+         -1;  // FIXME: G1 reserved for large imm generation by frame code.
     }
   }];
 }