-/****************************************************************************
- * File:
- * SchedGraph.cpp
- *
- * Purpose:
- * Scheduling graph based on SSA graph plus extra dependence edges
- * capturing dependences due to machine resources (machine registers,
- * CC registers, and any others).
- *
- * History:
- * 7/20/01 - Vikram Adve - Created
- ***************************************************************************/
+//===- SchedGraph.cpp - Scheduling Graph Implementation -------------------===//
+//
+// Scheduling graph based on SSA graph plus extra dependence edges capturing
+// dependences due to machine resources (machine registers, CC registers, and
+// any others).
+//
+//===----------------------------------------------------------------------===//
#include "SchedGraph.h"
-#include "llvm/InstrTypes.h"
-#include "llvm/Instruction.h"
-#include "llvm/BasicBlock.h"
-#include "llvm/Method.h"
-#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/Target/InstInfo.h"
-#include "llvm/Support/StringExtras.h"
-#include <algorithm>
+#include "llvm/CodeGen/InstrSelection.h"
+#include "llvm/CodeGen/MachineCodeForInstruction.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/Target/MachineRegInfo.h"
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Function.h"
+#include "llvm/iOther.h"
+#include "Support/StringExtras.h"
+#include "Support/STLExtras.h"
+
+using std::vector;
+using std::pair;
+using std::cerr;
+
+//*********************** Internal Data Structures *************************/
+
+// The following two types need to be classes, not typedefs, so we can use
+// opaque declarations in SchedGraph.h
+//
+struct RefVec: public vector<pair<SchedGraphNode*, int> > {
+ typedef vector< pair<SchedGraphNode*, int> >:: iterator iterator;
+ typedef vector< pair<SchedGraphNode*, int> >::const_iterator const_iterator;
+};
+
+struct RegToRefVecMap: public hash_map<int, RefVec> {
+ typedef hash_map<int, RefVec>:: iterator iterator;
+ typedef hash_map<int, RefVec>::const_iterator const_iterator;
+};
+
+struct ValueToDefVecMap: public hash_map<const Instruction*, RefVec> {
+ typedef hash_map<const Instruction*, RefVec>:: iterator iterator;
+ typedef hash_map<const Instruction*, RefVec>::const_iterator const_iterator;
+};
//
// class SchedGraphEdge
SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
SchedGraphNode* _sink,
SchedGraphEdgeDepType _depType,
- DataDepOrderType _depOrderType,
+ unsigned int _depOrderType,
int _minDelay)
: src(_src),
sink(_sink),
depType(_depType),
depOrderType(_depOrderType),
- val(NULL),
- minDelay((_minDelay >= 0)? _minDelay : _src->getLatency())
+ minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
+ val(NULL)
{
+ assert(src != sink && "Self-loop in scheduling graph!");
src->addOutEdge(this);
sink->addInEdge(this);
}
/*ctor*/
-SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
- SchedGraphNode* _sink,
- Value* _val,
- DataDepOrderType _depOrderType,
- int _minDelay)
+SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
+ SchedGraphNode* _sink,
+ const Value* _val,
+ unsigned int _depOrderType,
+ int _minDelay)
: src(_src),
sink(_sink),
- depType(DefUseDep),
+ depType(ValueDep),
depOrderType(_depOrderType),
- val(_val),
- minDelay((_minDelay >= 0)? _minDelay : _src->getLatency())
+ minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
+ val(_val)
{
+ assert(src != sink && "Self-loop in scheduling graph!");
src->addOutEdge(this);
sink->addInEdge(this);
}
/*ctor*/
-SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
- SchedGraphNode* _sink,
- unsigned int _regNum,
- DataDepOrderType _depOrderType,
- int _minDelay)
+SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
+ SchedGraphNode* _sink,
+ unsigned int _regNum,
+ unsigned int _depOrderType,
+ int _minDelay)
: src(_src),
sink(_sink),
depType(MachineRegister),
minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
machineRegNum(_regNum)
{
+ assert(src != sink && "Self-loop in scheduling graph!");
src->addOutEdge(this);
sink->addInEdge(this);
}
SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
SchedGraphNode* _sink,
ResourceId _resourceId,
- int _minDelay)
+ int _minDelay)
: src(_src),
sink(_sink),
depType(MachineResource),
minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
resourceId(_resourceId)
{
+ assert(src != sink && "Self-loop in scheduling graph!");
src->addOutEdge(this);
sink->addInEdge(this);
}
-void SchedGraphEdge::dump(int indent=0) const {
- printIndent(indent); cout << *this;
+/*dtor*/
+SchedGraphEdge::~SchedGraphEdge()
+{
+}
+
+void SchedGraphEdge::dump(int indent) const {
+ cerr << std::string(indent*2, ' ') << *this;
}
//
/*ctor*/
-SchedGraphNode::SchedGraphNode(unsigned int _nodeId,
- const Instruction* _instr,
- const MachineInstr* _minstr,
- const TargetMachine& target)
- : nodeId(_nodeId),
- instr(_instr),
- minstr(_minstr),
- latency(0)
-{
+SchedGraphNode::SchedGraphNode(unsigned NID,
+ MachineBasicBlock *mbb,
+ int indexInBB,
+ const TargetMachine& Target)
+ : nodeId(NID), MBB(mbb), minstr(mbb ? (*mbb)[indexInBB] : 0),
+ origIndexInBB(indexInBB), latency(0) {
if (minstr)
{
MachineOpCode mopCode = minstr->getOpCode();
- latency = target.getInstrInfo().hasResultInterlock(mopCode)
- ? target.getInstrInfo().minLatency(mopCode)
- : target.getInstrInfo().maxLatency(mopCode);
+ latency = Target.getInstrInfo().hasResultInterlock(mopCode)
+ ? Target.getInstrInfo().minLatency(mopCode)
+ : Target.getInstrInfo().maxLatency(mopCode);
}
}
/*dtor*/
SchedGraphNode::~SchedGraphNode()
{
- // a node deletes its outgoing edges only
- for (unsigned i=0, N=outEdges.size(); i < N; i++)
- delete outEdges[i];
+ // for each node, delete its out-edges
+ std::for_each(beginOutEdges(), endOutEdges(),
+ deleter<SchedGraphEdge>);
}
-void SchedGraphNode::dump(int indent=0) const {
- printIndent(indent); cout << *this;
+void SchedGraphNode::dump(int indent) const {
+ cerr << std::string(indent*2, ' ') << *this;
}
SchedGraphNode::removeInEdge(const SchedGraphEdge* edge)
{
assert(edge->getSink() == this);
+
for (iterator I = beginInEdges(); I != endInEdges(); ++I)
if ((*I) == edge)
{
SchedGraphNode::removeOutEdge(const SchedGraphEdge* edge)
{
assert(edge->getSrc() == this);
+
for (iterator I = beginOutEdges(); I != endOutEdges(); ++I)
if ((*I) == edge)
{
}
}
-void
-SchedGraphNode::eraseAllEdges()
-{
- // Disconnect and delete all in-edges and out-edges for the node.
- // Note that we delete the in-edges too since they have been
- // disconnected from the source node and will not be deleted there.
- for (iterator I = beginInEdges(); I != endInEdges(); ++I)
- {
- (*I)->getSrc()->removeOutEdge(*I);
- delete *I;
- }
- for (iterator I = beginOutEdges(); I != endOutEdges(); ++I)
- {
- (*I)->getSink()->removeInEdge(*I);
- delete *I;
- }
- inEdges.clear();
- outEdges.clear();
-}
-
//
// class SchedGraph
/*ctor*/
-SchedGraph::SchedGraph(const BasicBlock* bb,
- const TargetMachine& target)
-{
- bbVec.push_back(bb);
- this->buildGraph(target);
+SchedGraph::SchedGraph(MachineBasicBlock &mbb, const TargetMachine& target)
+ : MBB(mbb) {
+ buildGraph(target);
}
/*dtor*/
SchedGraph::~SchedGraph()
{
- // delete all the nodes. each node deletes its out-edges.
- for (iterator I=begin(); I != end(); ++I)
- delete (*I).second;
+ for (const_iterator I = begin(); I != end(); ++I)
+ delete I->second;
+ delete graphRoot;
+ delete graphLeaf;
}
void
SchedGraph::dump() const
{
- cout << " Sched Graph for Basic Blocks: ";
- for (unsigned i=0, N=bbVec.size(); i < N; i++)
- {
- cout << (bbVec[i]->hasName()? bbVec[i]->getName() : "block")
- << " (" << bbVec[i] << ")"
- << ((i == N-1)? "" : ", ");
- }
+ cerr << " Sched Graph for Basic Block: ";
+ cerr << MBB.getBasicBlock()->getName()
+ << " (" << MBB.getBasicBlock() << ")";
- cout << endl << endl << " Actual Root nodes : ";
+ cerr << "\n\n Actual Root nodes : ";
for (unsigned i=0, N=graphRoot->outEdges.size(); i < N; i++)
- cout << graphRoot->outEdges[i]->getSink()->getNodeId()
+ cerr << graphRoot->outEdges[i]->getSink()->getNodeId()
<< ((i == N-1)? "" : ", ");
- cout << endl << " Graph Nodes:" << endl;
+ cerr << "\n Graph Nodes:\n";
for (const_iterator I=begin(); I != end(); ++I)
- cout << endl << * (*I).second;
+ cerr << "\n" << *I->second;
+
+ cerr << "\n";
+}
+
+
+void
+SchedGraph::eraseIncomingEdges(SchedGraphNode* node, bool addDummyEdges)
+{
+ // Delete and disconnect all in-edges for the node
+ for (SchedGraphNode::iterator I = node->beginInEdges();
+ I != node->endInEdges(); ++I)
+ {
+ SchedGraphNode* srcNode = (*I)->getSrc();
+ srcNode->removeOutEdge(*I);
+ delete *I;
+
+ if (addDummyEdges &&
+ srcNode != getRoot() &&
+ srcNode->beginOutEdges() == srcNode->endOutEdges())
+ { // srcNode has no more out edges, so add an edge to dummy EXIT node
+ assert(node != getLeaf() && "Adding edge that was just removed?");
+ (void) new SchedGraphEdge(srcNode, getLeaf(),
+ SchedGraphEdge::CtrlDep, SchedGraphEdge::NonDataDep, 0);
+ }
+ }
+
+ node->inEdges.clear();
+}
+
+void
+SchedGraph::eraseOutgoingEdges(SchedGraphNode* node, bool addDummyEdges)
+{
+ // Delete and disconnect all out-edges for the node
+ for (SchedGraphNode::iterator I = node->beginOutEdges();
+ I != node->endOutEdges(); ++I)
+ {
+ SchedGraphNode* sinkNode = (*I)->getSink();
+ sinkNode->removeInEdge(*I);
+ delete *I;
+
+ if (addDummyEdges &&
+ sinkNode != getLeaf() &&
+ sinkNode->beginInEdges() == sinkNode->endInEdges())
+ { //sinkNode has no more in edges, so add an edge from dummy ENTRY node
+ assert(node != getRoot() && "Adding edge that was just removed?");
+ (void) new SchedGraphEdge(getRoot(), sinkNode,
+ SchedGraphEdge::CtrlDep, SchedGraphEdge::NonDataDep, 0);
+ }
+ }
- cout << endl;
+ node->outEdges.clear();
+}
+
+void
+SchedGraph::eraseIncidentEdges(SchedGraphNode* node, bool addDummyEdges)
+{
+ this->eraseIncomingEdges(node, addDummyEdges);
+ this->eraseOutgoingEdges(node, addDummyEdges);
}
const TargetMachine& target)
{
const MachineInstrInfo& mii = target.getInstrInfo();
- MachineCodeForVMInstr& termMvec = term->getMachineInstrVec();
+ MachineCodeForInstruction &termMvec = MachineCodeForInstruction::get(term);
// Find the first branch instr in the sequence of machine instrs for term
//
unsigned first = 0;
- while (! mii.isBranch(termMvec[first]->getOpCode()))
+ while (! mii.isBranch(termMvec[first]->getOpCode()) &&
+ ! mii.isReturn(termMvec[first]->getOpCode()))
++first;
assert(first < termMvec.size() &&
- "No branch instructions for BR? Ok, but weird! Delete assertion.");
+ "No branch instructions for terminator? Ok, but weird!");
if (first == termMvec.size())
return;
-
- SchedGraphNode* firstBrNode = this->getGraphNodeForInstr(termMvec[first]);
-
+
+ SchedGraphNode* firstBrNode = getGraphNodeForInstr(termMvec[first]);
+
// Add CD edges from each instruction in the sequence to the
// *last preceding* branch instr. in the sequence
+ // Use a latency of 0 because we only need to prevent out-of-order issue.
//
- for (int i = (int) termMvec.size()-1; i > (int) first; i--)
+ for (unsigned i = termMvec.size(); i > first+1; --i)
{
- SchedGraphNode* toNode = this->getGraphNodeForInstr(termMvec[i]);
- assert(toNode && "No node for instr generated for branch?");
+ SchedGraphNode* toNode = getGraphNodeForInstr(termMvec[i-1]);
+ assert(toNode && "No node for instr generated for branch/ret?");
- for (int j = i-1; j >= 0; j--)
- if (mii.isBranch(termMvec[j]->getOpCode()))
+ for (unsigned j = i-1; j != 0; --j)
+ if (mii.isBranch(termMvec[j-1]->getOpCode()) ||
+ mii.isReturn(termMvec[j-1]->getOpCode()))
{
- SchedGraphNode* brNode = this->getGraphNodeForInstr(termMvec[j]);
- assert(brNode && "No node for instr generated for branch?");
+ SchedGraphNode* brNode = getGraphNodeForInstr(termMvec[j-1]);
+ assert(brNode && "No node for instr generated for branch/ret?");
(void) new SchedGraphEdge(brNode, toNode, SchedGraphEdge::CtrlDep,
SchedGraphEdge::NonDataDep, 0);
break; // only one incoming edge is enough
}
// Add CD edges from each instruction preceding the first branch
- // to the first branch
+ // to the first branch. Use a latency of 0 as above.
//
- for (int i = first-1; i >= 0; i--)
+ for (unsigned i = first; i != 0; --i)
{
- SchedGraphNode* fromNode = this->getGraphNodeForInstr(termMvec[i]);
+ SchedGraphNode* fromNode = getGraphNodeForInstr(termMvec[i-1]);
assert(fromNode && "No node for instr generated for branch?");
(void) new SchedGraphEdge(fromNode, firstBrNode, SchedGraphEdge::CtrlDep,
SchedGraphEdge::NonDataDep, 0);
}
- // Now add CD edges to the first branch instruction in the sequence
- // from all preceding instructions in the basic block.
+ // Now add CD edges to the first branch instruction in the sequence from
+ // all preceding instructions in the basic block. Use 0 latency again.
//
- const BasicBlock* bb = term->getParent();
- for (BasicBlock::const_iterator II = bb->begin(); II != bb->end(); ++II)
+ for (unsigned i=0, N=MBB.size(); i < N; i++)
{
- if ((*II) == (const Instruction*) term) // special case, handled above
- continue;
+ if (MBB[i] == termMvec[first]) // reached the first branch
+ break;
- assert(! (*II)->isTerminator() && "Two terminators in basic block?");
+ SchedGraphNode* fromNode = this->getGraphNodeForInstr(MBB[i]);
+ if (fromNode == NULL)
+ continue; // dummy instruction, e.g., PHI
- const MachineCodeForVMInstr& mvec = (*II)->getMachineInstrVec();
- for (unsigned i=0, N=mvec.size(); i < N; i++)
- {
- SchedGraphNode* fromNode = this->getGraphNodeForInstr(mvec[i]);
- if (fromNode == NULL)
- continue; // dummy instruction, e.g., PHI
-
- (void) new SchedGraphEdge(fromNode, firstBrNode,
- SchedGraphEdge::CtrlDep,
- SchedGraphEdge::NonDataDep, 0);
-
- // If we find any other machine instructions (other than due to
- // the terminator) that also have delay slots, add an outgoing edge
- // from the instruction to the instructions in the delay slots.
- //
- unsigned d = mii.getNumDelaySlots(mvec[i]->getOpCode());
- assert(i+d < N && "Insufficient delay slots for instruction?");
-
- for (unsigned j=1; j <= d; j++)
- {
- SchedGraphNode* toNode = this->getGraphNodeForInstr(mvec[i+j]);
- assert(toNode && "No node for machine instr in delay slot?");
- (void) new SchedGraphEdge(fromNode, toNode,
- SchedGraphEdge::CtrlDep,
- SchedGraphEdge::NonDataDep, 0);
- }
- }
+ (void) new SchedGraphEdge(fromNode, firstBrNode,
+ SchedGraphEdge::CtrlDep,
+ SchedGraphEdge::NonDataDep, 0);
+
+ // If we find any other machine instructions (other than due to
+ // the terminator) that also have delay slots, add an outgoing edge
+ // from the instruction to the instructions in the delay slots.
+ //
+ unsigned d = mii.getNumDelaySlots(MBB[i]->getOpCode());
+ assert(i+d < N && "Insufficient delay slots for instruction?");
+
+ for (unsigned j=1; j <= d; j++)
+ {
+ SchedGraphNode* toNode = this->getGraphNodeForInstr(MBB[i+j]);
+ assert(toNode && "No node for machine instr in delay slot?");
+ (void) new SchedGraphEdge(fromNode, toNode,
+ SchedGraphEdge::CtrlDep,
+ SchedGraphEdge::NonDataDep, 0);
+ }
}
}
+static const int SG_LOAD_REF = 0;
+static const int SG_STORE_REF = 1;
+static const int SG_CALL_REF = 2;
+
+static const unsigned int SG_DepOrderArray[][3] = {
+ { SchedGraphEdge::NonDataDep,
+ SchedGraphEdge::AntiDep,
+ SchedGraphEdge::AntiDep },
+ { SchedGraphEdge::TrueDep,
+ SchedGraphEdge::OutputDep,
+ SchedGraphEdge::TrueDep | SchedGraphEdge::OutputDep },
+ { SchedGraphEdge::TrueDep,
+ SchedGraphEdge::AntiDep | SchedGraphEdge::OutputDep,
+ SchedGraphEdge::TrueDep | SchedGraphEdge::AntiDep
+ | SchedGraphEdge::OutputDep }
+};
+
+// Add a dependence edge between every pair of machine load/store/call
+// instructions, where at least one is a store or a call.
+// Use latency 1 just to ensure that memory operations are ordered;
+// latency does not otherwise matter (true dependences enforce that).
+//
void
-SchedGraph::addMemEdges(const vector<const Instruction*>& memVec,
+SchedGraph::addMemEdges(const vector<SchedGraphNode*>& memNodeVec,
const TargetMachine& target)
{
const MachineInstrInfo& mii = target.getInstrInfo();
- for (unsigned im=0, NM=memVec.size(); im < NM; im++)
+ // Instructions in memNodeVec are in execution order within the basic block,
+ // so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
+ //
+ for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++)
{
- const Instruction* fromInstr = memVec[im];
- bool fromIsLoad = fromInstr->getOpcode() == Instruction::Load;
-
+ MachineOpCode fromOpCode = memNodeVec[im]->getOpCode();
+ int fromType = mii.isCall(fromOpCode)? SG_CALL_REF
+ : mii.isLoad(fromOpCode)? SG_LOAD_REF
+ : SG_STORE_REF;
for (unsigned jm=im+1; jm < NM; jm++)
{
- const Instruction* toInstr = memVec[jm];
- bool toIsLoad = toInstr->getOpcode() == Instruction::Load;
- SchedGraphEdge::DataDepOrderType depOrderType;
-
- if (fromIsLoad)
- {
- if (toIsLoad) continue; // both instructions are loads
- depOrderType = SchedGraphEdge::AntiDep;
- }
- else
- {
- depOrderType = (toIsLoad)? SchedGraphEdge::TrueDep
- : SchedGraphEdge::OutputDep;
- }
-
- MachineCodeForVMInstr& fromInstrMvec=fromInstr->getMachineInstrVec();
- MachineCodeForVMInstr& toInstrMvec = toInstr->getMachineInstrVec();
-
- // We have two VM memory instructions, and at least one is a store.
- // Add edges between all machine load/store instructions.
- //
- for (unsigned i=0, N=fromInstrMvec.size(); i < N; i++)
- {
- MachineOpCode fromOpCode = fromInstrMvec[i]->getOpCode();
- if (mii.isLoad(fromOpCode) || mii.isStore(fromOpCode))
- {
- SchedGraphNode* fromNode =
- this->getGraphNodeForInstr(fromInstrMvec[i]);
- assert(fromNode && "No node for memory instr?");
-
- for (unsigned j=0, M=toInstrMvec.size(); j < M; j++)
- {
- MachineOpCode toOpCode = toInstrMvec[j]->getOpCode();
- if (mii.isLoad(toOpCode) || mii.isStore(toOpCode))
- {
- SchedGraphNode* toNode =
- this->getGraphNodeForInstr(toInstrMvec[j]);
- assert(toNode && "No node for memory instr?");
-
- (void) new SchedGraphEdge(fromNode, toNode,
- SchedGraphEdge::MemoryDep,
- depOrderType, 1);
- }
- }
- }
- }
- }
+ MachineOpCode toOpCode = memNodeVec[jm]->getOpCode();
+ int toType = mii.isCall(toOpCode)? SG_CALL_REF
+ : mii.isLoad(toOpCode)? SG_LOAD_REF
+ : SG_STORE_REF;
+
+ if (fromType != SG_LOAD_REF || toType != SG_LOAD_REF)
+ (void) new SchedGraphEdge(memNodeVec[im], memNodeVec[jm],
+ SchedGraphEdge::MemoryDep,
+ SG_DepOrderArray[fromType][toType], 1);
+ }
}
-}
-
+}
-typedef vector< pair<SchedGraphNode*, unsigned int> > RegRefVec;
-
-// The following needs to be a class, not a typedef, so we can use
-// an opaque declaration in SchedGraph.h
-class NodeToRegRefMap: public hash_map<int, RegRefVec> {
- typedef hash_map<int, RegRefVec>:: iterator iterator;
- typedef hash_map<int, RegRefVec>::const_iterator const_iterator;
-};
+// Add edges from/to CC reg instrs to/from call instrs.
+// Essentially this prevents anything that sets or uses a CC reg from being
+// reordered w.r.t. a call.
+// Use a latency of 0 because we only need to prevent out-of-order issue,
+// like with control dependences.
+//
+void
+SchedGraph::addCallCCEdges(const vector<SchedGraphNode*>& memNodeVec,
+ MachineBasicBlock& bbMvec,
+ const TargetMachine& target)
+{
+ const MachineInstrInfo& mii = target.getInstrInfo();
+ vector<SchedGraphNode*> callNodeVec;
+
+ // Find the call instruction nodes and put them in a vector.
+ for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++)
+ if (mii.isCall(memNodeVec[im]->getOpCode()))
+ callNodeVec.push_back(memNodeVec[im]);
+
+ // Now walk the entire basic block, looking for CC instructions *and*
+ // call instructions, and keep track of the order of the instructions.
+ // Use the call node vec to quickly find earlier and later call nodes
+ // relative to the current CC instruction.
+ //
+ int lastCallNodeIdx = -1;
+ for (unsigned i=0, N=bbMvec.size(); i < N; i++)
+ if (mii.isCall(bbMvec[i]->getOpCode()))
+ {
+ ++lastCallNodeIdx;
+ for ( ; lastCallNodeIdx < (int)callNodeVec.size(); ++lastCallNodeIdx)
+ if (callNodeVec[lastCallNodeIdx]->getMachineInstr() == bbMvec[i])
+ break;
+ assert(lastCallNodeIdx < (int)callNodeVec.size() && "Missed Call?");
+ }
+ else if (mii.isCCInstr(bbMvec[i]->getOpCode()))
+ { // Add incoming/outgoing edges from/to preceding/later calls
+ SchedGraphNode* ccNode = this->getGraphNodeForInstr(bbMvec[i]);
+ int j=0;
+ for ( ; j <= lastCallNodeIdx; j++)
+ (void) new SchedGraphEdge(callNodeVec[j], ccNode,
+ MachineCCRegsRID, 0);
+ for ( ; j < (int) callNodeVec.size(); j++)
+ (void) new SchedGraphEdge(ccNode, callNodeVec[j],
+ MachineCCRegsRID, 0);
+ }
+}
void
-SchedGraph::addMachineRegEdges(NodeToRegRefMap& regToRefVecMap,
+SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap,
const TargetMachine& target)
{
- assert(bbVec.size() == 1 && "Only handling a single basic block here");
-
// This assumes that such hardwired registers are never allocated
// to any LLVM value (since register allocation happens later), i.e.,
// any uses or defs of this register have been made explicit!
// Also assumes that two registers with different numbers are
// not aliased!
//
- for (NodeToRegRefMap::iterator I = regToRefVecMap.begin();
+ for (RegToRefVecMap::iterator I = regToRefVecMap.begin();
I != regToRefVecMap.end(); ++I)
{
- int regNum = (*I).first;
- RegRefVec& regRefVec = (*I).second;
+ int regNum = (*I).first;
+ RefVec& regRefVec = (*I).second;
// regRefVec is ordered by control flow order in the basic block
- int lastDefIdx = -1;
for (unsigned i=0; i < regRefVec.size(); ++i)
{
SchedGraphNode* node = regRefVec[i].first;
- bool isDef = regRefVec[i].second;
-
- if (isDef)
- { // Each def gets an output edge from the last def
- if (lastDefIdx > 0)
- new SchedGraphEdge(regRefVec[lastDefIdx].first, node, regNum,
- SchedGraphEdge::OutputDep);
-
- // Also, an anti edge from all uses *since* the last def,
- // But don't add edge from an instruction to itself!
- for (int u = 1 + lastDefIdx; u < (int) i; u++)
- if (regRefVec[u].first != node)
- new SchedGraphEdge(regRefVec[u].first, node, regNum,
- SchedGraphEdge::AntiDep);
- }
- else
- { // Each use gets a true edge from the last def
- if (lastDefIdx > 0)
- new SchedGraphEdge(regRefVec[lastDefIdx].first, node, regNum);
- }
- }
+ unsigned int opNum = regRefVec[i].second;
+ bool isDef = node->getMachineInstr()->operandIsDefined(opNum);
+ bool isDefAndUse =
+ node->getMachineInstr()->operandIsDefinedAndUsed(opNum);
+
+ for (unsigned p=0; p < i; ++p)
+ {
+ SchedGraphNode* prevNode = regRefVec[p].first;
+ if (prevNode != node)
+ {
+ unsigned int prevOpNum = regRefVec[p].second;
+ bool prevIsDef =
+ prevNode->getMachineInstr()->operandIsDefined(prevOpNum);
+ bool prevIsDefAndUse =
+ prevNode->getMachineInstr()->operandIsDefinedAndUsed(prevOpNum);
+ if (isDef)
+ {
+ if (prevIsDef)
+ new SchedGraphEdge(prevNode, node, regNum,
+ SchedGraphEdge::OutputDep);
+ if (!prevIsDef || prevIsDefAndUse)
+ new SchedGraphEdge(prevNode, node, regNum,
+ SchedGraphEdge::AntiDep);
+ }
+
+ if (prevIsDef)
+ if (!isDef || isDefAndUse)
+ new SchedGraphEdge(prevNode, node, regNum,
+ SchedGraphEdge::TrueDep);
+ }
+ }
+ }
}
}
+// Adds dependences to/from refNode from/to all other defs
+// in the basic block. refNode may be a use, a def, or both.
+// We do not consider other uses because we are not building use-use deps.
+//
void
-SchedGraph::addSSAEdge(SchedGraphNode* node,
- Value* val,
- const TargetMachine& target)
+SchedGraph::addEdgesForValue(SchedGraphNode* refNode,
+ const RefVec& defVec,
+ const Value* defValue,
+ bool refNodeIsDef,
+ bool refNodeIsDefAndUse,
+ const TargetMachine& target)
{
- if (!val->isInstruction()) return;
-
- const Instruction* thisVMInstr = node->getInstr();
- const Instruction* defVMInstr = (const Instruction*) val;
-
- // Phi instructions are the only ones that produce a value but don't get
- // any non-dummy machine instructions. Return here as an optimization.
- //
- if (defVMInstr->isPHINode())
- return;
-
- // Now add the graph edge for the appropriate machine instruction(s).
- // Note that multiple machine instructions generated for the
- // def VM instruction may modify the register for the def value.
- //
- MachineCodeForVMInstr& defMvec = defVMInstr->getMachineInstrVec();
- const MachineInstrInfo& mii = target.getInstrInfo();
+ bool refNodeIsUse = !refNodeIsDef || refNodeIsDefAndUse;
- for (unsigned i=0, N=defMvec.size(); i < N; i++)
- for (int o=0, N = mii.getNumOperands(defMvec[i]->getOpCode()); o < N; o++)
- {
- const MachineOperand& defOp = defMvec[i]->getOperand(o);
-
- if (defOp.opIsDef()
- && (defOp.getOperandType() == MachineOperand::MO_VirtualRegister
- || defOp.getOperandType() == MachineOperand::MO_CCRegister)
- && (defOp.getVRegValue() == val))
- {
- // this instruction does define value `val'.
- // if there is a node for it in the same graph, add an edge.
- SchedGraphNode* defNode = this->getGraphNodeForInstr(defMvec[i]);
- if (defNode != NULL)
- (void) new SchedGraphEdge(defNode, node, val);
- }
- }
+ // Add true or output dep edges from all def nodes before refNode in BB.
+ // Add anti or output dep edges to all def nodes after refNode.
+ for (RefVec::const_iterator I=defVec.begin(), E=defVec.end(); I != E; ++I)
+ {
+ if ((*I).first == refNode)
+ continue; // Dont add any self-loops
+
+ if ((*I).first->getOrigIndexInBB() < refNode->getOrigIndexInBB())
+ { // (*).first is before refNode
+ if (refNodeIsDef)
+ (void) new SchedGraphEdge((*I).first, refNode, defValue,
+ SchedGraphEdge::OutputDep);
+ if (refNodeIsUse)
+ (void) new SchedGraphEdge((*I).first, refNode, defValue,
+ SchedGraphEdge::TrueDep);
+ }
+ else
+ { // (*).first is after refNode
+ if (refNodeIsDef)
+ (void) new SchedGraphEdge(refNode, (*I).first, defValue,
+ SchedGraphEdge::OutputDep);
+ if (refNodeIsUse)
+ (void) new SchedGraphEdge(refNode, (*I).first, defValue,
+ SchedGraphEdge::AntiDep);
+ }
+ }
}
void
-SchedGraph::addEdgesForInstruction(SchedGraphNode* node,
- NodeToRegRefMap& regToRefVecMap,
+SchedGraph::addEdgesForInstruction(const MachineInstr& MI,
+ const ValueToDefVecMap& valueToDefVecMap,
const TargetMachine& target)
{
- const Instruction& instr = * node->getInstr(); // No dummy nodes here!
- const MachineInstr& minstr = * node->getMachineInstr();
+ SchedGraphNode* node = getGraphNodeForInstr(&MI);
+ if (node == NULL)
+ return;
- // Add incoming edges for the following:
- // (1) operands of the machine instruction, including hidden operands
- // (2) machine register dependences
- // (3) other resource dependences for the machine instruction, if any
- // Also, note any uses or defs of machine registers.
+ // Add edges for all operands of the machine instruction.
//
- for (unsigned i=0, numOps=minstr.getNumOperands(); i < numOps; i++)
+ for (unsigned i = 0, numOps = MI.getNumOperands(); i != numOps; ++i)
{
- const MachineOperand& mop = minstr.getOperand(i);
-
- // if this writes to a machine register other than the hardwired
- // "zero" register used on many processors, record the reference.
- if (mop.getOperandType() == MachineOperand::MO_MachineRegister
- && (! (target.zeroRegNum >= 0
- && mop.getMachineRegNum()==(unsigned) target.zeroRegNum)))
- {
- regToRefVecMap[mop.getMachineRegNum()].
- push_back(make_pair(node, i));
- }
-
- // ignore all other def operands
- if (minstr.operandIsDefined(i))
- continue;
-
- switch(mop.getOperandType())
+ switch (MI.getOperandType(i))
{
case MachineOperand::MO_VirtualRegister:
case MachineOperand::MO_CCRegister:
- if (mop.getVRegValue())
- addSSAEdge(node, mop.getVRegValue(), target);
+ if (const Instruction* srcI =
+ dyn_cast_or_null<Instruction>(MI.getOperand(i).getVRegValue()))
+ {
+ ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
+ if (I != valueToDefVecMap.end())
+ addEdgesForValue(node, I->second, srcI,
+ MI.operandIsDefined(i),
+ MI.operandIsDefinedAndUsed(i), target);
+ }
break;
case MachineOperand::MO_MachineRegister:
}
}
- // add all true, anti,
- // and output dependences for this register. but ignore
+ // Add edges for values implicitly used by the machine instruction.
+ // Examples include function arguments to a Call instructions or the return
+ // value of a Ret instruction.
+ //
+ for (unsigned i=0, N=MI.getNumImplicitRefs(); i < N; ++i)
+ if (! MI.implicitRefIsDefined(i) ||
+ MI.implicitRefIsDefinedAndUsed(i))
+ if (const Instruction *srcI =
+ dyn_cast_or_null<Instruction>(MI.getImplicitRef(i)))
+ {
+ ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
+ if (I != valueToDefVecMap.end())
+ addEdgesForValue(node, I->second, srcI,
+ MI.implicitRefIsDefined(i),
+ MI.implicitRefIsDefinedAndUsed(i), target);
+ }
+}
+
+void
+SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
+ SchedGraphNode* node,
+ vector<SchedGraphNode*>& memNodeVec,
+ RegToRefVecMap& regToRefVecMap,
+ ValueToDefVecMap& valueToDefVecMap)
+{
+ const MachineInstrInfo& mii = target.getInstrInfo();
+
+
+ MachineOpCode opCode = node->getOpCode();
+ if (mii.isLoad(opCode) || mii.isStore(opCode) || mii.isCall(opCode))
+ memNodeVec.push_back(node);
+
+ // Collect the register references and value defs. for explicit operands
+ //
+ const MachineInstr& minstr = *node->getMachineInstr();
+ for (int i=0, numOps = (int) minstr.getNumOperands(); i < numOps; i++)
+ {
+ const MachineOperand& mop = minstr.getOperand(i);
+
+ // if this references a register other than the hardwired
+ // "zero" register, record the reference.
+ if (mop.getType() == MachineOperand::MO_MachineRegister)
+ {
+ int regNum = mop.getMachineRegNum();
+ if (regNum != target.getRegInfo().getZeroRegNum())
+ regToRefVecMap[mop.getMachineRegNum()].push_back(
+ std::make_pair(node, i));
+ continue; // nothing more to do
+ }
+
+ // ignore all other non-def operands
+ if (! minstr.operandIsDefined(i))
+ continue;
+
+ // We must be defining a value.
+ assert((mop.getType() == MachineOperand::MO_VirtualRegister ||
+ mop.getType() == MachineOperand::MO_CCRegister)
+ && "Do not expect any other kind of operand to be defined!");
+
+ const Instruction* defInstr = cast<Instruction>(mop.getVRegValue());
+ valueToDefVecMap[defInstr].push_back(std::make_pair(node, i));
+ }
+
+ //
+ // Collect value defs. for implicit operands. The interface to extract
+ // them assumes they must be virtual registers!
+ //
+ for (unsigned i=0, N = minstr.getNumImplicitRefs(); i != N; ++i)
+ if (minstr.implicitRefIsDefined(i))
+ if (const Instruction* defInstr =
+ dyn_cast_or_null<Instruction>(minstr.getImplicitRef(i)))
+ valueToDefVecMap[defInstr].push_back(std::make_pair(node, -i));
}
void
-SchedGraph::buildGraph(const TargetMachine& target)
+SchedGraph::buildNodesForBB(const TargetMachine& target,
+ MachineBasicBlock& MBB,
+ vector<SchedGraphNode*>& memNodeVec,
+ RegToRefVecMap& regToRefVecMap,
+ ValueToDefVecMap& valueToDefVecMap)
{
const MachineInstrInfo& mii = target.getInstrInfo();
- const BasicBlock* bb = bbVec[0];
- assert(bbVec.size() == 1 && "Only handling a single basic block here");
+ // Build graph nodes for each VM instruction and gather def/use info.
+ // Do both those together in a single pass over all machine instructions.
+ for (unsigned i=0; i < MBB.size(); i++)
+ if (!mii.isDummyPhiInstr(MBB[i]->getOpCode())) {
+ SchedGraphNode* node = new SchedGraphNode(getNumNodes(), &MBB, i, target);
+ noteGraphNodeForInstr(MBB[i], node);
+
+ // Remember all register references and value defs
+ findDefUseInfoAtInstr(target, node, memNodeVec, regToRefVecMap,
+ valueToDefVecMap);
+ }
+}
+
+
+void
+SchedGraph::buildGraph(const TargetMachine& target)
+{
+ // Use this data structure to note all machine operands that compute
+ // ordinary LLVM values. These must be computed defs (i.e., instructions).
+ // Note that there may be multiple machine instructions that define
+ // each Value.
+ ValueToDefVecMap valueToDefVecMap;
- // Use this data structures to note all LLVM memory instructions.
+ // Use this data structure to note all memory instructions.
// We use this to add memory dependence edges without a second full walk.
//
- vector<const Instruction*> memVec;
+ // vector<const Instruction*> memVec;
+ vector<SchedGraphNode*> memNodeVec;
- // Use this data structures to note any uses or definitions of
+ // Use this data structure to note any uses or definitions of
// machine registers so we can add edges for those later without
// extra passes over the nodes.
// The vector holds an ordered list of references to the machine reg,
// single basic block, hence the assertion. Each reference is identified
// by the pair: <node, operand-number>.
//
- NodeToRegRefMap regToRefVecMap;
+ RegToRefVecMap regToRefVecMap;
// Make a dummy root node. We'll add edges to the real roots later.
- graphRoot = new SchedGraphNode(0, NULL, NULL, target);
- graphLeaf = new SchedGraphNode(1, NULL, NULL, target);
+ graphRoot = new SchedGraphNode(0, NULL, -1, target);
+ graphLeaf = new SchedGraphNode(1, NULL, -1, target);
//----------------------------------------------------------------
- // First add nodes for all the machine instructions in the basic block.
- // This greatly simplifies identifing which edges to add.
+ // First add nodes for all the machine instructions in the basic block
+ // because this greatly simplifies identifying which edges to add.
+ // Do this one VM instruction at a time since the SchedGraphNode needs that.
// Also, remember the load/store instructions to add memory deps later.
//----------------------------------------------------------------
-
- for (BasicBlock::const_iterator II = bb->begin(); II != bb->end(); ++II)
- {
- const Instruction *instr = *II;
- const MachineCodeForVMInstr& mvec = instr->getMachineInstrVec();
- for (unsigned i=0, N=mvec.size(); i < N; i++)
- if (! mii.isDummyPhiInstr(mvec[i]->getOpCode()))
- {
- SchedGraphNode* node = new SchedGraphNode(getNumNodes(),
- instr, mvec[i], target);
- this->noteGraphNodeForInstr(mvec[i], node);
- }
-
- if (instr->getOpcode() == Instruction::Load ||
- instr->getOpcode() == Instruction::Store)
- memVec.push_back(instr);
- }
+
+ buildNodesForBB(target, MBB, memNodeVec, regToRefVecMap, valueToDefVecMap);
//----------------------------------------------------------------
- // Now add the edges.
+ // Now add edges for the following (all are incoming edges except (4)):
+ // (1) operands of the machine instruction, including hidden operands
+ // (2) machine register dependences
+ // (3) memory load/store dependences
+ // (3) other resource dependences for the machine instruction, if any
+ // (4) output dependences when multiple machine instructions define the
+ // same value; all must have been generated from a single VM instrn
+ // (5) control dependences to branch instructions generated for the
+ // terminator instruction of the BB. Because of delay slots and
+ // 2-way conditional branches, multiple CD edges are needed
+ // (see addCDEdges for details).
+ // Also, note any uses or defs of machine registers.
+ //
//----------------------------------------------------------------
// First, add edges to the terminator instruction of the basic block.
- this->addCDEdges(bb->getTerminator(), target);
-
- // Then add memory dep edges: store->load, load->store, and store->store
- this->addMemEdges(memVec, target);
+ this->addCDEdges(MBB.getBasicBlock()->getTerminator(), target);
- // Then add other edges for all instructions in the block.
- for (SchedGraph::iterator GI = this->begin(); GI != this->end(); ++GI)
- {
- SchedGraphNode* node = (*GI).second;
- addEdgesForInstruction(node, regToRefVecMap, target);
- }
+ // Then add memory dep edges: store->load, load->store, and store->store.
+ // Call instructions are treated as both load and store.
+ this->addMemEdges(memNodeVec, target);
+
+ // Then add edges between call instructions and CC set/use instructions
+ this->addCallCCEdges(memNodeVec, MBB, target);
+
+ // Then add incoming def-use (SSA) edges for each machine instruction.
+ for (unsigned i=0, N=MBB.size(); i < N; i++)
+ addEdgesForInstruction(*MBB[i], valueToDefVecMap, target);
+
+#ifdef NEED_SEPARATE_NONSSA_EDGES_CODE
+ // Then add non-SSA edges for all VM instructions in the block.
+ // We assume that all machine instructions that define a value are
+ // generated from the VM instruction corresponding to that value.
+ // TODO: This could probably be done much more efficiently.
+ for (BasicBlock::const_iterator II = bb->begin(); II != bb->end(); ++II)
+ this->addNonSSAEdgesForValue(*II, target);
+#endif //NEED_SEPARATE_NONSSA_EDGES_CODE
// Then add edges for dependences on machine registers
this->addMachineRegEdges(regToRefVecMap, target);
//
/*ctor*/
-SchedGraphSet::SchedGraphSet(const Method* _method,
+SchedGraphSet::SchedGraphSet(const Function* _function,
const TargetMachine& target) :
- method(_method)
+ method(_function)
{
buildGraphsForMethod(method, target);
}
SchedGraphSet::~SchedGraphSet()
{
// delete all the graphs
- for (iterator I=begin(); I != end(); ++I)
- delete (*I).second;
+ for(iterator I = begin(), E = end(); I != E; ++I)
+ delete *I; // destructor is a friend
}
void
SchedGraphSet::dump() const
{
- cout << "======== Sched graphs for method `"
- << (method->hasName()? method->getName() : "???")
- << "' ========" << endl << endl;
+ cerr << "======== Sched graphs for function `" << method->getName()
+ << "' ========\n\n";
for (const_iterator I=begin(); I != end(); ++I)
- (*I).second->dump();
+ (*I)->dump();
- cout << endl << "====== End graphs for method `"
- << (method->hasName()? method->getName() : "")
- << "' ========" << endl << endl;
+ cerr << "\n====== End graphs for function `" << method->getName()
+ << "' ========\n\n";
}
void
-SchedGraphSet::buildGraphsForMethod(const Method *method,
+SchedGraphSet::buildGraphsForMethod(const Function *F,
const TargetMachine& target)
{
- for (Method::const_iterator BI = method->begin(); BI != method->end(); ++BI)
- {
- SchedGraph* graph = new SchedGraph(*BI, target);
- this->noteGraphForBlock(*BI, graph);
- }
+ MachineFunction &MF = MachineFunction::get(F);
+ for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
+ addGraph(new SchedGraph(*I, target));
}
-
-ostream&
-operator<<(ostream& os, const SchedGraphEdge& edge)
+std::ostream &operator<<(std::ostream &os, const SchedGraphEdge& edge)
{
os << "edge [" << edge.src->getNodeId() << "] -> ["
<< edge.sink->getNodeId() << "] : ";
switch(edge.depType) {
case SchedGraphEdge::CtrlDep: os<< "Control Dep"; break;
- case SchedGraphEdge::DefUseDep: os<< "Reg Value " << edge.val; break;
- case SchedGraphEdge::MemoryDep: os<< "Mem Value " << edge.val; break;
+ case SchedGraphEdge::ValueDep: os<< "Reg Value " << edge.val; break;
+ case SchedGraphEdge::MemoryDep: os<< "Memory Dep"; break;
case SchedGraphEdge::MachineRegister: os<< "Reg " <<edge.machineRegNum;break;
case SchedGraphEdge::MachineResource: os<<"Resource "<<edge.resourceId;break;
default: assert(0); break;
}
- os << " : delay = " << edge.minDelay << endl;
+ os << " : delay = " << edge.minDelay << "\n";
return os;
}
-ostream&
-operator<<(ostream& os, const SchedGraphNode& node)
+std::ostream &operator<<(std::ostream &os, const SchedGraphNode& node)
{
- printIndent(4, os);
- os << "Node " << node.nodeId << " : "
- << "latency = " << node.latency << endl;
-
- printIndent(6, os);
+ os << std::string(8, ' ')
+ << "Node " << node.nodeId << " : "
+ << "latency = " << node.latency << "\n" << std::string(12, ' ');
if (node.getMachineInstr() == NULL)
- os << "(Dummy node)" << endl;
+ os << "(Dummy node)\n";
else
{
- os << *node.getMachineInstr() << endl;
-
- printIndent(6, os);
- os << node.inEdges.size() << " Incoming Edges:" << endl;
+ os << *node.getMachineInstr() << "\n" << std::string(12, ' ');
+ os << node.inEdges.size() << " Incoming Edges:\n";
for (unsigned i=0, N=node.inEdges.size(); i < N; i++)
- {
- printIndent(8, os);
- os << * node.inEdges[i];
- }
+ os << std::string(16, ' ') << *node.inEdges[i];
- printIndent(6, os);
- os << node.outEdges.size() << " Outgoing Edges:" << endl;
+ os << std::string(12, ' ') << node.outEdges.size()
+ << " Outgoing Edges:\n";
for (unsigned i=0, N=node.outEdges.size(); i < N; i++)
- {
- printIndent(8, os);
- os << * node.outEdges[i];
- }
+ os << std::string(16, ' ') << *node.outEdges[i];
}
return os;
projects / oota-llvm.git / blobdiff