-// $Id$
-//***************************************************************************
-// File:
-// SchedGraph.cpp
-//
-// Purpose:
-// Scheduling graph based on SSA graph plus extra dependence edges
-// capturing dependences due to machine resources (machine registers,
-// CC registers, and any others).
-//
-// History:
-// 7/20/01 - Vikram Adve - Created
-//**************************************************************************/
+//===- SchedGraph.cpp - Scheduling Graph Implementation -------------------===//
+//
+// Scheduling graph based on SSA graph plus extra dependence edges capturing
+// dependences due to machine resources (machine registers, CC registers, and
+// any others).
+//
+//===----------------------------------------------------------------------===//
#include "SchedGraph.h"
-#include "llvm/InstrTypes.h"
-#include "llvm/Instruction.h"
-#include "llvm/BasicBlock.h"
-#include "llvm/Method.h"
-#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/InstrSelection.h"
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/CodeGen/MachineCodeForInstruction.h"
+#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Target/MachineRegInfo.h"
-#include "llvm/Support/StringExtras.h"
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Function.h"
#include "llvm/iOther.h"
-#include <algorithm>
-#include <hash_map>
-#include <vector>
+#include "Support/StringExtras.h"
+#include "Support/STLExtras.h"
+using std::vector;
+using std::pair;
+using std::cerr;
//*********************** Internal Data Structures *************************/
// The following two types need to be classes, not typedefs, so we can use
// opaque declarations in SchedGraph.h
//
-struct RefVec: public vector< pair<SchedGraphNode*, int> > {
+struct RefVec: public vector<pair<SchedGraphNode*, int> > {
typedef vector< pair<SchedGraphNode*, int> >:: iterator iterator;
typedef vector< pair<SchedGraphNode*, int> >::const_iterator const_iterator;
};
minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
val(NULL)
{
+ assert(src != sink && "Self-loop in scheduling graph!");
src->addOutEdge(this);
sink->addInEdge(this);
}
int _minDelay)
: src(_src),
sink(_sink),
- depType(DefUseDep),
+ depType(ValueDep),
depOrderType(_depOrderType),
minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
val(_val)
{
+ assert(src != sink && "Self-loop in scheduling graph!");
src->addOutEdge(this);
sink->addInEdge(this);
}
minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
machineRegNum(_regNum)
{
+ assert(src != sink && "Self-loop in scheduling graph!");
src->addOutEdge(this);
sink->addInEdge(this);
}
minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
resourceId(_resourceId)
{
+ assert(src != sink && "Self-loop in scheduling graph!");
src->addOutEdge(this);
sink->addInEdge(this);
}
{
}
-void SchedGraphEdge::dump(int indent=0) const {
- printIndent(indent); cout << *this;
+void SchedGraphEdge::dump(int indent) const {
+ cerr << std::string(indent*2, ' ') << *this;
}
//
/*ctor*/
-SchedGraphNode::SchedGraphNode(unsigned int _nodeId,
- const Instruction* _instr,
- const MachineInstr* _minstr,
- const TargetMachine& target)
- : nodeId(_nodeId),
- instr(_instr),
- minstr(_minstr),
- latency(0)
-{
+SchedGraphNode::SchedGraphNode(unsigned NID,
+ MachineBasicBlock *mbb,
+ int indexInBB,
+ const TargetMachine& Target)
+ : nodeId(NID), MBB(mbb), minstr(mbb ? (*mbb)[indexInBB] : 0),
+ origIndexInBB(indexInBB), latency(0) {
if (minstr)
{
MachineOpCode mopCode = minstr->getOpCode();
- latency = target.getInstrInfo().hasResultInterlock(mopCode)
- ? target.getInstrInfo().minLatency(mopCode)
- : target.getInstrInfo().maxLatency(mopCode);
+ latency = Target.getInstrInfo().hasResultInterlock(mopCode)
+ ? Target.getInstrInfo().minLatency(mopCode)
+ : Target.getInstrInfo().maxLatency(mopCode);
}
}
/*dtor*/
SchedGraphNode::~SchedGraphNode()
{
+ // for each node, delete its out-edges
+ std::for_each(beginOutEdges(), endOutEdges(),
+ deleter<SchedGraphEdge>);
}
-void SchedGraphNode::dump(int indent=0) const {
- printIndent(indent); cout << *this;
+void SchedGraphNode::dump(int indent) const {
+ cerr << std::string(indent*2, ' ') << *this;
}
/*ctor*/
-SchedGraph::SchedGraph(const BasicBlock* bb,
- const TargetMachine& target)
-{
- bbVec.push_back(bb);
- this->buildGraph(target);
+SchedGraph::SchedGraph(MachineBasicBlock &mbb, const TargetMachine& target)
+ : MBB(mbb) {
+ buildGraph(target);
}
/*dtor*/
SchedGraph::~SchedGraph()
{
- for (iterator I=begin(); I != end(); ++I)
- {
- SchedGraphNode* node = (*I).second;
-
- // for each node, delete its out-edges
- for (SchedGraphNode::iterator I = node->beginOutEdges();
- I != node->endOutEdges(); ++I)
- delete *I;
-
- // then delete the node itself.
- delete node;
- }
+ for (const_iterator I = begin(); I != end(); ++I)
+ delete I->second;
+ delete graphRoot;
+ delete graphLeaf;
}
void
SchedGraph::dump() const
{
- cout << " Sched Graph for Basic Blocks: ";
- for (unsigned i=0, N=bbVec.size(); i < N; i++)
- {
- cout << (bbVec[i]->hasName()? bbVec[i]->getName() : "block")
- << " (" << bbVec[i] << ")"
- << ((i == N-1)? "" : ", ");
- }
+ cerr << " Sched Graph for Basic Block: ";
+ cerr << MBB.getBasicBlock()->getName()
+ << " (" << MBB.getBasicBlock() << ")";
- cout << endl << endl << " Actual Root nodes : ";
+ cerr << "\n\n Actual Root nodes : ";
for (unsigned i=0, N=graphRoot->outEdges.size(); i < N; i++)
- cout << graphRoot->outEdges[i]->getSink()->getNodeId()
+ cerr << graphRoot->outEdges[i]->getSink()->getNodeId()
<< ((i == N-1)? "" : ", ");
- cout << endl << " Graph Nodes:" << endl;
+ cerr << "\n Graph Nodes:\n";
for (const_iterator I=begin(); I != end(); ++I)
- cout << endl << * (*I).second;
+ cerr << "\n" << *I->second;
- cout << endl;
+ cerr << "\n";
}
const TargetMachine& target)
{
const MachineInstrInfo& mii = target.getInstrInfo();
- MachineCodeForVMInstr& termMvec = term->getMachineInstrVec();
+ MachineCodeForInstruction &termMvec = MachineCodeForInstruction::get(term);
// Find the first branch instr in the sequence of machine instrs for term
//
unsigned first = 0;
- while (! mii.isBranch(termMvec[first]->getOpCode()))
+ while (! mii.isBranch(termMvec[first]->getOpCode()) &&
+ ! mii.isReturn(termMvec[first]->getOpCode()))
++first;
assert(first < termMvec.size() &&
- "No branch instructions for BR? Ok, but weird! Delete assertion.");
+ "No branch instructions for terminator? Ok, but weird!");
if (first == termMvec.size())
return;
-
- SchedGraphNode* firstBrNode = this->getGraphNodeForInstr(termMvec[first]);
-
+
+ SchedGraphNode* firstBrNode = getGraphNodeForInstr(termMvec[first]);
+
// Add CD edges from each instruction in the sequence to the
// *last preceding* branch instr. in the sequence
// Use a latency of 0 because we only need to prevent out-of-order issue.
//
- for (int i = (int) termMvec.size()-1; i > (int) first; i--)
+ for (unsigned i = termMvec.size(); i > first+1; --i)
{
- SchedGraphNode* toNode = this->getGraphNodeForInstr(termMvec[i]);
- assert(toNode && "No node for instr generated for branch?");
+ SchedGraphNode* toNode = getGraphNodeForInstr(termMvec[i-1]);
+ assert(toNode && "No node for instr generated for branch/ret?");
- for (int j = i-1; j >= 0; j--)
- if (mii.isBranch(termMvec[j]->getOpCode()))
+ for (unsigned j = i-1; j != 0; --j)
+ if (mii.isBranch(termMvec[j-1]->getOpCode()) ||
+ mii.isReturn(termMvec[j-1]->getOpCode()))
{
- SchedGraphNode* brNode = this->getGraphNodeForInstr(termMvec[j]);
- assert(brNode && "No node for instr generated for branch?");
+ SchedGraphNode* brNode = getGraphNodeForInstr(termMvec[j-1]);
+ assert(brNode && "No node for instr generated for branch/ret?");
(void) new SchedGraphEdge(brNode, toNode, SchedGraphEdge::CtrlDep,
SchedGraphEdge::NonDataDep, 0);
break; // only one incoming edge is enough
// Add CD edges from each instruction preceding the first branch
// to the first branch. Use a latency of 0 as above.
//
- for (int i = first-1; i >= 0; i--)
+ for (unsigned i = first; i != 0; --i)
{
- SchedGraphNode* fromNode = this->getGraphNodeForInstr(termMvec[i]);
+ SchedGraphNode* fromNode = getGraphNodeForInstr(termMvec[i-1]);
assert(fromNode && "No node for instr generated for branch?");
(void) new SchedGraphEdge(fromNode, firstBrNode, SchedGraphEdge::CtrlDep,
SchedGraphEdge::NonDataDep, 0);
// Now add CD edges to the first branch instruction in the sequence from
// all preceding instructions in the basic block. Use 0 latency again.
//
- const BasicBlock* bb = term->getParent();
- for (BasicBlock::const_iterator II = bb->begin(); II != bb->end(); ++II)
+ for (unsigned i=0, N=MBB.size(); i < N; i++)
{
- if ((*II) == (const Instruction*) term) // special case, handled above
- continue;
+ if (MBB[i] == termMvec[first]) // reached the first branch
+ break;
- assert(! (*II)->isTerminator() && "Two terminators in basic block?");
+ SchedGraphNode* fromNode = this->getGraphNodeForInstr(MBB[i]);
+ if (fromNode == NULL)
+ continue; // dummy instruction, e.g., PHI
- const MachineCodeForVMInstr& mvec = (*II)->getMachineInstrVec();
- for (unsigned i=0, N=mvec.size(); i < N; i++)
- {
- SchedGraphNode* fromNode = this->getGraphNodeForInstr(mvec[i]);
- if (fromNode == NULL)
- continue; // dummy instruction, e.g., PHI
-
- (void) new SchedGraphEdge(fromNode, firstBrNode,
- SchedGraphEdge::CtrlDep,
- SchedGraphEdge::NonDataDep, 0);
-
- // If we find any other machine instructions (other than due to
- // the terminator) that also have delay slots, add an outgoing edge
- // from the instruction to the instructions in the delay slots.
- //
- unsigned d = mii.getNumDelaySlots(mvec[i]->getOpCode());
- assert(i+d < N && "Insufficient delay slots for instruction?");
-
- for (unsigned j=1; j <= d; j++)
- {
- SchedGraphNode* toNode = this->getGraphNodeForInstr(mvec[i+j]);
- assert(toNode && "No node for machine instr in delay slot?");
- (void) new SchedGraphEdge(fromNode, toNode,
- SchedGraphEdge::CtrlDep,
- SchedGraphEdge::NonDataDep, 0);
- }
- }
+ (void) new SchedGraphEdge(fromNode, firstBrNode,
+ SchedGraphEdge::CtrlDep,
+ SchedGraphEdge::NonDataDep, 0);
+
+ // If we find any other machine instructions (other than due to
+ // the terminator) that also have delay slots, add an outgoing edge
+ // from the instruction to the instructions in the delay slots.
+ //
+ unsigned d = mii.getNumDelaySlots(MBB[i]->getOpCode());
+ assert(i+d < N && "Insufficient delay slots for instruction?");
+
+ for (unsigned j=1; j <= d; j++)
+ {
+ SchedGraphNode* toNode = this->getGraphNodeForInstr(MBB[i+j]);
+ assert(toNode && "No node for machine instr in delay slot?");
+ (void) new SchedGraphEdge(fromNode, toNode,
+ SchedGraphEdge::CtrlDep,
+ SchedGraphEdge::NonDataDep, 0);
+ }
}
}
//
void
SchedGraph::addCallCCEdges(const vector<SchedGraphNode*>& memNodeVec,
- MachineCodeForBasicBlock& bbMvec,
+ MachineBasicBlock& bbMvec,
const TargetMachine& target)
{
const MachineInstrInfo& mii = target.getInstrInfo();
SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap,
const TargetMachine& target)
{
- assert(bbVec.size() == 1 && "Only handling a single basic block here");
-
// This assumes that such hardwired registers are never allocated
// to any LLVM value (since register allocation happens later), i.e.,
// any uses or defs of this register have been made explicit!
SchedGraphNode* node = regRefVec[i].first;
unsigned int opNum = regRefVec[i].second;
bool isDef = node->getMachineInstr()->operandIsDefined(opNum);
-
+ bool isDefAndUse =
+ node->getMachineInstr()->operandIsDefinedAndUsed(opNum);
+
for (unsigned p=0; p < i; ++p)
{
SchedGraphNode* prevNode = regRefVec[p].first;
unsigned int prevOpNum = regRefVec[p].second;
bool prevIsDef =
prevNode->getMachineInstr()->operandIsDefined(prevOpNum);
-
+ bool prevIsDefAndUse =
+ prevNode->getMachineInstr()->operandIsDefinedAndUsed(prevOpNum);
if (isDef)
- new SchedGraphEdge(prevNode, node, regNum,
- (prevIsDef)? SchedGraphEdge::OutputDep
- : SchedGraphEdge::AntiDep);
- else if (prevIsDef)
- new SchedGraphEdge(prevNode, node, regNum,
- SchedGraphEdge::TrueDep);
+ {
+ if (prevIsDef)
+ new SchedGraphEdge(prevNode, node, regNum,
+ SchedGraphEdge::OutputDep);
+ if (!prevIsDef || prevIsDefAndUse)
+ new SchedGraphEdge(prevNode, node, regNum,
+ SchedGraphEdge::AntiDep);
+ }
+
+ if (prevIsDef)
+ if (!isDef || isDefAndUse)
+ new SchedGraphEdge(prevNode, node, regNum,
+ SchedGraphEdge::TrueDep);
}
}
}
}
+// Adds dependences to/from refNode from/to all other defs
+// in the basic block. refNode may be a use, a def, or both.
+// We do not consider other uses because we are not building use-use deps.
+//
void
-SchedGraph::addSSAEdge(SchedGraphNode* destNode,
- const RefVec& defVec,
- const Value* defValue,
- const TargetMachine& target)
+SchedGraph::addEdgesForValue(SchedGraphNode* refNode,
+ const RefVec& defVec,
+ const Value* defValue,
+ bool refNodeIsDef,
+ bool refNodeIsDefAndUse,
+ const TargetMachine& target)
{
+ bool refNodeIsUse = !refNodeIsDef || refNodeIsDefAndUse;
+
+ // Add true or output dep edges from all def nodes before refNode in BB.
+ // Add anti or output dep edges to all def nodes after refNode.
for (RefVec::const_iterator I=defVec.begin(), E=defVec.end(); I != E; ++I)
- (void) new SchedGraphEdge((*I).first, destNode, defValue);
+ {
+ if ((*I).first == refNode)
+ continue; // Dont add any self-loops
+
+ if ((*I).first->getOrigIndexInBB() < refNode->getOrigIndexInBB())
+ { // (*).first is before refNode
+ if (refNodeIsDef)
+ (void) new SchedGraphEdge((*I).first, refNode, defValue,
+ SchedGraphEdge::OutputDep);
+ if (refNodeIsUse)
+ (void) new SchedGraphEdge((*I).first, refNode, defValue,
+ SchedGraphEdge::TrueDep);
+ }
+ else
+ { // (*).first is after refNode
+ if (refNodeIsDef)
+ (void) new SchedGraphEdge(refNode, (*I).first, defValue,
+ SchedGraphEdge::OutputDep);
+ if (refNodeIsUse)
+ (void) new SchedGraphEdge(refNode, (*I).first, defValue,
+ SchedGraphEdge::AntiDep);
+ }
+ }
}
void
-SchedGraph::addEdgesForInstruction(const MachineInstr& minstr,
+SchedGraph::addEdgesForInstruction(const MachineInstr& MI,
const ValueToDefVecMap& valueToDefVecMap,
const TargetMachine& target)
{
- SchedGraphNode* node = this->getGraphNodeForInstr(&minstr);
+ SchedGraphNode* node = getGraphNodeForInstr(&MI);
if (node == NULL)
return;
- assert(node->getInstr() && "Should be no dummy nodes here!");
- const Instruction* instr = node->getInstr();
-
// Add edges for all operands of the machine instruction.
//
- for (unsigned i=0, numOps=minstr.getNumOperands(); i < numOps; i++)
+ for (unsigned i = 0, numOps = MI.getNumOperands(); i != numOps; ++i)
{
- // ignore def operands here
- if (minstr.operandIsDefined(i))
- continue;
-
- const MachineOperand& mop = minstr.getOperand(i);
-
- switch(mop.getOperandType())
+ switch (MI.getOperandType(i))
{
case MachineOperand::MO_VirtualRegister:
case MachineOperand::MO_CCRegister:
if (const Instruction* srcI =
- dyn_cast_or_null<Instruction>(mop.getVRegValue()))
+ dyn_cast_or_null<Instruction>(MI.getOperand(i).getVRegValue()))
{
ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
if (I != valueToDefVecMap.end())
- addSSAEdge(node, (*I).second, mop.getVRegValue(), target);
+ addEdgesForValue(node, I->second, srcI,
+ MI.operandIsDefined(i),
+ MI.operandIsDefinedAndUsed(i), target);
}
break;
// Examples include function arguments to a Call instructions or the return
// value of a Ret instruction.
//
- for (unsigned i=0, N=minstr.getNumImplicitRefs(); i < N; ++i)
- if (! minstr.implicitRefIsDefined(i))
- if (const Instruction* srcI =
- dyn_cast_or_null<Instruction>(minstr.getImplicitRef(i)))
+ for (unsigned i=0, N=MI.getNumImplicitRefs(); i < N; ++i)
+ if (! MI.implicitRefIsDefined(i) ||
+ MI.implicitRefIsDefinedAndUsed(i))
+ if (const Instruction *srcI =
+ dyn_cast_or_null<Instruction>(MI.getImplicitRef(i)))
{
ValueToDefVecMap::const_iterator I = valueToDefVecMap.find(srcI);
if (I != valueToDefVecMap.end())
- addSSAEdge(node, (*I).second, minstr.getImplicitRef(i), target);
+ addEdgesForValue(node, I->second, srcI,
+ MI.implicitRefIsDefined(i),
+ MI.implicitRefIsDefinedAndUsed(i), target);
}
}
-void
-SchedGraph::addNonSSAEdgesForValue(const Instruction* instr,
- const TargetMachine& target)
-{
- if (isa<PHINode>(instr))
- return;
-
- MachineCodeForVMInstr& mvec = instr->getMachineInstrVec();
- const MachineInstrInfo& mii = target.getInstrInfo();
- RefVec refVec;
-
- for (unsigned i=0, N=mvec.size(); i < N; i++)
- for (int o=0, N = mii.getNumOperands(mvec[i]->getOpCode()); o < N; o++)
- {
- const MachineOperand& mop = mvec[i]->getOperand(o);
-
- if ((mop.getOperandType() == MachineOperand::MO_VirtualRegister ||
- mop.getOperandType() == MachineOperand::MO_CCRegister)
- && mop.getVRegValue() == (Value*) instr)
- {
- // this operand is a definition or use of value `instr'
- SchedGraphNode* node = this->getGraphNodeForInstr(mvec[i]);
- assert(node && "No node for machine instruction in this BB?");
- refVec.push_back(make_pair(node, o));
- }
- }
-
- // refVec is ordered by control flow order of the machine instructions
- for (unsigned i=0; i < refVec.size(); ++i)
- {
- SchedGraphNode* node = refVec[i].first;
- unsigned int opNum = refVec[i].second;
- bool isDef = node->getMachineInstr()->operandIsDefined(opNum);
-
- if (isDef)
- // add output and/or anti deps to this definition
- for (unsigned p=0; p < i; ++p)
- {
- SchedGraphNode* prevNode = refVec[p].first;
- if (prevNode != node)
- {
- bool prevIsDef = prevNode->getMachineInstr()->
- operandIsDefined(refVec[p].second);
- new SchedGraphEdge(prevNode, node, SchedGraphEdge::DefUseDep,
- (prevIsDef)? SchedGraphEdge::OutputDep
- : SchedGraphEdge::AntiDep);
- }
- }
- }
-}
-
-
void
SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
SchedGraphNode* node,
// Collect the register references and value defs. for explicit operands
//
- const MachineInstr& minstr = * node->getMachineInstr();
+ const MachineInstr& minstr = *node->getMachineInstr();
for (int i=0, numOps = (int) minstr.getNumOperands(); i < numOps; i++)
{
const MachineOperand& mop = minstr.getOperand(i);
// if this references a register other than the hardwired
// "zero" register, record the reference.
- if (mop.getOperandType() == MachineOperand::MO_MachineRegister)
+ if (mop.getType() == MachineOperand::MO_MachineRegister)
{
int regNum = mop.getMachineRegNum();
if (regNum != target.getRegInfo().getZeroRegNum())
- regToRefVecMap[mop.getMachineRegNum()].push_back(make_pair(node,
- i));
+ regToRefVecMap[mop.getMachineRegNum()].push_back(
+ std::make_pair(node, i));
continue; // nothing more to do
}
continue;
// We must be defining a value.
- assert((mop.getOperandType() == MachineOperand::MO_VirtualRegister ||
- mop.getOperandType() == MachineOperand::MO_CCRegister)
+ assert((mop.getType() == MachineOperand::MO_VirtualRegister ||
+ mop.getType() == MachineOperand::MO_CCRegister)
&& "Do not expect any other kind of operand to be defined!");
const Instruction* defInstr = cast<Instruction>(mop.getVRegValue());
- valueToDefVecMap[defInstr].push_back(make_pair(node, i));
+ valueToDefVecMap[defInstr].push_back(std::make_pair(node, i));
}
//
// Collect value defs. for implicit operands. The interface to extract
// them assumes they must be virtual registers!
//
- for (int i=0, N = (int) minstr.getNumImplicitRefs(); i < N; ++i)
+ for (unsigned i=0, N = minstr.getNumImplicitRefs(); i != N; ++i)
if (minstr.implicitRefIsDefined(i))
if (const Instruction* defInstr =
dyn_cast_or_null<Instruction>(minstr.getImplicitRef(i)))
- {
- valueToDefVecMap[defInstr].push_back(make_pair(node, -i));
- }
+ valueToDefVecMap[defInstr].push_back(std::make_pair(node, -i));
}
void
-SchedGraph::buildNodesforVMInstr(const TargetMachine& target,
- const Instruction* instr,
- vector<SchedGraphNode*>& memNodeVec,
- RegToRefVecMap& regToRefVecMap,
- ValueToDefVecMap& valueToDefVecMap)
+SchedGraph::buildNodesForBB(const TargetMachine& target,
+ MachineBasicBlock& MBB,
+ vector<SchedGraphNode*>& memNodeVec,
+ RegToRefVecMap& regToRefVecMap,
+ ValueToDefVecMap& valueToDefVecMap)
{
const MachineInstrInfo& mii = target.getInstrInfo();
- const MachineCodeForVMInstr& mvec = instr->getMachineInstrVec();
- for (unsigned i=0; i < mvec.size(); i++)
- if (! mii.isDummyPhiInstr(mvec[i]->getOpCode()))
- {
- SchedGraphNode* node = new SchedGraphNode(getNumNodes(),
- instr, mvec[i], target);
- this->noteGraphNodeForInstr(mvec[i], node);
-
- // Remember all register references and value defs
- findDefUseInfoAtInstr(target, node,
- memNodeVec, regToRefVecMap, valueToDefVecMap);
- }
+
+ // Build graph nodes for each VM instruction and gather def/use info.
+ // Do both those together in a single pass over all machine instructions.
+ for (unsigned i=0; i < MBB.size(); i++)
+ if (!mii.isDummyPhiInstr(MBB[i]->getOpCode())) {
+ SchedGraphNode* node = new SchedGraphNode(getNumNodes(), &MBB, i, target);
+ noteGraphNodeForInstr(MBB[i], node);
+
+ // Remember all register references and value defs
+ findDefUseInfoAtInstr(target, node, memNodeVec, regToRefVecMap,
+ valueToDefVecMap);
+ }
}
void
SchedGraph::buildGraph(const TargetMachine& target)
{
- const MachineInstrInfo& mii = target.getInstrInfo();
- const BasicBlock* bb = bbVec[0];
-
- assert(bbVec.size() == 1 && "Only handling a single basic block here");
-
// Use this data structure to note all machine operands that compute
// ordinary LLVM values. These must be computed defs (i.e., instructions).
// Note that there may be multiple machine instructions that define
RegToRefVecMap regToRefVecMap;
// Make a dummy root node. We'll add edges to the real roots later.
- graphRoot = new SchedGraphNode(0, NULL, NULL, target);
- graphLeaf = new SchedGraphNode(1, NULL, NULL, target);
+ graphRoot = new SchedGraphNode(0, NULL, -1, target);
+ graphLeaf = new SchedGraphNode(1, NULL, -1, target);
//----------------------------------------------------------------
// First add nodes for all the machine instructions in the basic block
// Do this one VM instruction at a time since the SchedGraphNode needs that.
// Also, remember the load/store instructions to add memory deps later.
//----------------------------------------------------------------
-
- for (BasicBlock::const_iterator II = bb->begin(); II != bb->end(); ++II)
- {
- const Instruction *instr = *II;
- // Build graph nodes for this VM instruction and gather def/use info.
- // Do these together in a single pass over all machine instructions.
- buildNodesforVMInstr(target, instr,
- memNodeVec, regToRefVecMap, valueToDefVecMap);
- }
+ buildNodesForBB(target, MBB, memNodeVec, regToRefVecMap, valueToDefVecMap);
//----------------------------------------------------------------
// Now add edges for the following (all are incoming edges except (4)):
//
//----------------------------------------------------------------
- MachineCodeForBasicBlock& bbMvec = bb->getMachineInstrVec();
-
// First, add edges to the terminator instruction of the basic block.
- this->addCDEdges(bb->getTerminator(), target);
+ this->addCDEdges(MBB.getBasicBlock()->getTerminator(), target);
// Then add memory dep edges: store->load, load->store, and store->store.
// Call instructions are treated as both load and store.
this->addMemEdges(memNodeVec, target);
// Then add edges between call instructions and CC set/use instructions
- this->addCallCCEdges(memNodeVec, bbMvec, target);
+ this->addCallCCEdges(memNodeVec, MBB, target);
// Then add incoming def-use (SSA) edges for each machine instruction.
- for (unsigned i=0, N=bbMvec.size(); i < N; i++)
- addEdgesForInstruction(*bbMvec[i], valueToDefVecMap, target);
+ for (unsigned i=0, N=MBB.size(); i < N; i++)
+ addEdgesForInstruction(*MBB[i], valueToDefVecMap, target);
+#ifdef NEED_SEPARATE_NONSSA_EDGES_CODE
// Then add non-SSA edges for all VM instructions in the block.
// We assume that all machine instructions that define a value are
// generated from the VM instruction corresponding to that value.
// TODO: This could probably be done much more efficiently.
for (BasicBlock::const_iterator II = bb->begin(); II != bb->end(); ++II)
this->addNonSSAEdgesForValue(*II, target);
+#endif //NEED_SEPARATE_NONSSA_EDGES_CODE
// Then add edges for dependences on machine registers
this->addMachineRegEdges(regToRefVecMap, target);
//
/*ctor*/
-SchedGraphSet::SchedGraphSet(const Method* _method,
+SchedGraphSet::SchedGraphSet(const Function* _function,
const TargetMachine& target) :
- method(_method)
+ method(_function)
{
buildGraphsForMethod(method, target);
}
SchedGraphSet::~SchedGraphSet()
{
// delete all the graphs
- for (iterator I=begin(); I != end(); ++I)
- delete (*I).second;
+ for(iterator I = begin(), E = end(); I != E; ++I)
+ delete *I; // destructor is a friend
}
void
SchedGraphSet::dump() const
{
- cout << "======== Sched graphs for method `"
- << (method->hasName()? method->getName() : "???")
- << "' ========" << endl << endl;
+ cerr << "======== Sched graphs for function `" << method->getName()
+ << "' ========\n\n";
for (const_iterator I=begin(); I != end(); ++I)
- (*I).second->dump();
+ (*I)->dump();
- cout << endl << "====== End graphs for method `"
- << (method->hasName()? method->getName() : "")
- << "' ========" << endl << endl;
+ cerr << "\n====== End graphs for function `" << method->getName()
+ << "' ========\n\n";
}
void
-SchedGraphSet::buildGraphsForMethod(const Method *method,
+SchedGraphSet::buildGraphsForMethod(const Function *F,
const TargetMachine& target)
{
- for (Method::const_iterator BI = method->begin(); BI != method->end(); ++BI)
- {
- SchedGraph* graph = new SchedGraph(*BI, target);
- this->noteGraphForBlock(*BI, graph);
- }
+ MachineFunction &MF = MachineFunction::get(F);
+ for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
+ addGraph(new SchedGraph(*I, target));
}
-
-ostream&
-operator<<(ostream& os, const SchedGraphEdge& edge)
+std::ostream &operator<<(std::ostream &os, const SchedGraphEdge& edge)
{
os << "edge [" << edge.src->getNodeId() << "] -> ["
<< edge.sink->getNodeId() << "] : ";
switch(edge.depType) {
case SchedGraphEdge::CtrlDep: os<< "Control Dep"; break;
- case SchedGraphEdge::DefUseDep: os<< "Reg Value " << edge.val; break;
- case SchedGraphEdge::MemoryDep: os<< "Mem Value " << edge.val; break;
+ case SchedGraphEdge::ValueDep: os<< "Reg Value " << edge.val; break;
+ case SchedGraphEdge::MemoryDep: os<< "Memory Dep"; break;
case SchedGraphEdge::MachineRegister: os<< "Reg " <<edge.machineRegNum;break;
case SchedGraphEdge::MachineResource: os<<"Resource "<<edge.resourceId;break;
default: assert(0); break;
}
- os << " : delay = " << edge.minDelay << endl;
+ os << " : delay = " << edge.minDelay << "\n";
return os;
}
-ostream&
-operator<<(ostream& os, const SchedGraphNode& node)
+std::ostream &operator<<(std::ostream &os, const SchedGraphNode& node)
{
- printIndent(4, os);
- os << "Node " << node.nodeId << " : "
- << "latency = " << node.latency << endl;
-
- printIndent(6, os);
+ os << std::string(8, ' ')
+ << "Node " << node.nodeId << " : "
+ << "latency = " << node.latency << "\n" << std::string(12, ' ');
if (node.getMachineInstr() == NULL)
- os << "(Dummy node)" << endl;
+ os << "(Dummy node)\n";
else
{
- os << *node.getMachineInstr() << endl;
-
- printIndent(6, os);
- os << node.inEdges.size() << " Incoming Edges:" << endl;
+ os << *node.getMachineInstr() << "\n" << std::string(12, ' ');
+ os << node.inEdges.size() << " Incoming Edges:\n";
for (unsigned i=0, N=node.inEdges.size(); i < N; i++)
- {
- printIndent(8, os);
- os << * node.inEdges[i];
- }
+ os << std::string(16, ' ') << *node.inEdges[i];
- printIndent(6, os);
- os << node.outEdges.size() << " Outgoing Edges:" << endl;
+ os << std::string(12, ' ') << node.outEdges.size()
+ << " Outgoing Edges:\n";
for (unsigned i=0, N=node.outEdges.size(); i < N; i++)
- {
- printIndent(8, os);
- os << * node.outEdges[i];
- }
+ os << std::string(16, ' ') << *node.outEdges[i];
}
return os;
projects / oota-llvm.git / blobdiff