#include "llvm/CodeGen/PhyRegAlloc.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrAnnot.h"
-#include "llvm/CodeGen/MachineCodeForBasicBlock.h"
-#include "llvm/CodeGen/MachineCodeForMethod.h"
+#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h"
#include "llvm/Analysis/LoopInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/MachineFrameInfo.h"
+#include "llvm/Target/MachineInstrInfo.h"
#include "llvm/Function.h"
#include "llvm/Type.h"
#include "llvm/iOther.h"
//----------------------------------------------------------------------------
PhyRegAlloc::PhyRegAlloc(Function *F, const TargetMachine& tm,
FunctionLiveVarInfo *Lvi, LoopInfo *LDC)
- : TM(tm), Meth(F),
- mcInfo(MachineCodeForMethod::get(F)),
- LVI(Lvi), LRI(F, tm, RegClassList),
- MRI(tm.getRegInfo()),
- NumOfRegClasses(MRI.getNumOfRegClasses()),
- LoopDepthCalc(LDC) {
+ : TM(tm), Fn(F), MF(MachineFunction::get(F)), LVI(Lvi),
+ LRI(F, tm, RegClassList), MRI(tm.getRegInfo()),
+ NumOfRegClasses(MRI.getNumOfRegClasses()), LoopDepthCalc(LDC) {
// create each RegisterClass and put in RegClassList
//
- for (unsigned rc=0; rc < NumOfRegClasses; rc++)
+ for (unsigned rc=0; rc != NumOfRegClasses; rc++)
RegClassList.push_back(new RegClass(F, MRI.getMachineRegClass(rc),
&ResColList));
}
cerr << "Creating interference graphs ...\n";
unsigned BBLoopDepthCost;
- for (Function::const_iterator BBI = Meth->begin(), BBE = Meth->end();
+ for (MachineFunction::iterator BBI = MF.begin(), BBE = MF.end();
BBI != BBE; ++BBI) {
+ const MachineBasicBlock &MBB = *BBI;
+ const BasicBlock *BB = MBB.getBasicBlock();
// find the 10^(loop_depth) of this BB
//
- BBLoopDepthCost = (unsigned)pow(10.0, LoopDepthCalc->getLoopDepth(BBI));
+ BBLoopDepthCost = (unsigned)pow(10.0, LoopDepthCalc->getLoopDepth(BB));
// get the iterator for machine instructions
//
- const MachineCodeForBasicBlock& MIVec = MachineCodeForBasicBlock::get(BBI);
- MachineCodeForBasicBlock::const_iterator MII = MIVec.begin();
+ MachineBasicBlock::const_iterator MII = MBB.begin();
// iterate over all the machine instructions in BB
//
- for ( ; MII != MIVec.end(); ++MII) {
-
- const MachineInstr *MInst = *MII;
+ for ( ; MII != MBB.end(); ++MII) {
+ const MachineInstr *MInst = *MII;
// get the LV set after the instruction
//
- const ValueSet &LVSetAI = LVI->getLiveVarSetAfterMInst(MInst, BBI);
-
- const bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpCode());
+ const ValueSet &LVSetAI = LVI->getLiveVarSetAfterMInst(MInst, BB);
+ bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpCode());
if (isCallInst ) {
// set the isCallInterference flag of each live range wich extends
setCallInterferences(MInst, &LVSetAI);
}
-
// iterate over all MI operands to find defs
//
for (MachineInstr::const_val_op_iterator OpI = MInst->begin(),
void PhyRegAlloc::addInterferencesForArgs() {
// get the InSet of root BB
- const ValueSet &InSet = LVI->getInSetOfBB(&Meth->front());
+ const ValueSet &InSet = LVI->getInSetOfBB(&Fn->front());
- for (Function::const_aiterator AI=Meth->abegin(); AI != Meth->aend(); ++AI) {
+ for (Function::const_aiterator AI = Fn->abegin(); AI != Fn->aend(); ++AI) {
// add interferences between args and LVars at start
addInterference(AI, &InSet, false);
//-----------------------------
inline void
InsertBefore(MachineInstr* newMI,
- MachineCodeForBasicBlock& MIVec,
- MachineCodeForBasicBlock::iterator& MII)
+ MachineBasicBlock& MBB,
+ MachineBasicBlock::iterator& MII)
{
- MII = MIVec.insert(MII, newMI);
+ MII = MBB.insert(MII, newMI);
++MII;
}
inline void
InsertAfter(MachineInstr* newMI,
- MachineCodeForBasicBlock& MIVec,
- MachineCodeForBasicBlock::iterator& MII)
+ MachineBasicBlock& MBB,
+ MachineBasicBlock::iterator& MII)
{
++MII; // insert before the next instruction
- MII = MIVec.insert(MII, newMI);
+ MII = MBB.insert(MII, newMI);
}
inline void
SubstituteInPlace(MachineInstr* newMI,
- MachineCodeForBasicBlock& MIVec,
- MachineCodeForBasicBlock::iterator MII)
+ MachineBasicBlock& MBB,
+ MachineBasicBlock::iterator MII)
{
*MII = newMI;
}
inline void
PrependInstructions(vector<MachineInstr *> &IBef,
- MachineCodeForBasicBlock& MIVec,
- MachineCodeForBasicBlock::iterator& MII,
+ MachineBasicBlock& MBB,
+ MachineBasicBlock::iterator& MII,
const std::string& msg)
{
if (!IBef.empty())
if (OrigMI) cerr << "For MInst:\n " << *OrigMI;
cerr << msg << "PREPENDed instr:\n " << **AdIt << "\n";
}
- InsertBefore(*AdIt, MIVec, MII);
+ InsertBefore(*AdIt, MBB, MII);
}
}
}
inline void
AppendInstructions(std::vector<MachineInstr *> &IAft,
- MachineCodeForBasicBlock& MIVec,
- MachineCodeForBasicBlock::iterator& MII,
+ MachineBasicBlock& MBB,
+ MachineBasicBlock::iterator& MII,
const std::string& msg)
{
if (!IAft.empty())
if (OrigMI) cerr << "For MInst:\n " << *OrigMI;
cerr << msg << "APPENDed instr:\n " << **AdIt << "\n";
}
- InsertAfter(*AdIt, MIVec, MII);
+ InsertAfter(*AdIt, MBB, MII);
}
}
}
-void PhyRegAlloc::updateMachineCode()
-{
- MachineCodeForBasicBlock& MIVec = MachineCodeForBasicBlock::get(&Meth->getEntryNode());
-
+void PhyRegAlloc::updateMachineCode() {
// Insert any instructions needed at method entry
- MachineCodeForBasicBlock::iterator MII = MIVec.begin();
- PrependInstructions(AddedInstrAtEntry.InstrnsBefore, MIVec, MII,
+ MachineBasicBlock::iterator MII = MF.front().begin();
+ PrependInstructions(AddedInstrAtEntry.InstrnsBefore, MF.front(), MII,
"At function entry: \n");
assert(AddedInstrAtEntry.InstrnsAfter.empty() &&
"InstrsAfter should be unnecessary since we are just inserting at "
"the function entry point here.");
- for (Function::const_iterator BBI = Meth->begin(), BBE = Meth->end();
+ for (MachineFunction::iterator BBI = MF.begin(), BBE = MF.end();
BBI != BBE; ++BBI) {
// iterate over all the machine instructions in BB
- MachineCodeForBasicBlock &MIVec = MachineCodeForBasicBlock::get(BBI);
- for (MachineCodeForBasicBlock::iterator MII = MIVec.begin();
- MII != MIVec.end(); ++MII) {
-
+ MachineBasicBlock &MBB = *BBI;
+ for (MachineBasicBlock::iterator MII = MBB.begin();
+ MII != MBB.end(); ++MII) {
+
MachineInstr *MInst = *MII;
-
unsigned Opcode = MInst->getOpCode();
// do not process Phis
continue;
// Reset tmp stack positions so they can be reused for each machine instr.
- mcInfo.popAllTempValues(TM);
+ MF.popAllTempValues(TM);
// Now insert speical instructions (if necessary) for call/return
// instructions.
//
if (TM.getInstrInfo().isCall(Opcode) ||
- TM.getInstrInfo().isReturn(Opcode)) {
-
- AddedInstrns &AI = AddedInstrMap[MInst];
+ TM.getInstrInfo().isReturn(Opcode)) {
+ AddedInstrns &AI = AddedInstrMap[MInst];
- if (TM.getInstrInfo().isCall(Opcode))
- MRI.colorCallArgs(MInst, LRI, &AI, *this, BBI);
- else if (TM.getInstrInfo().isReturn(Opcode))
- MRI.colorRetValue(MInst, LRI, &AI);
+ if (TM.getInstrInfo().isCall(Opcode))
+ MRI.colorCallArgs(MInst, LRI, &AI, *this, MBB.getBasicBlock());
+ else if (TM.getInstrInfo().isReturn(Opcode))
+ MRI.colorRetValue(MInst, LRI, &AI);
}
// Set the registers for operands in the machine instruction
for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum)
{
MachineOperand& Op = MInst->getOperand(OpNum);
- if (Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
- Op.getOperandType() == MachineOperand::MO_CCRegister)
+ if (Op.getType() == MachineOperand::MO_VirtualRegister ||
+ Op.getType() == MachineOperand::MO_CCRegister)
{
const Value *const Val = Op.getVRegValue();
continue;
}
- if (LR->hasColor() )
+ if (LR->hasColor())
MInst->SetRegForOperand(OpNum,
MRI.getUnifiedRegNum(LR->getRegClass()->getID(),
LR->getColor()));
else
// LR did NOT receive a color (register). Insert spill code.
- insertCode4SpilledLR(LR, MInst, BBI, OpNum );
+ insertCode4SpilledLR(LR, MInst, MBB.getBasicBlock(), OpNum);
}
} // for each operand
// branch because putting code before or after it would be VERY BAD!
//
unsigned bumpIteratorBy = 0;
- if (MII != MIVec.begin())
+ if (MII != MBB.begin())
if (unsigned predDelaySlots =
TM.getInstrInfo().getNumDelaySlots((*(MII-1))->getOpCode()))
{
// Current instruction is in the delay slot of a branch and it
// needs spill code inserted before or after it.
// Move it before the preceding branch.
- InsertBefore(MInst, MIVec, --MII);
+ InsertBefore(MInst, MBB, --MII);
MachineInstr* nopI =
new MachineInstr(TM.getInstrInfo().getNOPOpCode());
- SubstituteInPlace(nopI, MIVec, MII+1); // replace orig with NOP
+ SubstituteInPlace(nopI, MBB, MII+1); // replace orig with NOP
--MII; // point to MInst in new location
bumpIteratorBy = 2; // later skip the branch and the NOP!
}
// instruction, add them now.
//
if (AddedInstrMap.count(MInst)) {
- PrependInstructions(AddedInstrMap[MInst].InstrnsBefore, MIVec, MII,"");
+ PrependInstructions(AddedInstrMap[MInst].InstrnsBefore, MBB, MII,"");
}
// If there are instructions to be added *after* this machine
else {
// Here we can add the "instructions after" to the current
// instruction since there are no delay slots for this instruction
- AppendInstructions(AddedInstrMap[MInst].InstrnsAfter, MIVec, MII,"");
+ AppendInstructions(AddedInstrMap[MInst].InstrnsAfter, MBB, MII,"");
} // if not delay
}
RegClass *RC = LR->getRegClass();
const ValueSet &LVSetBef = LVI->getLiveVarSetBeforeMInst(MInst, BB);
- mcInfo.pushTempValue(TM, MRI.getSpilledRegSize(RegType) );
+ MF.pushTempValue(TM, MRI.getSpilledRegSize(RegType) );
vector<MachineInstr*> MIBef, MIAft;
vector<MachineInstr*> AdIMid;
std::vector<MachineInstr*>& MIBef,
std::vector<MachineInstr*>& MIAft) {
- RegClass* RC = this->getRegClassByID(MRI.getRegClassIDOfRegType(RegType));
+ RegClass* RC = getRegClassByID(MRI.getRegClassIDOfRegType(RegType));
int RegU = getUnusedUniRegAtMI(RC, MInst, LVSetBef);
// we couldn't find an unused register. Generate code to free up a reg by
// saving it on stack and restoring after the instruction
- int TmpOff = mcInfo.pushTempValue(TM, MRI.getSpilledRegSize(RegType) );
+ int TmpOff = MF.pushTempValue(TM, MRI.getSpilledRegSize(RegType) );
RegU = getUniRegNotUsedByThisInst(RC, MInst);
int scratchRegType = -1;
if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
{
- int scratchReg = this->getUsableUniRegAtMI(scratchRegType, LVSetBef,
- MInst, MIBef, MIAft);
+ int scratchReg = getUsableUniRegAtMI(scratchRegType, LVSetBef,
+ MInst, MIBef, MIAft);
assert(scratchReg != MRI.getInvalidRegNum());
// We may as well hold the value in the scratch register instead
{
const MachineOperand& Op = MInst->getOperand(OpNum);
- if (Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
- Op.getOperandType() == MachineOperand::MO_CCRegister)
+ if (MInst->getOperandType(OpNum) == MachineOperand::MO_VirtualRegister ||
+ MInst->getOperandType(OpNum) == MachineOperand::MO_CCRegister)
if (const Value* Val = Op.getVRegValue())
if (MRI.getRegClassIDOfValue(Val) == RC->getID())
if (Op.getAllocatedRegNum() == -1)
void PhyRegAlloc::printMachineCode()
{
- cerr << "\n;************** Function " << Meth->getName()
+ cerr << "\n;************** Function " << Fn->getName()
<< " *****************\n";
- for (Function::const_iterator BBI = Meth->begin(), BBE = Meth->end();
+ for (MachineFunction::iterator BBI = MF.begin(), BBE = MF.end();
BBI != BBE; ++BBI) {
- cerr << "\n"; printLabel(BBI); cerr << ": ";
+ cerr << "\n"; printLabel(BBI->getBasicBlock()); cerr << ": ";
// get the iterator for machine instructions
- MachineCodeForBasicBlock& MIVec = MachineCodeForBasicBlock::get(BBI);
- MachineCodeForBasicBlock::iterator MII = MIVec.begin();
+ MachineBasicBlock& MBB = *BBI;
+ MachineBasicBlock::iterator MII = MBB.begin();
// iterate over all the machine instructions in BB
- for ( ; MII != MIVec.end(); ++MII) {
+ for ( ; MII != MBB.end(); ++MII) {
MachineInstr *const MInst = *MII;
cerr << "\n\t";
for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
MachineOperand& Op = MInst->getOperand(OpNum);
- if (Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
- Op.getOperandType() == MachineOperand::MO_CCRegister /*||
- Op.getOperandType() == MachineOperand::MO_PCRelativeDisp*/ ) {
+ if (Op.getType() == MachineOperand::MO_VirtualRegister ||
+ Op.getType() == MachineOperand::MO_CCRegister /*||
+ Op.getType() == MachineOperand::MO_PCRelativeDisp*/ ) {
const Value *const Val = Op.getVRegValue () ;
// ****this code is temporary till NULL Values are fixed
}
}
- else if (Op.getOperandType() == MachineOperand::MO_MachineRegister) {
+ else if (Op.getType() == MachineOperand::MO_MachineRegister) {
cerr << "\t" << "%" << MRI.getUnifiedRegName(Op.getMachineRegNum());
}
//----------------------------------------------------------------------------
void PhyRegAlloc::colorIncomingArgs()
{
- const BasicBlock &FirstBB = Meth->front();
- const MachineInstr *FirstMI = MachineCodeForBasicBlock::get(&FirstBB).front();
- assert(FirstMI && "No machine instruction in entry BB");
-
- MRI.colorMethodArgs(Meth, LRI, &AddedInstrAtEntry);
+ MRI.colorMethodArgs(Fn, LRI, &AddedInstrAtEntry);
}
//----------------------------------------------------------------------------
// Used to generate a label for a basic block
//----------------------------------------------------------------------------
-void PhyRegAlloc::printLabel(const Value *const Val) {
+void PhyRegAlloc::printLabel(const Value *Val) {
if (Val->hasName())
cerr << Val->getName();
else
- cerr << "Label" << Val;
+ cerr << "Label" << Val;
}
if (HMI->first && HMI->second) {
LiveRange *L = HMI->second; // get the LiveRange
if (!L->hasColor()) { // NOTE: ** allocating the size of long Type **
- int stackOffset = mcInfo.allocateSpilledValue(TM, Type::LongTy);
+ int stackOffset = MF.allocateSpilledValue(TM, Type::LongTy);
L->setSpillOffFromFP(stackOffset);
if (DEBUG_RA)
cerr << " LR# " << L->getUserIGNode()->getIndex()
for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
RegClassList[rc]->printIG();
}
-
LRI.coalesceLRs(); // coalesce all live ranges
-
if (DEBUG_RA >= RA_DEBUG_LiveRanges) {
// print all LRs in all reg classes
- for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
- RegClassList[ rc ]->printIGNodeList();
+ for (unsigned rc=0; rc < NumOfRegClasses; rc++)
+ RegClassList[rc]->printIGNodeList();
// print IGs in all register classes
- for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
- RegClassList[ rc ]->printIG();
+ for (unsigned rc=0; rc < NumOfRegClasses; rc++)
+ RegClassList[rc]->printIG();
}
// color all register classes using the graph coloring algo
for (unsigned rc=0; rc < NumOfRegClasses ; rc++)
- RegClassList[ rc ]->colorAllRegs();
+ RegClassList[rc]->colorAllRegs();
// Atter grpah coloring, if some LRs did not receive a color (i.e, spilled)
// a poistion for such spilled LRs
//
allocateStackSpace4SpilledLRs();
- mcInfo.popAllTempValues(TM); // TODO **Check
+ MF.popAllTempValues(TM); // TODO **Check
// color incoming args - if the correct color was not received
// insert code to copy to the correct register
if (DEBUG_RA) {
cerr << "\n**** Machine Code After Register Allocation:\n\n";
- MachineCodeForMethod::get(Meth).dump();
+ MF.dump();
}
}
projects / oota-llvm.git / blobdiff