-//***************************************************************************
-// File:
-// PhyRegAlloc.cpp
+//===-- PhyRegAlloc.cpp ---------------------------------------------------===//
//
-// Purpose:
-// Register allocation for LLVM.
-//
-// History:
-// 9/10/01 - Ruchira Sasanka - created.
-//**************************************************************************/
+// Register allocation for LLVM.
+//
+//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/RegisterAllocation.h"
+#include "llvm/CodeGen/RegAllocCommon.h"
#include "llvm/CodeGen/PhyRegAlloc.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrAnnot.h"
-#include "llvm/CodeGen/MachineCodeForBasicBlock.h"
-#include "llvm/CodeGen/MachineCodeForMethod.h"
+#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Analysis/LiveVar/FunctionLiveVarInfo.h"
#include "llvm/Analysis/LoopInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/MachineFrameInfo.h"
+#include "llvm/Target/MachineInstrInfo.h"
#include "llvm/Function.h"
#include "llvm/Type.h"
#include "llvm/iOther.h"
-#include "llvm/CodeGen/RegAllocCommon.h"
-#include "Support/CommandLine.h"
#include "Support/STLExtras.h"
+#include "Support/CommandLine.h"
#include <math.h>
using std::cerr;
using std::vector;
RegAllocDebugLevel_t DEBUG_RA;
+
static cl::opt<RegAllocDebugLevel_t, true>
DRA_opt("dregalloc", cl::Hidden, cl::location(DEBUG_RA),
cl::desc("enable register allocation debugging information"),
cl::values(
- clEnumValN(RA_DEBUG_None , "n", "disable debug output"),
- clEnumValN(RA_DEBUG_Normal , "y", "enable debug output"),
- clEnumValN(RA_DEBUG_Verbose, "v", "enable extra debug output"),
+ clEnumValN(RA_DEBUG_None , "n", "disable debug output"),
+ clEnumValN(RA_DEBUG_Results, "y", "debug output for allocation results"),
+ clEnumValN(RA_DEBUG_Coloring, "c", "debug output for graph coloring step"),
+ clEnumValN(RA_DEBUG_Interference,"ig","debug output for interference graphs"),
+ clEnumValN(RA_DEBUG_LiveRanges , "lr","debug output for live ranges"),
+ clEnumValN(RA_DEBUG_Verbose, "v", "extra debug output"),
0));
-
//----------------------------------------------------------------------------
// RegisterAllocation pass front end...
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
PhyRegAlloc::PhyRegAlloc(Function *F, const TargetMachine& tm,
FunctionLiveVarInfo *Lvi, LoopInfo *LDC)
- : TM(tm), Meth(F),
- mcInfo(MachineCodeForMethod::get(F)),
- LVI(Lvi), LRI(F, tm, RegClassList),
- MRI(tm.getRegInfo()),
- NumOfRegClasses(MRI.getNumOfRegClasses()),
- LoopDepthCalc(LDC) {
+ : TM(tm), Fn(F), MF(MachineFunction::get(F)), LVI(Lvi),
+ LRI(F, tm, RegClassList), MRI(tm.getRegInfo()),
+ NumOfRegClasses(MRI.getNumOfRegClasses()), LoopDepthCalc(LDC) {
// create each RegisterClass and put in RegClassList
//
- for (unsigned rc=0; rc < NumOfRegClasses; rc++)
+ for (unsigned rc=0; rc != NumOfRegClasses; rc++)
RegClassList.push_back(new RegClass(F, MRI.getMachineRegClass(rc),
&ResColList));
}
// and IGNodeList (one in each IG). The actual nodes will be pushed later.
//----------------------------------------------------------------------------
void PhyRegAlloc::createIGNodeListsAndIGs() {
- if (DEBUG_RA) cerr << "Creating LR lists ...\n";
+ if (DEBUG_RA >= RA_DEBUG_LiveRanges) cerr << "Creating LR lists ...\n";
// hash map iterator
LiveRangeMapType::const_iterator HMI = LRI.getLiveRangeMap()->begin();
if (HMI->first) {
LiveRange *L = HMI->second; // get the LiveRange
if (!L) {
- if (DEBUG_RA) {
- cerr << "\n*?!?Warning: Null liver range found for: "
- << RAV(HMI->first) << "\n";
- }
+ if (DEBUG_RA)
+ cerr << "\n**** ?!?WARNING: NULL LIVE RANGE FOUND FOR: "
+ << RAV(HMI->first) << "****\n";
continue;
}
- // if the Value * is not null, and LR
- // is not yet written to the IGNodeList
+
+ // if the Value * is not null, and LR is not yet written to the IGNodeList
if (!(L->getUserIGNode()) ) {
RegClass *const RC = // RegClass of first value in the LR
RegClassList[ L->getRegClass()->getID() ];
-
RC->addLRToIG(L); // add this LR to an IG
}
}
for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
RegClassList[rc]->createInterferenceGraph();
- if (DEBUG_RA)
- cerr << "LRLists Created!\n";
+ if (DEBUG_RA >= RA_DEBUG_LiveRanges) cerr << "LRLists Created!\n";
}
-
-
//----------------------------------------------------------------------------
// This method will add all interferences at for a given instruction.
// Interence occurs only if the LR of Def (Inst or Arg) is of the same reg
// class as that of live var. The live var passed to this function is the
// LVset AFTER the instruction
//----------------------------------------------------------------------------
+
void PhyRegAlloc::addInterference(const Value *Def,
const ValueSet *LVSet,
bool isCallInst) {
cerr << "< Def=" << RAV(Def) << ", Lvar=" << RAV(*LIt) << "> ";
// get the live range corresponding to live var
- //
+ //
LiveRange *LROfVar = LRI.getLiveRangeForValue(*LIt);
// LROfVar can be null if it is a const since a const
// doesn't have a dominating def - see Assumptions above
//
- if (LROfVar) {
- if (LROfDef == LROfVar) // do not set interf for same LR
- continue;
-
- // if 2 reg classes are the same set interference
- //
- if (RCOfDef == LROfVar->getRegClass()) {
- RCOfDef->setInterference( LROfDef, LROfVar);
- } else if (DEBUG_RA >= RA_DEBUG_Verbose) {
- // we will not have LRs for values not explicitly allocated in the
- // instruction stream (e.g., constants)
- cerr << " warning: no live range for " << RAV(*LIt) << "\n";
- }
- }
+ if (LROfVar)
+ if (LROfDef != LROfVar) // do not set interf for same LR
+ if (RCOfDef == LROfVar->getRegClass()) // 2 reg classes are the same
+ RCOfDef->setInterference( LROfDef, LROfVar);
}
}
void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst,
const ValueSet *LVSetAft) {
- if (DEBUG_RA)
+ if (DEBUG_RA >= RA_DEBUG_Interference)
cerr << "\n For call inst: " << *MInst;
ValueSet::const_iterator LIt = LVSetAft->begin();
//
LiveRange *const LR = LRI.getLiveRangeForValue(*LIt );
- if (LR && DEBUG_RA) {
- cerr << "\n\tLR Aft Call: ";
- printSet(*LR);
- }
-
// LR can be null if it is a const since a const
// doesn't have a dominating def - see Assumptions above
//
- if (LR ) {
+ if (LR ) {
+ if (DEBUG_RA >= RA_DEBUG_Interference) {
+ cerr << "\n\tLR after Call: ";
+ printSet(*LR);
+ }
LR->setCallInterference();
- if (DEBUG_RA) {
- cerr << "\n ++Added call interf for LR: " ;
+ if (DEBUG_RA >= RA_DEBUG_Interference) {
+ cerr << "\n ++After adding call interference for LR: " ;
printSet(*LR);
}
}
void PhyRegAlloc::buildInterferenceGraphs()
{
- if (DEBUG_RA) cerr << "Creating interference graphs ...\n";
+ if (DEBUG_RA >= RA_DEBUG_Interference)
+ cerr << "Creating interference graphs ...\n";
unsigned BBLoopDepthCost;
- for (Function::const_iterator BBI = Meth->begin(), BBE = Meth->end();
+ for (MachineFunction::iterator BBI = MF.begin(), BBE = MF.end();
BBI != BBE; ++BBI) {
+ const MachineBasicBlock &MBB = *BBI;
+ const BasicBlock *BB = MBB.getBasicBlock();
// find the 10^(loop_depth) of this BB
//
- BBLoopDepthCost = (unsigned)pow(10.0, LoopDepthCalc->getLoopDepth(BBI));
+ BBLoopDepthCost = (unsigned)pow(10.0, LoopDepthCalc->getLoopDepth(BB));
// get the iterator for machine instructions
//
- const MachineCodeForBasicBlock& MIVec = MachineCodeForBasicBlock::get(BBI);
- MachineCodeForBasicBlock::const_iterator MII = MIVec.begin();
+ MachineBasicBlock::const_iterator MII = MBB.begin();
// iterate over all the machine instructions in BB
//
- for ( ; MII != MIVec.end(); ++MII) {
-
- const MachineInstr *MInst = *MII;
+ for ( ; MII != MBB.end(); ++MII) {
+ const MachineInstr *MInst = *MII;
// get the LV set after the instruction
//
- const ValueSet &LVSetAI = LVI->getLiveVarSetAfterMInst(MInst, BBI);
-
- const bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpCode());
+ const ValueSet &LVSetAI = LVI->getLiveVarSetAfterMInst(MInst, BB);
+ bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpCode());
if (isCallInst ) {
// set the isCallInterference flag of each live range wich extends
setCallInterferences(MInst, &LVSetAI);
}
-
// iterate over all MI operands to find defs
//
for (MachineInstr::const_val_op_iterator OpI = MInst->begin(),
//
addInterferencesForArgs();
- if (DEBUG_RA)
- cerr << "Interference graphs calculted!\n";
-
+ if (DEBUG_RA >= RA_DEBUG_Interference)
+ cerr << "Interference graphs calculated!\n";
}
//----------------------------------------------------------------------------
// This method will add interferences for incoming arguments to a function.
//----------------------------------------------------------------------------
+
void PhyRegAlloc::addInterferencesForArgs() {
// get the InSet of root BB
- const ValueSet &InSet = LVI->getInSetOfBB(&Meth->front());
+ const ValueSet &InSet = LVI->getInSetOfBB(&Fn->front());
- for (Function::const_aiterator AI = Meth->abegin(); AI != Meth->aend(); ++AI) {
+ for (Function::const_aiterator AI = Fn->abegin(); AI != Fn->aend(); ++AI) {
// add interferences between args and LVars at start
addInterference(AI, &InSet, false);
- if (DEBUG_RA >= RA_DEBUG_Verbose)
+ if (DEBUG_RA >= RA_DEBUG_Interference)
cerr << " - %% adding interference for argument " << RAV(AI) << "\n";
}
}
//-----------------------------
// Utility functions used below
//-----------------------------
+inline void
+InsertBefore(MachineInstr* newMI,
+ MachineBasicBlock& MBB,
+ MachineBasicBlock::iterator& MII)
+{
+ MII = MBB.insert(MII, newMI);
+ ++MII;
+}
+
+inline void
+InsertAfter(MachineInstr* newMI,
+ MachineBasicBlock& MBB,
+ MachineBasicBlock::iterator& MII)
+{
+ ++MII; // insert before the next instruction
+ MII = MBB.insert(MII, newMI);
+}
+
+inline void
+SubstituteInPlace(MachineInstr* newMI,
+ MachineBasicBlock& MBB,
+ MachineBasicBlock::iterator MII)
+{
+ *MII = newMI;
+}
+
inline void
PrependInstructions(vector<MachineInstr *> &IBef,
- MachineCodeForBasicBlock& MIVec,
- MachineCodeForBasicBlock::iterator& MII,
+ MachineBasicBlock& MBB,
+ MachineBasicBlock::iterator& MII,
const std::string& msg)
{
if (!IBef.empty())
for (AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt)
{
if (DEBUG_RA) {
- if (OrigMI) cerr << "For MInst: " << *OrigMI;
- cerr << msg << " PREPENDed instr: " << **AdIt << "\n";
+ if (OrigMI) cerr << "For MInst:\n " << *OrigMI;
+ cerr << msg << "PREPENDed instr:\n " << **AdIt << "\n";
}
- MII = MIVec.insert(MII, *AdIt);
- ++MII;
+ InsertBefore(*AdIt, MBB, MII);
}
}
}
inline void
AppendInstructions(std::vector<MachineInstr *> &IAft,
- MachineCodeForBasicBlock& MIVec,
- MachineCodeForBasicBlock::iterator& MII,
+ MachineBasicBlock& MBB,
+ MachineBasicBlock::iterator& MII,
const std::string& msg)
{
if (!IAft.empty())
for ( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt )
{
if (DEBUG_RA) {
- if (OrigMI) cerr << "For MInst: " << *OrigMI;
- cerr << msg << " APPENDed instr: " << **AdIt << "\n";
+ if (OrigMI) cerr << "For MInst:\n " << *OrigMI;
+ cerr << msg << "APPENDed instr:\n " << **AdIt << "\n";
}
- ++MII; // insert before the next instruction
- MII = MIVec.insert(MII, *AdIt);
+ InsertAfter(*AdIt, MBB, MII);
}
}
}
-void PhyRegAlloc::updateMachineCode()
-{
- MachineCodeForBasicBlock& MIVec = MachineCodeForBasicBlock::get(&Meth->getEntryNode());
-
+void PhyRegAlloc::updateMachineCode() {
// Insert any instructions needed at method entry
- MachineCodeForBasicBlock::iterator MII = MIVec.begin();
- PrependInstructions(AddedInstrAtEntry.InstrnsBefore, MIVec, MII,
+ MachineBasicBlock::iterator MII = MF.front().begin();
+ PrependInstructions(AddedInstrAtEntry.InstrnsBefore, MF.front(), MII,
"At function entry: \n");
assert(AddedInstrAtEntry.InstrnsAfter.empty() &&
"InstrsAfter should be unnecessary since we are just inserting at "
"the function entry point here.");
- for (Function::const_iterator BBI = Meth->begin(), BBE = Meth->end();
+ for (MachineFunction::iterator BBI = MF.begin(), BBE = MF.end();
BBI != BBE; ++BBI) {
-
+
// iterate over all the machine instructions in BB
- MachineCodeForBasicBlock &MIVec = MachineCodeForBasicBlock::get(BBI);
- for (MachineCodeForBasicBlock::iterator MII = MIVec.begin();
- MII != MIVec.end(); ++MII) {
-
+ MachineBasicBlock &MBB = *BBI;
+ for (MachineBasicBlock::iterator MII = MBB.begin();
+ MII != MBB.end(); ++MII) {
+
MachineInstr *MInst = *MII;
-
unsigned Opcode = MInst->getOpCode();
// do not process Phis
continue;
// Reset tmp stack positions so they can be reused for each machine instr.
- mcInfo.popAllTempValues(TM);
+ MF.popAllTempValues(TM);
// Now insert speical instructions (if necessary) for call/return
// instructions.
//
if (TM.getInstrInfo().isCall(Opcode) ||
- TM.getInstrInfo().isReturn(Opcode)) {
-
- AddedInstrns &AI = AddedInstrMap[MInst];
+ TM.getInstrInfo().isReturn(Opcode)) {
+ AddedInstrns &AI = AddedInstrMap[MInst];
- if (TM.getInstrInfo().isCall(Opcode))
- MRI.colorCallArgs(MInst, LRI, &AI, *this, BBI);
- else if (TM.getInstrInfo().isReturn(Opcode))
- MRI.colorRetValue(MInst, LRI, &AI);
+ if (TM.getInstrInfo().isCall(Opcode))
+ MRI.colorCallArgs(MInst, LRI, &AI, *this, MBB.getBasicBlock());
+ else if (TM.getInstrInfo().isReturn(Opcode))
+ MRI.colorRetValue(MInst, LRI, &AI);
}
// Set the registers for operands in the machine instruction
for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum)
{
MachineOperand& Op = MInst->getOperand(OpNum);
- if (Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
- Op.getOperandType() == MachineOperand::MO_CCRegister)
+ if (Op.getType() == MachineOperand::MO_VirtualRegister ||
+ Op.getType() == MachineOperand::MO_CCRegister)
{
const Value *const Val = Op.getVRegValue();
continue;
}
- if (LR->hasColor() )
+ if (LR->hasColor())
MInst->SetRegForOperand(OpNum,
MRI.getUnifiedRegNum(LR->getRegClass()->getID(),
LR->getColor()));
else
// LR did NOT receive a color (register). Insert spill code.
- insertCode4SpilledLR(LR, MInst, BBI, OpNum );
+ insertCode4SpilledLR(LR, MInst, MBB.getBasicBlock(), OpNum);
}
} // for each operand
-
-
+
// Now add instructions that the register allocator inserts before/after
// this machine instructions (done only for calls/rets/incoming args)
// We do this here, to ensure that spill for an instruction is inserted
// closest as possible to an instruction (see above insertCode4Spill...)
//
+ // First, if the instruction in the delay slot of a branch needs
+ // instructions inserted, move it out of the delay slot and before the
+ // branch because putting code before or after it would be VERY BAD!
+ //
+ unsigned bumpIteratorBy = 0;
+ if (MII != MBB.begin())
+ if (unsigned predDelaySlots =
+ TM.getInstrInfo().getNumDelaySlots((*(MII-1))->getOpCode()))
+ {
+ assert(predDelaySlots==1 && "Not handling multiple delay slots!");
+ if (TM.getInstrInfo().isBranch((*(MII-1))->getOpCode())
+ && (AddedInstrMap.count(MInst) ||
+ AddedInstrMap[MInst].InstrnsAfter.size() > 0))
+ {
+ // Current instruction is in the delay slot of a branch and it
+ // needs spill code inserted before or after it.
+ // Move it before the preceding branch.
+ InsertBefore(MInst, MBB, --MII);
+ MachineInstr* nopI =
+ new MachineInstr(TM.getInstrInfo().getNOPOpCode());
+ SubstituteInPlace(nopI, MBB, MII+1); // replace orig with NOP
+ --MII; // point to MInst in new location
+ bumpIteratorBy = 2; // later skip the branch and the NOP!
+ }
+ }
+
// If there are instructions to be added, *before* this machine
// instruction, add them now.
//
if (AddedInstrMap.count(MInst)) {
- PrependInstructions(AddedInstrMap[MInst].InstrnsBefore, MIVec, MII,"");
+ PrependInstructions(AddedInstrMap[MInst].InstrnsBefore, MBB, MII,"");
}
// If there are instructions to be added *after* this machine
// added after it must really go after the delayed instruction(s)
// So, we move the InstrAfter of the current instruction to the
// corresponding delayed instruction
-
- unsigned delay;
- if ((delay=TM.getInstrInfo().getNumDelaySlots(MInst->getOpCode())) >0){
+ if (unsigned delay =
+ TM.getInstrInfo().getNumDelaySlots(MInst->getOpCode())) {
+
+ // Delayed instructions are typically branches or calls. Let's make
+ // sure this is not a branch, otherwise "insert-after" is meaningless,
+ // and should never happen for any reason (spill code, register
+ // restores, etc.).
+ assert(! TM.getInstrInfo().isBranch(MInst->getOpCode()) &&
+ ! TM.getInstrInfo().isReturn(MInst->getOpCode()) &&
+ "INTERNAL ERROR: Register allocator should not be inserting "
+ "any code after a branch or return!");
+
move2DelayedInstr(MInst, *(MII+delay) );
}
else {
// Here we can add the "instructions after" to the current
// instruction since there are no delay slots for this instruction
- AppendInstructions(AddedInstrMap[MInst].InstrnsAfter, MIVec, MII,"");
+ AppendInstructions(AddedInstrMap[MInst].InstrnsAfter, MBB, MII,"");
} // if not delay
}
-
+
+ // If we mucked with the instruction order above, adjust the loop iterator
+ if (bumpIteratorBy)
+ MII = MII + bumpIteratorBy;
+
} // for each machine instruction
}
}
const BasicBlock *BB,
const unsigned OpNum) {
- assert(! TM.getInstrInfo().isCall(MInst->getOpCode()) &&
- (! TM.getInstrInfo().isReturn(MInst->getOpCode())) &&
- "Arg of a call/ret must be handled elsewhere");
+ assert((! TM.getInstrInfo().isCall(MInst->getOpCode()) || OpNum == 0) &&
+ "Outgoing arg of a call must be handled elsewhere (func arg ok)");
+ assert(! TM.getInstrInfo().isReturn(MInst->getOpCode()) &&
+ "Return value of a ret must be handled elsewhere");
MachineOperand& Op = MInst->getOperand(OpNum);
bool isDef = MInst->operandIsDefined(OpNum);
RegClass *RC = LR->getRegClass();
const ValueSet &LVSetBef = LVI->getLiveVarSetBeforeMInst(MInst, BB);
- mcInfo.pushTempValue(TM, MRI.getSpilledRegSize(RegType) );
+ MF.pushTempValue(TM, MRI.getSpilledRegSize(RegType) );
vector<MachineInstr*> MIBef, MIAft;
vector<MachineInstr*> AdIMid;
int scratchReg = -1;
if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
{
- scratchReg = this->getUsableUniRegAtMI(scratchRegType, &LVSetBef,
- MInst, MIBef, MIAft);
+ scratchReg = getUsableUniRegAtMI(scratchRegType, &LVSetBef,
+ MInst, MIBef, MIAft);
assert(scratchReg != MRI.getInvalidRegNum());
- MInst->getRegsUsed().insert(scratchReg);
+ MInst->insertUsedReg(scratchReg);
}
if (!isDef || isDefAndUse) {
AI.InstrnsAfter.insert(AI.InstrnsAfter.begin(), MIAft.begin(), MIAft.end());
if (DEBUG_RA) {
- cerr << "\nFor Inst " << *MInst;
- cerr << " - SPILLED LR: "; printSet(*LR);
- cerr << "\n - Added Instructions:";
+ cerr << "\nFor Inst:\n " << *MInst;
+ cerr << "SPILLED LR# " << LR->getUserIGNode()->getIndex();
+ cerr << "; added Instructions:";
for_each(MIBef.begin(), MIBef.end(), std::mem_fun(&MachineInstr::dump));
for_each(MIAft.begin(), MIAft.end(), std::mem_fun(&MachineInstr::dump));
}
std::vector<MachineInstr*>& MIBef,
std::vector<MachineInstr*>& MIAft) {
- RegClass* RC = this->getRegClassByID(MRI.getRegClassIDOfRegType(RegType));
+ RegClass* RC = getRegClassByID(MRI.getRegClassIDOfRegType(RegType));
int RegU = getUnusedUniRegAtMI(RC, MInst, LVSetBef);
// we couldn't find an unused register. Generate code to free up a reg by
// saving it on stack and restoring after the instruction
- int TmpOff = mcInfo.pushTempValue(TM, MRI.getSpilledRegSize(RegType) );
+ int TmpOff = MF.pushTempValue(TM, MRI.getSpilledRegSize(RegType) );
RegU = getUniRegNotUsedByThisInst(RC, MInst);
int scratchRegType = -1;
if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
{
- int scratchReg = this->getUsableUniRegAtMI(scratchRegType, LVSetBef,
- MInst, MIBef, MIAft);
+ int scratchReg = getUsableUniRegAtMI(scratchRegType, LVSetBef,
+ MInst, MIBef, MIAft);
assert(scratchReg != MRI.getInvalidRegNum());
// We may as well hold the value in the scratch register instead
// of copying it to memory and back. But we have to mark the
// register as used by this instruction, so it does not get used
// as a scratch reg. by another operand or anyone else.
- MInst->getRegsUsed().insert(scratchReg);
+ MInst->insertUsedReg(scratchReg);
MRI.cpReg2RegMI(MIBef, RegU, scratchReg, RegType);
MRI.cpReg2RegMI(MIAft, scratchReg, RegU, RegType);
}
// Add the registers already marked as used by the instruction.
// This should include any scratch registers that are used to save
// values across the instruction (e.g., for saving state register values).
- const hash_set<int>& regsUsed = MInst->getRegsUsed();
- for (hash_set<int>::const_iterator SI=regsUsed.begin(), SE=regsUsed.end();
- SI != SE; ++SI)
- {
+ const vector<bool> ®sUsed = MInst->getRegsUsed();
+ for (unsigned i = 0, e = regsUsed.size(); i != e; ++i)
+ if (regsUsed[i]) {
unsigned classId = 0;
- int classRegNum = MRI.getClassRegNum(*SI, classId);
+ int classRegNum = MRI.getClassRegNum(i, classId);
if (RC->getID() == classId)
{
assert(classRegNum < (int) IsColorUsedArr.size() &&
{
const MachineOperand& Op = MInst->getOperand(OpNum);
- if (Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
- Op.getOperandType() == MachineOperand::MO_CCRegister)
+ if (MInst->getOperandType(OpNum) == MachineOperand::MO_VirtualRegister ||
+ MInst->getOperandType(OpNum) == MachineOperand::MO_CCRegister)
if (const Value* Val = Op.getVRegValue())
if (MRI.getRegClassIDOfValue(Val) == RC->getID())
if (Op.getAllocatedRegNum() == -1)
void PhyRegAlloc::printMachineCode()
{
- cerr << "\n;************** Function " << Meth->getName()
+ cerr << "\n;************** Function " << Fn->getName()
<< " *****************\n";
- for (Function::const_iterator BBI = Meth->begin(), BBE = Meth->end();
+ for (MachineFunction::iterator BBI = MF.begin(), BBE = MF.end();
BBI != BBE; ++BBI) {
- cerr << "\n"; printLabel(BBI); cerr << ": ";
+ cerr << "\n"; printLabel(BBI->getBasicBlock()); cerr << ": ";
// get the iterator for machine instructions
- MachineCodeForBasicBlock& MIVec = MachineCodeForBasicBlock::get(BBI);
- MachineCodeForBasicBlock::iterator MII = MIVec.begin();
+ MachineBasicBlock& MBB = *BBI;
+ MachineBasicBlock::iterator MII = MBB.begin();
// iterate over all the machine instructions in BB
- for ( ; MII != MIVec.end(); ++MII) {
+ for ( ; MII != MBB.end(); ++MII) {
MachineInstr *const MInst = *MII;
cerr << "\n\t";
for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
MachineOperand& Op = MInst->getOperand(OpNum);
- if (Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
- Op.getOperandType() == MachineOperand::MO_CCRegister /*||
- Op.getOperandType() == MachineOperand::MO_PCRelativeDisp*/ ) {
+ if (Op.getType() == MachineOperand::MO_VirtualRegister ||
+ Op.getType() == MachineOperand::MO_CCRegister /*||
+ Op.getType() == MachineOperand::MO_PCRelativeDisp*/ ) {
const Value *const Val = Op.getVRegValue () ;
// ****this code is temporary till NULL Values are fixed
}
}
- else if (Op.getOperandType() == MachineOperand::MO_MachineRegister) {
+ else if (Op.getType() == MachineOperand::MO_MachineRegister) {
cerr << "\t" << "%" << MRI.getUnifiedRegName(Op.getMachineRegNum());
}
//----------------------------------------------------------------------------
void PhyRegAlloc::colorIncomingArgs()
{
- const BasicBlock &FirstBB = Meth->front();
- const MachineInstr *FirstMI = MachineCodeForBasicBlock::get(&FirstBB).front();
- assert(FirstMI && "No machine instruction in entry BB");
-
- MRI.colorMethodArgs(Meth, LRI, &AddedInstrAtEntry);
+ MRI.colorMethodArgs(Fn, LRI, &AddedInstrAtEntry);
}
//----------------------------------------------------------------------------
// Used to generate a label for a basic block
//----------------------------------------------------------------------------
-void PhyRegAlloc::printLabel(const Value *const Val) {
+void PhyRegAlloc::printLabel(const Value *Val) {
if (Val->hasName())
cerr << Val->getName();
else
- cerr << "Label" << Val;
+ cerr << "Label" << Val;
}
void PhyRegAlloc::markUnusableSugColors()
{
- if (DEBUG_RA ) cerr << "\nmarking unusable suggested colors ...\n";
-
// hash map iterator
LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
//----------------------------------------------------------------------------
void PhyRegAlloc::allocateStackSpace4SpilledLRs() {
- if (DEBUG_RA) cerr << "\nsetting LR stack offsets ...\n";
+ if (DEBUG_RA) cerr << "\nSetting LR stack offsets for spills...\n";
LiveRangeMapType::const_iterator HMI = LRI.getLiveRangeMap()->begin();
LiveRangeMapType::const_iterator HMIEnd = LRI.getLiveRangeMap()->end();
for ( ; HMI != HMIEnd ; ++HMI) {
if (HMI->first && HMI->second) {
LiveRange *L = HMI->second; // get the LiveRange
- if (!L->hasColor()) // NOTE: ** allocating the size of long Type **
- L->setSpillOffFromFP(mcInfo.allocateSpilledValue(TM, Type::LongTy));
+ if (!L->hasColor()) { // NOTE: ** allocating the size of long Type **
+ int stackOffset = MF.allocateSpilledValue(TM, Type::LongTy);
+ L->setSpillOffFromFP(stackOffset);
+ if (DEBUG_RA)
+ cerr << " LR# " << L->getUserIGNode()->getIndex()
+ << ": stack-offset = " << stackOffset << "\n";
+ }
}
} // for all LR's in hash map
}
//
LRI.constructLiveRanges(); // create LR info
- if (DEBUG_RA)
+ if (DEBUG_RA >= RA_DEBUG_LiveRanges)
LRI.printLiveRanges();
createIGNodeListsAndIGs(); // create IGNode list and IGs
buildInterferenceGraphs(); // build IGs in all reg classes
- if (DEBUG_RA) {
+ if (DEBUG_RA >= RA_DEBUG_LiveRanges) {
// print all LRs in all reg classes
for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
RegClassList[rc]->printIGNodeList();
for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
RegClassList[rc]->printIG();
}
-
LRI.coalesceLRs(); // coalesce all live ranges
-
- if (DEBUG_RA) {
+ if (DEBUG_RA >= RA_DEBUG_LiveRanges) {
// print all LRs in all reg classes
- for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
- RegClassList[ rc ]->printIGNodeList();
+ for (unsigned rc=0; rc < NumOfRegClasses; rc++)
+ RegClassList[rc]->printIGNodeList();
// print IGs in all register classes
- for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
- RegClassList[ rc ]->printIG();
+ for (unsigned rc=0; rc < NumOfRegClasses; rc++)
+ RegClassList[rc]->printIG();
}
// color all register classes using the graph coloring algo
for (unsigned rc=0; rc < NumOfRegClasses ; rc++)
- RegClassList[ rc ]->colorAllRegs();
+ RegClassList[rc]->colorAllRegs();
// Atter grpah coloring, if some LRs did not receive a color (i.e, spilled)
// a poistion for such spilled LRs
//
allocateStackSpace4SpilledLRs();
- mcInfo.popAllTempValues(TM); // TODO **Check
+ MF.popAllTempValues(TM); // TODO **Check
// color incoming args - if the correct color was not received
// insert code to copy to the correct register
updateMachineCode();
if (DEBUG_RA) {
- MachineCodeForMethod::get(Meth).dump();
- printMachineCode(); // only for DEBUGGING
+ cerr << "\n**** Machine Code After Register Allocation:\n\n";
+ MF.dump();
}
}
projects / oota-llvm.git / blobdiff