-/* Title: PhyRegAlloc.h
+/* Title: PhyRegAlloc.h -*- C++ -*-
Author: Ruchira Sasanka
Date: Aug 20, 01
Purpose: This is the main entry point for register allocation.
Notes:
+ =====
* RegisterClasses: Each RegClass accepts a
MachineRegClass which contains machine specific info about that register
* Machine dependent work: All parts of the register coloring algorithm
except coloring of an individual node are machine independent.
- Register allocation must be done as:
+ Register allocation must be done as:
- static const MachineRegInfo MRI = MachineRegInfo(); // machine reg info
+ FunctionLiveVarInfo LVI(*FunctionI ); // compute LV info
+ LVI.analyze();
- MethodLiveVarInfo LVI(*MethodI ); // compute LV info
- LVI.analyze();
+ TargetMachine &target = ....
- PhyRegAlloc PRA(*MethodI, &MRI, &LVI); // allocate regs
- PRA.allocateRegisters();
-
- Assumptions:
- All values in a live range will be of the same physical reg class.
+ PhyRegAlloc PRA(*FunctionI, target, &LVI); // allocate regs
+ PRA.allocateRegisters();
*/
-
-
#ifndef PHY_REG_ALLOC_H
#define PHY_REG_ALLOC_H
-#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/RegClass.h"
#include "llvm/CodeGen/LiveRangeInfo.h"
-#include "llvm/Analysis/LiveVar/MethodLiveVarInfo.h"
-
-#include <deque>
+#include <vector>
+#include <map>
+
+class MachineFunction;
+class MachineRegInfo;
+class FunctionLiveVarInfo;
+class MachineInstr;
+class LoopInfo;
+
+//----------------------------------------------------------------------------
+// Class AddedInstrns:
+// When register allocator inserts new instructions in to the existing
+// instruction stream, it does NOT directly modify the instruction stream.
+// Rather, it creates an object of AddedInstrns and stick it in the
+// AddedInstrMap for an existing instruction. This class contains two vectors
+// to store such instructions added before and after an existing instruction.
+//----------------------------------------------------------------------------
+
+struct AddedInstrns {
+ std::vector<MachineInstr*> InstrnsBefore;//Insts added BEFORE an existing inst
+ std::vector<MachineInstr*> InstrnsAfter; //Insts added AFTER an existing inst
+};
-class AddedInstrns
-{
- public:
- deque<MachineInstr *> InstrnsBefore;
- deque<MachineInstr *> InstrnsAfter;
+typedef std::map<const MachineInstr *, AddedInstrns> AddedInstrMapType;
- AddedInstrns() : InstrnsBefore(), InstrnsAfter() { }
-};
-typedef hash_map<const MachineInstr *, AddedInstrns *> AddedInstrMapType;
+//----------------------------------------------------------------------------
+// class PhyRegAlloc:
+// Main class the register allocator. Call allocateRegisters() to allocate
+// registers for a Function.
+//----------------------------------------------------------------------------
-class PhyRegAlloc
-{
+class PhyRegAlloc: public NonCopyable {
- vector<RegClass *> RegClassList ; // vector of register classes
- const Method *const Meth; // name of the method we work on
+ std::vector<RegClass *> RegClassList; // vector of register classes
const TargetMachine &TM; // target machine
- MethodLiveVarInfo *const LVI; // LV information for this method
+ const Function *Fn; // name of the function we work on
+ MachineFunction &MF; // descriptor for method's native code
+ FunctionLiveVarInfo *const LVI; // LV information for this method
// (already computed for BBs)
LiveRangeInfo LRI; // LR info (will be computed)
const MachineRegInfo &MRI; // Machine Register information
const unsigned NumOfRegClasses; // recorded here for efficiency
- //vector<const Instruction *> CallInstrList; // a list of all call instrs
- //vector<const Instruction *> RetInstrList; // a list of all return instrs
-
+
AddedInstrMapType AddedInstrMap; // to store instrns added in this phase
+ AddedInstrns AddedInstrAtEntry; // to store instrns added at entry
+ LoopInfo *LoopDepthCalc; // to calculate loop depths
+ ReservedColorListType ResColList; // A set of reserved regs if desired.
+ // currently not used
+
+public:
+ PhyRegAlloc(Function *F, const TargetMachine& TM, FunctionLiveVarInfo *Lvi,
+ LoopInfo *LoopDepthCalc);
+ ~PhyRegAlloc();
+
+ // main method called for allocating registers
+ //
+ void allocateRegisters();
+
+
+ // access to register classes by class ID
+ //
+ const RegClass* getRegClassByID(unsigned int id) const {
+ return RegClassList[id];
+ }
+ RegClass* getRegClassByID(unsigned int id) {
+ return RegClassList[id]; }
+
+
+private:
- //------- private methods ---------------------------------------------------
+ //------- ------------------ private methods---------------------------------
- void addInterference(const Value *const Def, const LiveVarSet *const LVSet,
- const bool isCallInst);
+ void addInterference(const Value *Def, const ValueSet *LVSet,
+ bool isCallInst);
void addInterferencesForArgs();
void createIGNodeListsAndIGs();
void buildInterferenceGraphs();
- void insertCallerSavingCode(const MachineInstr *MInst,
- const BasicBlock *BB );
void setCallInterferences(const MachineInstr *MInst,
- const LiveVarSet *const LVSetAft );
+ const ValueSet *LVSetAft );
+
+ void move2DelayedInstr(const MachineInstr *OrigMI,
+ const MachineInstr *DelayedMI );
void markUnusableSugColors();
+ void allocateStackSpace4SpilledLRs();
+
+ void insertCode4SpilledLR (const LiveRange *LR,
+ MachineInstr *MInst,
+ const BasicBlock *BB,
+ const unsigned OpNum);
- inline void constructLiveRanges()
- { LRI.constructLiveRanges(); }
+ inline void constructLiveRanges() { LRI.constructLiveRanges(); }
void colorIncomingArgs();
void colorCallRetArgs();
void printLabel(const Value *const Val);
void printMachineCode();
-
- public:
- PhyRegAlloc(const Method *const M, const TargetMachine& TM,
- MethodLiveVarInfo *const Lvi);
-
- void allocateRegisters(); // main method called for allocatin
-
-};
-
+ friend class UltraSparcRegInfo;
+ int getUsableUniRegAtMI(int RegType,
+ const ValueSet *LVSetBef,
+ MachineInstr *MInst,
+ std::vector<MachineInstr*>& MIBef,
+ std::vector<MachineInstr*>& MIAft);
+
+ int getUnusedUniRegAtMI(RegClass *RC, const MachineInstr *MInst,
+ const ValueSet *LVSetBef);
+ void setRelRegsUsedByThisInst(RegClass *RC, const MachineInstr *MInst );
+ int getUniRegNotUsedByThisInst(RegClass *RC, const MachineInstr *MInst);
+ void addInterf4PseudoInstr(const MachineInstr *MInst);
+};
#endif
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