-//===-- SparcV9CodeEmitter.cpp - --------===//
+//===-- SparcV9CodeEmitter.cpp --------------------------------------------===//
//
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// SPARC-specific backend for emitting machine code to memory.
+//
+// This module also contains the code for lazily resolving the targets of call
+// instructions, including the callback used to redirect calls to functions for
+// which the code has not yet been generated into the JIT compiler.
+//
+// This file #includes SparcV9GenCodeEmitter.inc, which contains the code for
+// getBinaryCodeForInstr(), a method that converts a MachineInstr into the
+// corresponding binary machine code word.
//
//===----------------------------------------------------------------------===//
#include "llvm/GlobalVariable.h"
#include "llvm/PassManager.h"
#include "llvm/CodeGen/MachineCodeEmitter.h"
-#include "llvm/CodeGen/MachineFunctionInfo.h"
+#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetData.h"
-#include "Support/hash_set"
-#include "SparcInternals.h"
+#include "llvm/Support/Debug.h"
+#include "SparcV9Internals.h"
+#include "SparcV9TargetMachine.h"
+#include "SparcV9RegInfo.h"
#include "SparcV9CodeEmitter.h"
-
-bool UltraSparc::addPassesToEmitMachineCode(PassManager &PM,
- MachineCodeEmitter &MCE) {
- //PM.add(new SparcV9CodeEmitter(MCE));
- //MachineCodeEmitter *M = MachineCodeEmitter::createDebugMachineCodeEmitter();
- MachineCodeEmitter *M = MachineCodeEmitter::createFilePrinterEmitter(MCE);
- PM.add(new SparcV9CodeEmitter(this, *M));
- PM.add(createMachineCodeDestructionPass()); // Free stuff no longer needed
+#include "SparcV9Relocations.h"
+#include "MachineFunctionInfo.h"
+using namespace llvm;
+
+bool SparcV9TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
+ MachineCodeEmitter &MCE) {
+ PM.add(new SparcV9CodeEmitter(*this, MCE));
+ PM.add(createSparcV9MachineCodeDestructionPass());
return false;
}
-namespace {
- class JITResolver {
- MachineCodeEmitter &MCE;
-
- // LazyCodeGenMap - Keep track of call sites for functions that are to be
- // lazily resolved.
- std::map<unsigned, Function*> LazyCodeGenMap;
-
- // LazyResolverMap - Keep track of the lazy resolver created for a
- // particular function so that we can reuse them if necessary.
- std::map<Function*, unsigned> LazyResolverMap;
- public:
- JITResolver(MachineCodeEmitter &mce) : MCE(mce) {}
- unsigned getLazyResolver(Function *F);
- unsigned addFunctionReference(unsigned Address, Function *F);
-
- private:
- unsigned emitStubForFunction(Function *F);
- static void CompilationCallback();
- unsigned resolveFunctionReference(unsigned RetAddr);
- };
-
- JITResolver *TheJITResolver;
-}
-
-/// addFunctionReference - This method is called when we need to emit the
-/// address of a function that has not yet been emitted, so we don't know the
-/// address. Instead, we emit a call to the CompilationCallback method, and
-/// keep track of where we are.
-///
-unsigned JITResolver::addFunctionReference(unsigned Address, Function *F) {
- LazyCodeGenMap[Address] = F;
- return (intptr_t)&JITResolver::CompilationCallback;
-}
-
-unsigned JITResolver::resolveFunctionReference(unsigned RetAddr) {
- std::map<unsigned, Function*>::iterator I = LazyCodeGenMap.find(RetAddr);
- assert(I != LazyCodeGenMap.end() && "Not in map!");
- Function *F = I->second;
- LazyCodeGenMap.erase(I);
- return MCE.forceCompilationOf(F);
-}
-
-unsigned JITResolver::getLazyResolver(Function *F) {
- std::map<Function*, unsigned>::iterator I = LazyResolverMap.lower_bound(F);
- if (I != LazyResolverMap.end() && I->first == F) return I->second;
-
-//std::cerr << "Getting lazy resolver for : " << ((Value*)F)->getName() << "\n";
-
- unsigned Stub = emitStubForFunction(F);
- LazyResolverMap.insert(I, std::make_pair(F, Stub));
- return Stub;
-}
-
-void JITResolver::CompilationCallback() {
- uint64_t *StackPtr = (uint64_t*)__builtin_frame_address(0);
- uint64_t RetAddr = (uint64_t)(intptr_t)__builtin_return_address(0);
-
-#if 0
- std::cerr << "In callback! Addr=0x" << std::hex << RetAddr
- << " SP=0x" << (unsigned)StackPtr << std::dec
- << ": Resolving call to function: "
- << TheVM->getFunctionReferencedName((void*)RetAddr) << "\n";
-#endif
-
- std::cerr << "Sparc's JIT Resolver not implemented!\n";
- abort();
-
-#if 0
- unsigned NewVal = TheJITResolver->resolveFunctionReference((void*)RetAddr);
-
- // Rewrite the call target... so that we don't fault every time we execute
- // the call.
- *(unsigned*)RetAddr = NewVal;
-
- // Change the return address to reexecute the call instruction...
- StackPtr[1] -= 4;
-#endif
-}
-
-/// emitStubForFunction - This method is used by the JIT when it needs to emit
-/// the address of a function for a function whose code has not yet been
-/// generated. In order to do this, it generates a stub which jumps to the lazy
-/// function compiler, which will eventually get fixed to call the function
-/// directly.
-///
-unsigned JITResolver::emitStubForFunction(Function *F) {
-#if 0
- MCE.startFunctionStub(*F, 6);
- MCE.emitByte(0xE8); // Call with 32 bit pc-rel destination...
-
- unsigned Address = addFunctionReference(MCE.getCurrentPCValue(), F);
- MCE.emitWord(Address-MCE.getCurrentPCValue()-4);
+SparcV9CodeEmitter::SparcV9CodeEmitter(TargetMachine &tm,
+ MachineCodeEmitter &M): TM(tm), MCE(M) {}
- MCE.emitByte(0xCD); // Interrupt - Just a marker identifying the stub!
- return (intptr_t)MCE.finishFunctionStub(*F);
-#endif
- std::cerr << "Sparc's JITResolver::emitStubForFunction() not implemented!\n";
- abort();
+void SparcV9CodeEmitter::emitWord(unsigned Val) {
+ MCE.emitWord(Val);
}
+unsigned
+SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg,
+ MachineInstr &MI) {
+ const SparcV9RegInfo &RI = *TM.getRegInfo();
+ unsigned regClass, regType = RI.getRegType(fakeReg);
+ // At least map fakeReg into its class
+ fakeReg = RI.getClassRegNum(fakeReg, regClass);
-void SparcV9CodeEmitter::emitConstant(unsigned Val, unsigned Size) {
- // Output the constant in big endian byte order...
- unsigned byteVal;
- for (int i = Size-1; i >= 0; --i) {
- byteVal = Val >> 8*i;
- MCE->emitByte(byteVal & 255);
- }
-}
-
-unsigned getRealRegNum(unsigned fakeReg, unsigned regClass) {
switch (regClass) {
- case UltraSparcRegInfo::IntRegType: {
- // Sparc manual, p31
+ case SparcV9RegInfo::IntRegClassID: {
+ // SparcV9 manual, p31
static const unsigned IntRegMap[] = {
// "o0", "o1", "o2", "o3", "o4", "o5", "o7",
8, 9, 10, 11, 12, 13, 15,
// "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
16, 17, 18, 19, 20, 21, 22, 23,
- // "i0", "i1", "i2", "i3", "i4", "i5",
- 24, 25, 26, 27, 28, 29,
- // "i6", "i7",
- 30, 31,
- // "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
+ // "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
+ 24, 25, 26, 27, 28, 29, 30, 31,
+ // "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
0, 1, 2, 3, 4, 5, 6, 7,
// "o6"
14
- };
-
+ };
+
return IntRegMap[fakeReg];
break;
}
- case UltraSparcRegInfo::FPSingleRegType: {
+ case SparcV9RegInfo::FloatRegClassID: {
+ DEBUG(std::cerr << "FP reg: " << fakeReg << "\n");
+ if (regType == SparcV9RegInfo::FPSingleRegType) {
+ // only numbered 0-31, hence can already fit into 5 bits (and 6)
+ DEBUG(std::cerr << "FP single reg, returning: " << fakeReg << "\n");
+ } else if (regType == SparcV9RegInfo::FPDoubleRegType) {
+ // FIXME: This assumes that we only have 5-bit register fields!
+ // From SparcV9 Manual, page 40.
+ // The bit layout becomes: b[4], b[3], b[2], b[1], b[5]
+ fakeReg |= (fakeReg >> 5) & 1;
+ fakeReg &= 0x1f;
+ DEBUG(std::cerr << "FP double reg, returning: " << fakeReg << "\n");
+ }
return fakeReg;
}
- case UltraSparcRegInfo::FPDoubleRegType: {
- return fakeReg;
+ case SparcV9RegInfo::IntCCRegClassID: {
+ /* xcc, icc, ccr */
+ static const unsigned IntCCReg[] = { 6, 4, 2 };
+
+ assert(fakeReg < sizeof(IntCCReg)/sizeof(IntCCReg[0])
+ && "CC register out of bounds for IntCCReg map");
+ DEBUG(std::cerr << "IntCC reg: " << IntCCReg[fakeReg] << "\n");
+ return IntCCReg[fakeReg];
}
- case UltraSparcRegInfo::FloatCCRegType: {
+ case SparcV9RegInfo::FloatCCRegClassID: {
+ /* These are laid out %fcc0 - %fcc3 => 0 - 3, so are correct */
+ DEBUG(std::cerr << "FP CC reg: " << fakeReg << "\n");
return fakeReg;
-
}
- case UltraSparcRegInfo::IntCCRegType: {
- return fakeReg;
+ case SparcV9RegInfo::SpecialRegClassID: {
+ // Currently only "special" reg is %fsr, which is encoded as 1 in
+ // instructions and 0 in SparcV9SpecialRegClass.
+ static const unsigned SpecialReg[] = { 1 };
+ assert(fakeReg < sizeof(SpecialReg)/sizeof(SpecialReg[0])
+ && "Special register out of bounds for SpecialReg map");
+ DEBUG(std::cerr << "Special reg: " << SpecialReg[fakeReg] << "\n");
+ return SpecialReg[fakeReg];
}
default:
- assert(0 && "Invalid unified register number in getRegType");
+ assert(0 && "Invalid unified register number in getRealRegNum");
return fakeReg;
}
}
+
+
int64_t SparcV9CodeEmitter::getMachineOpValue(MachineInstr &MI,
MachineOperand &MO) {
int64_t rv = 0; // Return value; defaults to 0 for unhandled cases
// or things that get fixed up later by the JIT.
-
- if (MO.isVirtualRegister()) {
- std::cerr << "ERROR: virtual register found in machine code.\n";
- abort();
- } else if (MO.isPCRelativeDisp()) {
+ if (MO.isPCRelativeDisp() || MO.isGlobalAddress()) {
+ DEBUG(std::cerr << "PCRelativeDisp: ");
Value *V = MO.getVRegValue();
if (BasicBlock *BB = dyn_cast<BasicBlock>(V)) {
- std::cerr << "Saving reference to BB (VReg)\n";
- unsigned* CurrPC = (unsigned*)(intptr_t)MCE->getCurrentPCValue();
+ DEBUG(std::cerr << "Saving reference to BB (VReg)\n");
+ unsigned* CurrPC = (unsigned*)(intptr_t)MCE.getCurrentPCValue();
BBRefs.push_back(std::make_pair(BB, std::make_pair(CurrPC, &MI)));
- } else if (Constant *C = dyn_cast<Constant>(V)) {
- if (ConstantMap.find(C) != ConstantMap.end())
- rv = (int64_t)(intptr_t)ConstantMap[C] - MCE->getCurrentPCValue();
- else {
- std::cerr << "ERROR: constant not in map:" << MO << "\n";
- abort();
+ } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
+ // The real target of the branch is CI = PC + (rv * 4)
+ // So undo that: give the instruction (CI - PC) / 4
+ rv = (CI->getRawValue() - MCE.getCurrentPCValue()) / 4;
+ } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
+ unsigned Reloc = 0;
+ if (MI.getOpcode() == V9::CALL) {
+ Reloc = V9::reloc_pcrel_call;
+ } else if (MI.getOpcode() == V9::SETHI) {
+ if (MO.isHiBits64())
+ Reloc = V9::reloc_sethi_hh;
+ else if (MO.isHiBits32())
+ Reloc = V9::reloc_sethi_lm;
+ else
+ assert(0 && "Unknown relocation!");
+ } else if (MI.getOpcode() == V9::ORi) {
+ if (MO.isLoBits32())
+ Reloc = V9::reloc_or_lo;
+ else if (MO.isLoBits64())
+ Reloc = V9::reloc_or_hm;
+ else
+ assert(0 && "Unknown relocation!");
+ } else {
+ assert(0 && "Unknown relocation!");
}
+
+ MCE.addRelocation(MachineRelocation(MCE.getCurrentPCOffset(), Reloc, GV));
+ rv = 0;
} else {
std::cerr << "ERROR: PC relative disp unhandled:" << MO << "\n";
abort();
}
- } else if (MO.isPhysicalRegister()) {
- // This is necessary because the Sparc doesn't actually lay out registers
- // in the real fashion -- it skips those that it chooses not to allocate,
- // i.e. those that are the SP, etc.
- unsigned fakeReg = MO.getReg(), realReg, regClass, regType;
- regType = TM->getRegInfo().getRegType(fakeReg);
- // At least map fakeReg into its class
- fakeReg = TM->getRegInfo().getClassRegNum(fakeReg, regClass);
- // Find the real register number for use in an instruction
- realReg = getRealRegNum(fakeReg, regClass);
- std::cerr << "Reg[" << std::dec << fakeReg << "] = " << realReg << "\n";
- rv = realReg;
+ } else if (MO.isRegister() || MO.getType() == MachineOperand::MO_CCRegister)
+ {
+ // This is necessary because the SparcV9 backend doesn't actually lay out
+ // registers in the real fashion -- it skips those that it chooses not to
+ // allocate, i.e. those that are the FP, SP, etc.
+ unsigned fakeReg = MO.getReg();
+ unsigned realRegByClass = getRealRegNum(fakeReg, MI);
+ DEBUG(std::cerr << MO << ": Reg[" << std::dec << fakeReg << "] => "
+ << realRegByClass << " (LLC: "
+ << TM.getRegInfo()->getUnifiedRegName(fakeReg) << ")\n");
+ rv = realRegByClass;
} else if (MO.isImmediate()) {
rv = MO.getImmedValue();
- } else if (MO.isGlobalAddress()) {
- rv = (int64_t)
- (intptr_t)getGlobalAddress(cast<GlobalValue>(MO.getVRegValue()),
- MI, MO.isPCRelative());
+ DEBUG(std::cerr << "immed: " << rv << "\n");
} else if (MO.isMachineBasicBlock()) {
- // Duplicate code of the above case for VirtualRegister, BasicBlock...
- // It should really hit this case, but Sparc backend uses VRegs instead
- std::cerr << "Saving reference to MBB\n";
- BasicBlock *BB = MO.getMachineBasicBlock()->getBasicBlock();
- unsigned* CurrPC = (unsigned*)(intptr_t)MCE->getCurrentPCValue();
+ // Duplicate code of the above case for VirtualRegister, BasicBlock...
+ // It should really hit this case, but SparcV9 backend uses VRegs instead
+ DEBUG(std::cerr << "Saving reference to MBB\n");
+ const BasicBlock *BB = MO.getMachineBasicBlock()->getBasicBlock();
+ unsigned* CurrPC = (unsigned*)(intptr_t)MCE.getCurrentPCValue();
BBRefs.push_back(std::make_pair(BB, std::make_pair(CurrPC, &MI)));
} else if (MO.isExternalSymbol()) {
- // Sparc backend doesn't generate this (yet...)
+ // SparcV9 backend doesn't generate this (yet...)
std::cerr << "ERROR: External symbol unhandled: " << MO << "\n";
abort();
} else if (MO.isFrameIndex()) {
- // Sparc backend doesn't generate this (yet...)
+ // SparcV9 backend doesn't generate this (yet...)
int FrameIndex = MO.getFrameIndex();
std::cerr << "ERROR: Frame index unhandled.\n";
abort();
} else if (MO.isConstantPoolIndex()) {
- // Sparc backend doesn't generate this (yet...)
- std::cerr << "ERROR: Constant Pool index unhandled.\n";
- abort();
+ unsigned Index = MO.getConstantPoolIndex();
+ rv = MCE.getConstantPoolEntryAddress(Index);
} else {
std::cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
abort();
// are used in SPARC assembly. (Some of these make no sense in combination
// with some of the above; we'll trust that the instruction selector
// will not produce nonsense, and not check for valid combinations here.)
- if (MO.opLoBits32()) { // %lo(val)
+ if (MO.isLoBits32()) { // %lo(val) == %lo() in SparcV9 ABI doc
return rv & 0x03ff;
- } else if (MO.opHiBits32()) { // %lm(val)
+ } else if (MO.isHiBits32()) { // %lm(val) == %hi() in SparcV9 ABI doc
return (rv >> 10) & 0x03fffff;
- } else if (MO.opLoBits64()) { // %hm(val)
+ } else if (MO.isLoBits64()) { // %hm(val) == %ulo() in SparcV9 ABI doc
return (rv >> 32) & 0x03ff;
- } else if (MO.opHiBits64()) { // %hh(val)
+ } else if (MO.isHiBits64()) { // %hh(val) == %uhi() in SparcV9 ABI doc
return rv >> 42;
} else { // (unadorned) val
return rv;
return (Val & 1);
}
-void* SparcV9CodeEmitter::convertAddress(intptr_t Addr, bool isPCRelative) {
- if (isPCRelative) {
- return (void*)(Addr - (intptr_t)MCE->getCurrentPCValue());
- } else {
- return (void*)Addr;
- }
-}
-
-
-
bool SparcV9CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
- std::cerr << "Starting function " << MF.getFunction()->getName()
- << ", address: " << "0x" << std::hex
- << (long)MCE->getCurrentPCValue() << "\n";
-
- MCE->startFunction(MF);
-
- // FIXME: the Sparc backend does not use the ConstantPool!!
- //MCE->emitConstantPool(MF.getConstantPool());
-
- // Instead, the Sparc backend has its own constant pool implementation:
- const hash_set<const Constant*> &pool = MF.getInfo()->getConstantPoolValues();
- for (hash_set<const Constant*>::const_iterator I = pool.begin(),
- E = pool.end(); I != E; ++I)
- {
- const Constant *C = *I;
- // For now we just allocate some memory on the heap, this can be
- // dramatically improved.
- const Type *Ty = ((Value*)C)->getType();
- void *Addr = malloc(TM->getTargetData().getTypeSize(Ty));
- //FIXME
- //TheVM.InitializeMemory(C, Addr);
- std::cerr << "Adding ConstantMap[" << C << "]=" << std::dec << Addr << "\n";
- ConstantMap[C] = Addr;
- }
+ MCE.startFunction(MF);
+ DEBUG(std::cerr << "Starting function " << MF.getFunction()->getName()
+ << ", address: " << "0x" << std::hex
+ << (long)MCE.getCurrentPCValue() << "\n");
+ MCE.emitConstantPool(MF.getConstantPool());
for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
emitBasicBlock(*I);
- MCE->finishFunction(MF);
+ MCE.finishFunction(MF);
- std::cerr << "Finishing function " << MF.getFunction()->getName() << "\n";
- ConstantMap.clear();
- for (unsigned i = 0, e = BBRefs.size(); i != e; ++i) {
- long Location = BBLocations[BBRefs[i].first];
- unsigned *Ref = BBRefs[i].second.first;
- MachineInstr *MI = BBRefs[i].second.second;
- std::cerr << "Fixup @" << std::hex << Ref << " to " << Location
- << " in instr: " << std::dec << *MI << "\n";
- }
+ DEBUG(std::cerr << "Finishing fn " << MF.getFunction()->getName() << "\n");
// Resolve branches to BasicBlocks for the entire function
for (unsigned i = 0, e = BBRefs.size(); i != e; ++i) {
long Location = BBLocations[BBRefs[i].first];
unsigned *Ref = BBRefs[i].second.first;
MachineInstr *MI = BBRefs[i].second.second;
- std::cerr << "attempting to resolve BB: " << i << "\n";
+ DEBUG(std::cerr << "Fixup @ " << std::hex << Ref << " to 0x" << Location
+ << " in instr: " << std::dec << *MI);
for (unsigned ii = 0, ee = MI->getNumOperands(); ii != ee; ++ii) {
MachineOperand &op = MI->getOperand(ii);
if (op.isPCRelativeDisp()) {
// the instruction's branch target is made such that it branches to
- // PC + (br target * 4), so undo that arithmetic here:
+ // PC + (branchTarget * 4), so undo that arithmetic here:
// Location is the target of the branch
// Ref is the location of the instruction, and hence the PC
- unsigned branchTarget = (Location - (long)Ref) >> 2;
+ int64_t branchTarget = (Location - (long)Ref) >> 2;
// Save the flags.
- bool loBits32=false, hiBits32=false, loBits64=false, hiBits64=false;
- if (op.opLoBits32()) { loBits32=true; }
- if (op.opHiBits32()) { hiBits32=true; }
- if (op.opLoBits64()) { loBits64=true; }
- if (op.opHiBits64()) { hiBits64=true; }
+ bool loBits32=false, hiBits32=false, loBits64=false, hiBits64=false;
+ if (op.isLoBits32()) { loBits32=true; }
+ if (op.isHiBits32()) { hiBits32=true; }
+ if (op.isLoBits64()) { loBits64=true; }
+ if (op.isHiBits64()) { hiBits64=true; }
MI->SetMachineOperandConst(ii, MachineOperand::MO_SignExtendedImmed,
branchTarget);
- if (loBits32) { MI->setOperandLo32(ii); }
- else if (hiBits32) { MI->setOperandHi32(ii); }
- else if (loBits64) { MI->setOperandLo64(ii); }
- else if (hiBits64) { MI->setOperandHi64(ii); }
- std::cerr << "Rewrote BB ref: ";
+ if (loBits32) { MI->getOperand(ii).markLo32(); }
+ else if (hiBits32) { MI->getOperand(ii).markHi32(); }
+ else if (loBits64) { MI->getOperand(ii).markLo64(); }
+ else if (hiBits64) { MI->getOperand(ii).markHi64(); }
+ DEBUG(std::cerr << "Rewrote BB ref: ");
unsigned fixedInstr = SparcV9CodeEmitter::getBinaryCodeForInstr(*MI);
- *Ref = fixedInstr;
+ MCE.emitWordAt (fixedInstr, Ref);
break;
}
}
void SparcV9CodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
currBB = MBB.getBasicBlock();
- BBLocations[currBB] = MCE->getCurrentPCValue();
+ BBLocations[currBB] = MCE.getCurrentPCValue();
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I)
- emitInstruction(**I);
-}
-
-void SparcV9CodeEmitter::emitInstruction(MachineInstr &MI) {
- emitConstant(getBinaryCodeForInstr(MI), 4);
-}
-
-void* SparcV9CodeEmitter::getGlobalAddress(GlobalValue *V, MachineInstr &MI,
- bool isPCRelative)
-{
- if (isPCRelative) { // must be a call, this is a major hack!
- // Try looking up the function to see if it is already compiled!
- if (void *Addr = (void*)(intptr_t)MCE->getGlobalValueAddress(V)) {
- intptr_t CurByte = MCE->getCurrentPCValue();
- // The real target of the call is Addr = PC + (target * 4)
- // CurByte is the PC, Addr we just received
- return (void*) (((long)Addr - (long)CurByte) >> 2);
+ if (I->getOpcode() != V9::RDCCR) {
+ emitWord(getBinaryCodeForInstr(*I));
} else {
- if (Function *F = dyn_cast<Function>(V)) {
- // Function has not yet been code generated!
- TheJITResolver->addFunctionReference(MCE->getCurrentPCValue(),
- cast<Function>(V));
- // Delayed resolution...
- return
- (void*)(intptr_t)TheJITResolver->getLazyResolver(cast<Function>(V));
-
- } else if (Constant *C = ConstantPointerRef::get(V)) {
- if (ConstantMap.find(C) != ConstantMap.end()) {
- return ConstantMap[C];
- } else {
- std::cerr << "Constant: 0x" << std::hex << &*C << std::dec
- << ", " << *V << " not found in ConstantMap!\n";
- abort();
- }
-
-#if 0
- } else if (const GlobalVariable *G = dyn_cast<GlobalVariable>(V)) {
- if (G->isConstant()) {
- const Constant* C = G->getInitializer();
- if (ConstantMap.find(C) != ConstantMap.end()) {
- return ConstantMap[C];
- } else {
- std::cerr << "Constant: " << *G << " not found in ConstantMap!\n";
- abort();
- }
- } else {
- std::cerr << "Variable: " << *G << " address not found!\n";
- abort();
- }
-#endif
- } else {
- std::cerr << "Unhandled global: " << *V << "\n";
- abort();
- }
+ // FIXME: The tblgen produced code emitter cannot deal with the fact that
+ // machine operand #0 of the RDCCR instruction should be ignored. This is
+ // really a bug in the representation of the RDCCR instruction (which has
+ // no need to explicitly represent the CCR dest), but we hack around it
+ // here.
+ unsigned RegNo = getMachineOpValue(*I, I->getOperand(1));
+ RegNo &= (1<<5)-1;
+ emitWord((RegNo << 25) | 2168487936U);
}
- } else {
- return convertAddress((intptr_t)MCE->getGlobalValueAddress(V),
- isPCRelative);
- }
}
-
-#include "SparcV9CodeEmitter.inc"
+#include "SparcV9GenCodeEmitter.inc"
projects / oota-llvm.git / blobdiff