- Added some SSE2 128-bit packed integer ops.

[oota-llvm.git] / lib / Target / SparcV9 / SparcV9CodeEmitter.cpp

diff --git a/lib/Target/SparcV9/SparcV9CodeEmitter.cpp b/lib/Target/SparcV9/SparcV9CodeEmitter.cpp
index 3e7ef3ad217ae9c24b5a139ad85f72c44a4d3ae4..d691a10f76322cc92ee90de1f7e66d02b03a6dc5 100644 (file)
--- a/lib/Target/SparcV9/SparcV9CodeEmitter.cpp
+++ b/lib/Target/SparcV9/SparcV9CodeEmitter.cpp
@@ -1,22 +1,21 @@
 //===-- SparcV9CodeEmitter.cpp --------------------------------------------===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // SPARC-specific backend for emitting machine code to memory.
 //
-// This module also contains the code for lazily resolving the targets
-// of call instructions, including the callback used to redirect calls
-// to functions for which the code has not yet been generated into the
-// JIT compiler.
+// This module also contains the code for lazily resolving the targets of call
+// instructions, including the callback used to redirect calls to functions for
+// which the code has not yet been generated into the JIT compiler.
 //
-// This file #includes SparcV9CodeEmitter.inc, which contains the code
-// for getBinaryCodeForInstr(), a method that converts a MachineInstr
-// into the corresponding binary machine code word.
+// This file #includes SparcV9GenCodeEmitter.inc, which contains the code for
+// getBinaryCodeForInstr(), a method that converts a MachineInstr into the
+// corresponding binary machine code word.
 //
 //===----------------------------------------------------------------------===//
 
@@ -37,6 +36,7 @@
 #include "SparcV9CodeEmitter.h"
 #include "SparcV9Relocations.h"
 #include "MachineFunctionInfo.h"
+#include <iostream>
 using namespace llvm;
 
 bool SparcV9TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
@@ -53,11 +53,11 @@ void SparcV9CodeEmitter::emitWord(unsigned Val) {
   MCE.emitWord(Val);
 }
 
-unsigned 
+unsigned
 SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg,
                                   MachineInstr &MI) {
   const SparcV9RegInfo &RI = *TM.getRegInfo();
-  unsigned regClass, regType = RI.getRegType(fakeReg);
+  unsigned regClass = 0, regType = RI.getRegType(fakeReg);
   // At least map fakeReg into its class
   fakeReg = RI.getClassRegNum(fakeReg, regClass);
 
@@ -71,12 +71,12 @@ SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg,
       16, 17, 18, 19, 20, 21, 22, 23,
       // "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
       24, 25, 26, 27, 28, 29, 30, 31,
-      // "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", 
+      // "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
       0, 1, 2, 3, 4, 5, 6, 7,
       // "o6"
       14
-    }; 
- 
+    };
+
     return IntRegMap[fakeReg];
     break;
   }
@@ -91,16 +91,16 @@ SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg,
       // The bit layout becomes: b[4], b[3], b[2], b[1], b[5]
       fakeReg |= (fakeReg >> 5) & 1;
       fakeReg &= 0x1f;
-      DEBUG(std::cerr << "FP double reg, returning: " << fakeReg << "\n");      
+      DEBUG(std::cerr << "FP double reg, returning: " << fakeReg << "\n");
     }
     return fakeReg;
   }
   case SparcV9RegInfo::IntCCRegClassID: {
     /*                                   xcc, icc, ccr */
     static const unsigned IntCCReg[] = {  6,   4,   2 };
-    
+
     assert(fakeReg < sizeof(IntCCReg)/sizeof(IntCCReg[0])
-             && "CC register out of bounds for IntCCReg map");      
+             && "CC register out of bounds for IntCCReg map");
     DEBUG(std::cerr << "IntCC reg: " << IntCCReg[fakeReg] << "\n");
     return IntCCReg[fakeReg];
   }
@@ -114,7 +114,7 @@ SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg,
     // instructions and 0 in SparcV9SpecialRegClass.
     static const unsigned SpecialReg[] = {  1 };
     assert(fakeReg < sizeof(SpecialReg)/sizeof(SpecialReg[0])
-             && "Special register out of bounds for SpecialReg map");      
+             && "Special register out of bounds for SpecialReg map");
     DEBUG(std::cerr << "Special reg: " << SpecialReg[fakeReg] << "\n");
     return SpecialReg[fakeReg];
   }
@@ -177,14 +177,14 @@ int64_t SparcV9CodeEmitter::getMachineOpValue(MachineInstr &MI,
     unsigned fakeReg = MO.getReg();
     unsigned realRegByClass = getRealRegNum(fakeReg, MI);
     DEBUG(std::cerr << MO << ": Reg[" << std::dec << fakeReg << "] => "
-                    << realRegByClass << " (LLC: " 
+                    << realRegByClass << " (LLC: "
                     << TM.getRegInfo()->getUnifiedRegName(fakeReg) << ")\n");
     rv = realRegByClass;
   } else if (MO.isImmediate()) {
     rv = MO.getImmedValue();
     DEBUG(std::cerr << "immed: " << rv << "\n");
   } else if (MO.isMachineBasicBlock()) {
-    // Duplicate code of the above case for VirtualRegister, BasicBlock... 
+    // Duplicate code of the above case for VirtualRegister, BasicBlock...
     // It should really hit this case, but SparcV9 backend uses VRegs instead
     DEBUG(std::cerr << "Saving reference to MBB\n");
     const BasicBlock *BB = MO.getMachineBasicBlock()->getBasicBlock();
@@ -232,7 +232,7 @@ unsigned SparcV9CodeEmitter::getValueBit(int64_t Val, unsigned bit) {
 bool SparcV9CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
   MCE.startFunction(MF);
   DEBUG(std::cerr << "Starting function " << MF.getFunction()->getName()
-            << ", address: " << "0x" << std::hex 
+            << ", address: " << "0x" << std::hex
             << (long)MCE.getCurrentPCValue() << "\n");
 
   MCE.emitConstantPool(MF.getConstantPool());
@@ -258,7 +258,7 @@ bool SparcV9CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
         // Ref is the location of the instruction, and hence the PC
         int64_t branchTarget = (Location - (long)Ref) >> 2;
         // Save the flags.
-        bool loBits32=false, hiBits32=false, loBits64=false, hiBits64=false;   
+        bool loBits32=false, hiBits32=false, loBits64=false, hiBits64=false;
         if (op.isLoBits32()) { loBits32=true; }
         if (op.isHiBits32()) { hiBits32=true; }
         if (op.isLoBits64()) { loBits64=true; }
@@ -300,5 +300,5 @@ void SparcV9CodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
     }
 }
 
-#include "SparcV9CodeEmitter.inc"
+#include "SparcV9GenCodeEmitter.inc"