Printing support for more stuff

[oota-llvm.git] / lib / Target / SparcV9 / SparcV9Internals.h

diff --git a/lib/Target/SparcV9/SparcV9Internals.h b/lib/Target/SparcV9/SparcV9Internals.h
index 01315baa19e2f203d8a5cadec53ccd76daaa4ee4..31ec6a25b2a283965b18b106205730f2bdc266cc 100644 (file)
--- a/lib/Target/SparcV9/SparcV9Internals.h
+++ b/lib/Target/SparcV9/SparcV9Internals.h
@@ -22,13 +22,6 @@ class UltraSparc;
 class PhyRegAlloc;
 class Pass;
 
-// OpCodeMask definitions for the Sparc V9
-// 
-const OpCodeMask       Immed           = 0x00002000; // immed or reg operand?
-const OpCodeMask       Annul           = 0x20000000; // annul delay instr?
-const OpCodeMask       PredictTaken    = 0x00080000; // predict branch taken?
-
-
 enum SparcInstrSchedClass {
   SPARC_NONE,          /* Instructions with no scheduling restrictions */
   SPARC_IEUN,          /* Integer class that can use IEU0 or IEU1 */
@@ -83,7 +76,7 @@ extern const MachineInstrDescriptor SparcMachineInstrDesc[];
 //---------------------------------------------------------------------------
 
 struct UltraSparcInstrInfo : public MachineInstrInfo {
-  UltraSparcInstrInfo(const TargetMachine& tgt);
+  UltraSparcInstrInfo();
 
   //
   // All immediate constants are in position 1 except the
@@ -194,8 +187,8 @@ struct UltraSparcInstrInfo : public MachineInstrInfo {
   virtual void CreateSignExtensionInstructions(const TargetMachine& target,
                                        Function* F,
                                        Value* srcVal,
-                                       unsigned int srcSizeInBits,
-                                       Value* dest,
+                                       Value* destVal,
+                                       unsigned int numLowBits,
                                        std::vector<MachineInstr*>& mvec,
                                        MachineCodeForInstruction& mcfi) const;
 
@@ -208,8 +201,8 @@ struct UltraSparcInstrInfo : public MachineInstrInfo {
   virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
                                        Function* F,
                                        Value* srcVal,
-                                       unsigned int srcSizeInBits,
-                                       Value* dest,
+                                       Value* destVal,
+                                       unsigned int numLowBits,
                                        std::vector<MachineInstr*>& mvec,
                                        MachineCodeForInstruction& mcfi) const;
 };
@@ -250,10 +243,6 @@ class UltraSparcRegInfo : public MachineRegInfo {
   // order for efficiency.
 
 
-  // reverse pointer to get info about the ultra sparc machine
-  //
-  const UltraSparc *const UltraSparcInfo;
-
   // Number of registers used for passing int args (usually 6: %o0 - %o5)
   //
   unsigned const NumOfIntArgRegs;
@@ -277,8 +266,7 @@ class UltraSparcRegInfo : public MachineRegInfo {
   void suggestReg4RetAddr(MachineInstr *RetMI, 
                          LiveRangeInfo &LRI) const;
 
-  void suggestReg4CallAddr(MachineInstr *CallMI, LiveRangeInfo &LRI,
-                          std::vector<RegClass *> RCList) const;
+  void suggestReg4CallAddr(MachineInstr *CallMI, LiveRangeInfo &LRI) const;
   
   void InitializeOutgoingArg(MachineInstr* CallMI, AddedInstrns *CallAI,
                              PhyRegAlloc &PRA, LiveRange* LR,
@@ -330,13 +318,6 @@ class UltraSparcRegInfo : public MachineRegInfo {
 public:
   UltraSparcRegInfo(const UltraSparc &tgt);
 
-  // To get complete machine information structure using the machine register
-  // information
-  //
-  inline const UltraSparc &getUltraSparcInfo() const { 
-    return *UltraSparcInfo;
-  }
-
   // To find the register class used for a specified Type
   //
   unsigned getRegClassIDOfType(const Type *type,
@@ -384,8 +365,7 @@ public:
                              LiveRangeInfo& LRI) const;
 
   void suggestRegs4CallArgs(MachineInstr *CallMI, 
-                           LiveRangeInfo& LRI,
-                            std::vector<RegClass *> RCL) const; 
+                           LiveRangeInfo& LRI) const; 
 
   void suggestReg4RetValue(MachineInstr *RetMI, 
                            LiveRangeInfo& LRI) const;
@@ -573,32 +553,32 @@ public:
   // particular function.  The frame contents are obtained from the
   // MachineCodeInfoForMethod object for the given function.
   // 
-  int getFirstIncomingArgOffset  (MachineCodeForMethod& mcInfo,
+  int getFirstIncomingArgOffset  (MachineFunction& mcInfo,
                                   bool& growUp) const
   {
     growUp = true;                         // arguments area grows upwards
     return FirstIncomingArgOffsetFromFP;
   }
-  int getFirstOutgoingArgOffset  (MachineCodeForMethod& mcInfo,
+  int getFirstOutgoingArgOffset  (MachineFunction& mcInfo,
                                   bool& growUp) const
   {
     growUp = true;                         // arguments area grows upwards
     return FirstOutgoingArgOffsetFromSP;
   }
-  int getFirstOptionalOutgoingArgOffset(MachineCodeForMethod& mcInfo,
+  int getFirstOptionalOutgoingArgOffset(MachineFunction& mcInfo,
                                         bool& growUp)const
   {
     growUp = true;                         // arguments area grows upwards
     return FirstOptionalOutgoingArgOffsetFromSP;
   }
   
-  int getFirstAutomaticVarOffset (MachineCodeForMethod& mcInfo,
+  int getFirstAutomaticVarOffset (MachineFunction& mcInfo,
                                   bool& growUp) const;
-  int getRegSpillAreaOffset      (MachineCodeForMethod& mcInfo,
+  int getRegSpillAreaOffset      (MachineFunction& mcInfo,
                                   bool& growUp) const;
-  int getTmpAreaOffset           (MachineCodeForMethod& mcInfo,
+  int getTmpAreaOffset           (MachineFunction& mcInfo,
                                   bool& growUp) const;
-  int getDynamicAreaOffset       (MachineCodeForMethod& mcInfo,
+  int getDynamicAreaOffset       (MachineFunction& mcInfo,
                                   bool& growUp) const;
 
   //
@@ -722,7 +702,6 @@ public:
 //---------------------------------------------------------------------------
 
 class UltraSparc : public TargetMachine {
-private:
   UltraSparcInstrInfo instrInfo;
   UltraSparcSchedInfo schedInfo;
   UltraSparcRegInfo   regInfo;
@@ -739,17 +718,19 @@ public:
   virtual const MachineCacheInfo &getCacheInfo() const { return cacheInfo; }
   virtual const MachineOptInfo   &getOptInfo()   const { return optInfo; }
 
-  // getPrologEpilogCodeInserter - Inserts prolog/epilog code.
-  virtual Pass* getPrologEpilogInsertionPass();
+  virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
+
+  // getPrologEpilogInsertionPass - Inserts prolog/epilog code.
+  Pass* getPrologEpilogInsertionPass();
 
   // getFunctionAsmPrinterPass - Writes out machine code for a single function
-  virtual Pass* getFunctionAsmPrinterPass(std::ostream &Out);
+  Pass* getFunctionAsmPrinterPass(std::ostream &Out);
 
   // getModuleAsmPrinterPass - Writes generated machine code to assembly file.
-  virtual Pass* getModuleAsmPrinterPass(std::ostream &Out);
+  Pass* getModuleAsmPrinterPass(std::ostream &Out);
 
   // getEmitBytecodeToAsmPass - Emits final LLVM bytecode to assembly file.
-  virtual Pass* getEmitBytecodeToAsmPass(std::ostream &Out);
+  Pass* getEmitBytecodeToAsmPass(std::ostream &Out);
 };
 
 #endif