Added phi elimination code

[oota-llvm.git] / lib / Target / SparcV9 / SparcV9Internals.h

diff --git a/lib/Target/SparcV9/SparcV9Internals.h b/lib/Target/SparcV9/SparcV9Internals.h
index abcd756ad93c76544e770c1d8ebf6c518bf754d2..9b8fe177ef2753ca32638582630994477dbb5e65 100644 (file)
--- a/lib/Target/SparcV9/SparcV9Internals.h
+++ b/lib/Target/SparcV9/SparcV9Internals.h
@@ -16,8 +16,9 @@
 #include "SparcRegClassInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/MachineInstrInfo.h"
-#include "llvm/Target/MachineFrameInfo.h"
 #include "llvm/Target/MachineSchedInfo.h"
+#include "llvm/Target/MachineFrameInfo.h"
+#include "llvm/Target/MachineCacheInfo.h"
 #include "llvm/CodeGen/RegClass.h"
 #include "llvm/Type.h"
 
@@ -115,9 +116,9 @@ public:
                                       vector<TmpInstruction*>& tempVec) const;
 
   
-  // Create an instruction sequence to copy an integer value `val' from an
-  // integer to a floating point register `dest'.  val must be an integral
-  // type.  dest must be a Float or Double.
+  // Create an instruction sequence to copy an integer value `val'
+  // to a floating point value `dest' by copying to memory and back.
+  // val must be an integral type.  dest must be a Float or Double.
   // The generated instructions are returned in `minstrVec'.
   // Any temp. registers (TmpInstruction) created are returned in `tempVec'.
   // 
@@ -127,6 +128,26 @@ public:
                                            vector<MachineInstr*>& minstrVec,
                                            vector<TmpInstruction*>& tempVec,
                                            TargetMachine& target) const;
+
+  // Similarly, create an instruction sequence to copy an FP value
+  // `val' to an integer value `dest' by copying to memory and back.
+  // See the previous function for information about return values.
+  // 
+  virtual void  CreateCodeToCopyFloatToInt(Method* method,
+                                           Value* val,
+                                           Instruction* dest,
+                                           vector<MachineInstr*>& minstrVec,
+                                           vector<TmpInstruction*>& tempVec,
+                                           TargetMachine& target) const;
+
+ // create copy instruction(s)
+  virtual void
+  CreateCopyInstructionsByType(const TargetMachine& target,
+                             Value* src,
+                             Instruction* dest,
+                             vector<MachineInstr*>& minstrVec) const;
+
+
 };
 
 
@@ -259,6 +280,22 @@ class UltraSparcRegInfo : public MachineRegInfo
   }
 
 
+  int getRegType(int reg) const {
+    if( reg < 32 ) 
+      return IntRegType;
+    else if ( reg < (32 + 32) )
+      return FPSingleRegType;
+    else if ( reg < (64 + 32) )
+      return FPDoubleRegType;
+    else if( reg < (64+32+4) )
+      return FloatCCRegType;
+    else if( reg < (64+32+4+2) )  
+      return IntCCRegType;             
+    else 
+      assert(0 && "Invalid register number in getRegType");
+  }
+
+
 
   // ***TODO: See this method is necessary
 
@@ -272,6 +309,21 @@ class UltraSparcRegInfo : public MachineRegInfo
   MachineInstr * cpCCR2IntMI(const unsigned IntReg) const;
   MachineInstr * cpInt2CCRMI(const unsigned IntReg) const;
 
+
+
+  void moveInst2OrdVec(vector<MachineInstr *> &OrdVec, MachineInstr *UnordInst,
+                      PhyRegAlloc &PRA ) const;
+
+  void OrderAddedInstrns( vector<MachineInstr *> &UnordVec, 
+                         vector<MachineInstr *> &OrdVec,
+                         PhyRegAlloc &PRA) const;
+
+
+
+
+
+
+
  public:
 
 
@@ -1229,17 +1281,34 @@ public:
   }
   
 private:
+  // All stack addresses must be offset by 0x7ff (2047) on Sparc V9.
+  static const int OFFSET                                  = (int) 0x7ff;
   static const int StackFrameSizeAlignment                 =  16;
   static const int MinStackFrameSize                       = 176;
   static const int NumFixedOutgoingArgs                    =   6;
   static const int SizeOfEachArgOnStack                    =   8;
-  static const int StaticAreaOffsetFromFP                  =  -1;
-  static const int FirstIncomingArgOffsetFromFP            = 126;
-  static const int FirstOutgoingArgOffsetFromSP            = 128;
-  static const int FirstOptionalOutgoingArgOffsetFromSP    = 176;
+  static const int StaticAreaOffsetFromFP                  =  0 + OFFSET;
+  static const int FirstIncomingArgOffsetFromFP            = 128 + OFFSET;
+  static const int FirstOptionalIncomingArgOffsetFromFP    = 176 + OFFSET;
+  static const int FirstOutgoingArgOffsetFromSP            = 128 + OFFSET;
+  static const int FirstOptionalOutgoingArgOffsetFromSP    = 176 + OFFSET;
 };
 
 
+//---------------------------------------------------------------------------
+// class UltraSparcCacheInfo 
+// 
+// Purpose:
+//   Interface to cache parameters for the UltraSPARC.
+//   Just use defaults for now.
+//---------------------------------------------------------------------------
+
+class UltraSparcCacheInfo: public MachineCacheInfo {
+public:
+  /*ctor*/          UltraSparcCacheInfo  (const TargetMachine& target) :
+    MachineCacheInfo(target) {} 
+};
+
 
 //---------------------------------------------------------------------------
 // class UltraSparcMachine 
@@ -1257,6 +1326,7 @@ private:
   UltraSparcSchedInfo schedInfo;
   UltraSparcRegInfo   regInfo;
   UltraSparcFrameInfo frameInfo;
+  UltraSparcCacheInfo cacheInfo;
 public:
   UltraSparc();
   virtual ~UltraSparc() {}
@@ -1265,6 +1335,7 @@ public:
   virtual const MachineSchedInfo &getSchedInfo() const { return schedInfo; }
   virtual const MachineRegInfo   &getRegInfo()   const { return regInfo; }
   virtual const MachineFrameInfo &getFrameInfo() const { return frameInfo; }
+  virtual const MachineCacheInfo &getCacheInfo() const { return cacheInfo; }
   
   // compileMethod - For the sparc, we do instruction selection, followed by
   // delay slot scheduling, then register allocation.