-//===-- SparcInternals.h - Header file for Sparc backend ---------*- C++ -*--=//
-//
-// This file defines stuff that is to be private to the Sparc backend, but is
-// shared among different portions of the backend.
-//
-//===----------------------------------------------------------------------===//
+// $Id$ -*- C++ -*--
+//***************************************************************************
+// File:
+// SparcInternals.h
+//
+// Purpose:
+// This file defines stuff that is to be private to the Sparc
+// backend, but is shared among different portions of the backend.
+//**************************************************************************/
+
#ifndef SPARC_INTERNALS_H
#define SPARC_INTERNALS_H
-#include "llvm/Target/Machine.h"
-#include "SparcRegInfo.h"
-#include <sys/types.h>
+#include "SparcRegClassInfo.h"
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/MachineSchedInfo.h"
+#include "llvm/Target/MachineFrameInfo.h"
+#include "llvm/Target/MachineCacheInfo.h"
+#include "llvm/CodeGen/RegClass.h"
#include "llvm/Type.h"
+#include <sys/types.h>
+
class UltraSparc;
// OpCodeMask definitions for the Sparc V9
SPARC_NUM_SCHED_CLASSES = SPARC_INV
};
-// inline operator int (const SparcInstrSchedClass& si) {
-// return (int) si;
-// }
-//
-// inline operator SparcInstrSchedClass (int i) {
-// return (SparcInstrSchedClass) si;
-// }
-//
-// inline operator const SparcInstrSchedClass (int i) {
-// return (const SparcInstrSchedClass) si;
-// }
//---------------------------------------------------------------------------
// enum SparcMachineOpCode.
//
//---------------------------------------------------------------------------
-
enum SparcMachineOpCode {
+#define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
+ NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
+ ENUM,
+#include "SparcInstr.def"
- NOP,
-
- // Synthetic SPARC assembly opcodes for setting a register to a constant
- SETSW,
- SETUW,
-
- // Set high-order bits of register and clear low-order bits
- SETHI,
-
- // Add or add with carry.
- // Immed bit specifies if second operand is immediate(1) or register(0)
- ADD,
- ADDcc,
- ADDC,
- ADDCcc,
-
- // Subtract or subtract with carry.
- // Immed bit specifies if second operand is immediate(1) or register(0)
- SUB,
- SUBcc,
- SUBC,
- SUBCcc,
-
- // Integer multiply, signed divide, unsigned divide.
- // Note that the deprecated 32-bit multiply and multiply-step are not used.
- MULX,
- SDIVX,
- UDIVX,
-
- // Floating point add, subtract, compare
- FADDS,
- FADDD,
- FADDQ,
- FSUBS,
- FSUBD,
- FSUBQ,
- FCMPS,
- FCMPD,
- FCMPQ,
- // NOTE: FCMPE{S,D,Q}: FP Compare With Exception are currently unused!
-
- // Floating point multiply or divide.
- FMULS,
- FMULD,
- FMULQ,
- FSMULD,
- FDMULQ,
- FDIVS,
- FDIVD,
- FDIVQ,
- FSQRTS,
- FSQRTD,
- FSQRTQ,
-
- // Logical operations
- AND,
- ANDcc,
- ANDN,
- ANDNcc,
- OR,
- ORcc,
- ORN,
- ORNcc,
- XOR,
- XORcc,
- XNOR,
- XNORcc,
-
- // Shift operations
- SLL,
- SRL,
- SRA,
- SLLX,
- SRLX,
- SRAX,
-
- // Floating point move, negate, and abs instructions
- FMOVS,
- FMOVD,
-//FMOVQ,
- FNEGS,
- FNEGD,
-//FNEGQ,
- FABSS,
- FABSD,
-//FABSQ,
-
- // Convert from floating point to floating point formats
- FSTOD,
- FSTOQ,
- FDTOS,
- FDTOQ,
- FQTOS,
- FQTOD,
-
- // Convert from floating point to integer formats
- FSTOX,
- FDTOX,
- FQTOX,
- FSTOI,
- FDTOI,
- FQTOI,
-
- // Convert from integer to floating point formats
- FXTOS,
- FXTOD,
- FXTOQ,
- FITOS,
- FITOD,
- FITOQ,
-
- // Branch on integer comparison with zero.
- // Annul bit specifies if intruction in delay slot is annulled(1) or not(0).
- // PredictTaken bit hints if branch should be predicted taken(1) or not(0).
- BRZ,
- BRLEZ,
- BRLZ,
- BRNZ,
- BRGZ,
- BRGEZ,
-
- // Branch on integer condition code.
- // Annul bit specifies if intruction in delay slot is annulled(1) or not(0).
- // PredictTaken bit hints if branch should be predicted taken(1) or not(0).
- BA,
- BN,
- BNE,
- BE,
- BG,
- BLE,
- BGE,
- BL,
- BGU,
- BLEU,
- BCC,
- BCS,
- BPOS,
- BNEG,
- BVC,
- BVS,
-
- // Branch on floating point condition code.
- // Annul bit specifies if intruction in delay slot is annulled(1) or not(0).
- // PredictTaken bit hints if branch should be predicted taken(1) or not(0).
- FBA,
- FBN,
- FBU,
- FBG,
- FBUG,
- FBL,
- FBUL,
- FBLG,
- FBNE,
- FBE,
- FBUE,
- FBGE,
- FBUGE,
- FBLE,
- FBULE,
- FBO,
-
- // Conditional move on integer comparison with zero.
- MOVRZ,
- MOVRLEZ,
- MOVRLZ,
- MOVRNZ,
- MOVRGZ,
- MOVRGEZ,
-
- // Conditional move on integer condition code.
- MOVA,
- MOVN,
- MOVNE,
- MOVE,
- MOVG,
- MOVLE,
- MOVGE,
- MOVL,
- MOVGU,
- MOVLEU,
- MOVCC,
- MOVCS,
- MOVPOS,
- MOVNEG,
- MOVVC,
- MOVVS,
-
- // Conditional move on floating point condition code.
- // Note that the enum name is not the same as the assembly mnemonic below
- // because that would duplicate some entries with those above.
- // Therefore, we use MOVF here instead of MOV.
- MOVFA,
- MOVFN,
- MOVFU,
- MOVFG,
- MOVFUG,
- MOVFL,
- MOVFUL,
- MOVFLG,
- MOVFNE,
- MOVFE,
- MOVFUE,
- MOVFGE,
- MOVFUGE,
- MOVFLE,
- MOVFULE,
- MOVFO,
-
- // Conditional move of floating point register on each of the above:
- // i. on integer comparison with zero.
- // ii. on integer condition code
- // iii. on floating point condition code
- // Note that the same set is repeated for S,D,Q register classes.
- FMOVRSZ,
- FMOVRSLEZ,
- FMOVRSLZ,
- FMOVRSNZ,
- FMOVRSGZ,
- FMOVRSGEZ,
-
- FMOVSA,
- FMOVSN,
- FMOVSNE,
- FMOVSE,
- FMOVSG,
- FMOVSLE,
- FMOVSGE,
- FMOVSL,
- FMOVSGU,
- FMOVSLEU,
- FMOVSCC,
- FMOVSCS,
- FMOVSPOS,
- FMOVSNEG,
- FMOVSVC,
- FMOVSVS,
-
- FMOVSFA,
- FMOVSFN,
- FMOVSFU,
- FMOVSFG,
- FMOVSFUG,
- FMOVSFL,
- FMOVSFUL,
- FMOVSFLG,
- FMOVSFNE,
- FMOVSFE,
- FMOVSFUE,
- FMOVSFGE,
- FMOVSFUGE,
- FMOVSFLE,
- FMOVSFULE,
- FMOVSFO,
-
- FMOVRDZ,
- FMOVRDLEZ,
- FMOVRDLZ,
- FMOVRDNZ,
- FMOVRDGZ,
- FMOVRDGEZ,
-
- FMOVDA,
- FMOVDN,
- FMOVDNE,
- FMOVDE,
- FMOVDG,
- FMOVDLE,
- FMOVDGE,
- FMOVDL,
- FMOVDGU,
- FMOVDLEU,
- FMOVDCC,
- FMOVDCS,
- FMOVDPOS,
- FMOVDNEG,
- FMOVDVC,
- FMOVDVS,
-
- FMOVDFA,
- FMOVDFN,
- FMOVDFU,
- FMOVDFG,
- FMOVDFUG,
- FMOVDFL,
- FMOVDFUL,
- FMOVDFLG,
- FMOVDFNE,
- FMOVDFE,
- FMOVDFUE,
- FMOVDFGE,
- FMOVDFUGE,
- FMOVDFLE,
- FMOVDFULE,
- FMOVDFO,
-
- FMOVRQZ,
- FMOVRQLEZ,
- FMOVRQLZ,
- FMOVRQNZ,
- FMOVRQGZ,
- FMOVRQGEZ,
-
- FMOVQA,
- FMOVQN,
- FMOVQNE,
- FMOVQE,
- FMOVQG,
- FMOVQLE,
- FMOVQGE,
- FMOVQL,
- FMOVQGU,
- FMOVQLEU,
- FMOVQCC,
- FMOVQCS,
- FMOVQPOS,
- FMOVQNEG,
- FMOVQVC,
- FMOVQVS,
-
- FMOVQFA,
- FMOVQFN,
- FMOVQFU,
- FMOVQFG,
- FMOVQFUG,
- FMOVQFL,
- FMOVQFUL,
- FMOVQFLG,
- FMOVQFNE,
- FMOVQFE,
- FMOVQFUE,
- FMOVQFGE,
- FMOVQFUGE,
- FMOVQFLE,
- FMOVQFULE,
- FMOVQFO,
-
- // Load integer instructions
- LDSB,
- LDSH,
- LDSW,
- LDUB,
- LDUH,
- LDUW,
- LDX,
-
- // Load floating-point instructions
- LD,
- LDD, // use of this for integers is deprecated for Sparc V9
- LDQ,
-
- // Store integer instructions
- STB,
- STH,
- STW,
- STX,
-
- // Store floating-point instructions
- ST,
- STD,
-
- // Call, Return, and "Jump and link"
- // Immed bit specifies if second operand is immediate(1) or register(0)
- CALL,
- JMPL,
- RETURN, // last valid opcode
-
- // Synthetic phi operation for near-SSA form of machine code
- PHI,
-
// End-of-array marker
INVALID_OPCODE,
- NUM_REAL_OPCODES = RETURN+1, // number of valid opcodes
+ NUM_REAL_OPCODES = PHI, // number of valid opcodes
NUM_TOTAL_OPCODES = INVALID_OPCODE
};
-const MachineInstrDescriptor SparcMachineInstrDesc[] = {
-
- // Fields of each structure:
- // opCodeString,
- // numOperands,
- // resultPosition (0-based; -1 if no result),
- // maxImmedConst,
- // immedIsSignExtended,
- // numDelaySlots (in cycles)
- // latency (in cycles)
- // instr sched class (defined above)
- // instr class flags (defined in TargretMachine.h)
-
- { "NOP", 0, -1, 0, false, 0, 1, SPARC_NONE, M_NOP_FLAG },
-
- // Synthetic SPARC assembly opcodes for setting a register to a constant.
- // Max immediate constant should be ignored for both these instructions.
- { "SETSW", 2, 1, 0, true, 0, 1, SPARC_IEUN, M_INT_FLAG | M_ARITH_FLAG },
- { "SETUW", 2, 1, 0, false, 0, 1, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_FLAG | M_ARITH_FLAG },
-
- // Set high-order bits of register and clear low-order bits
- { "SETHI", 2, 1, (1 << 22) - 1, false, 0, 1, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_FLAG | M_ARITH_FLAG },
-
- // Add or add with carry.
- { "ADD", 3, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEUN, M_INT_FLAG | M_ARITH_FLAG },
- { "ADDcc", 4, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEU1, M_INT_FLAG | M_ARITH_FLAG },
- { "ADDC", 3, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEUN, M_INT_FLAG | M_ARITH_FLAG },
- { "ADDCcc", 4, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEU1, M_INT_FLAG | M_ARITH_FLAG },
-
- // Sub tract or subtract with carry.
- { "SUB", 3, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEUN, M_INT_FLAG | M_ARITH_FLAG },
- { "SUBcc", 4, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEU1, M_INT_FLAG | M_ARITH_FLAG },
- { "SUBC", 3, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEUN, M_INT_FLAG | M_ARITH_FLAG },
- { "SUBCcc", 4, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEU1, M_INT_FLAG | M_ARITH_FLAG },
-
- // Integer multiply, signed divide, unsigned divide.
- // Note that the deprecated 32-bit multiply and multiply-step are not used.
- { "MULX", 3, 2, (1 << 12) - 1, true, 0, 3, SPARC_IEUN, M_INT_FLAG | M_ARITH_FLAG },
- { "SDIVX", 3, 2, (1 << 12) - 1, true, 0, 6, SPARC_IEUN, M_INT_FLAG | M_ARITH_FLAG },
- { "UDIVX", 3, 2, (1 << 12) - 1, true, 0, 6, SPARC_IEUN, M_INT_FLAG | M_ARITH_FLAG },
-
- // Floating point add, subtract, compare.
- // Note that destination of FCMP* instructions is operand 0, not operand 2.
- { "FADDS", 3, 2, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG },
- { "FADDD", 3, 2, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG },
- { "FADDQ", 3, 2, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG },
- { "FSUBS", 3, 2, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG },
- { "FSUBD", 3, 2, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG },
- { "FSUBQ", 3, 2, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG },
- { "FCMPS", 3, 0, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG },
- { "FCMPD", 3, 0, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG },
- { "FCMPQ", 3, 0, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG },
- // NOTE: FCMPE{S,D,Q}: FP Compare With Exception are currently unused!
-
- // Floating point multiply or divide.
- { "FMULS", 3, 2, 0, false, 0, 3, SPARC_FPM, M_FLOAT_FLAG | M_ARITH_FLAG },
- { "FMULD", 3, 2, 0, false, 0, 3, SPARC_FPM, M_FLOAT_FLAG | M_ARITH_FLAG },
- { "FMULQ", 3, 2, 0, false, 0, 0, SPARC_FPM, M_FLOAT_FLAG | M_ARITH_FLAG },
- { "FSMULD", 3, 2, 0, false, 0, 3, SPARC_FPM, M_FLOAT_FLAG | M_ARITH_FLAG },
- { "FDMULQ", 3, 2, 0, false, 0, 0, SPARC_FPM, M_FLOAT_FLAG | M_ARITH_FLAG },
- { "FDIVS", 3, 2, 0, false, 0, 12, SPARC_FPM, M_FLOAT_FLAG | M_ARITH_FLAG },
- { "FDIVD", 3, 2, 0, false, 0, 22, SPARC_FPM, M_FLOAT_FLAG | M_ARITH_FLAG },
- { "FDIVQ", 3, 2, 0, false, 0, 0, SPARC_FPM, M_FLOAT_FLAG | M_ARITH_FLAG },
- { "FSQRTS", 3, 2, 0, false, 0, 12, SPARC_FPM, M_FLOAT_FLAG | M_ARITH_FLAG },
- { "FSQRTD", 3, 2, 0, false, 0, 22, SPARC_FPM, M_FLOAT_FLAG | M_ARITH_FLAG },
- { "FSQRTQ", 3, 2, 0, false, 0, 0, SPARC_FPM, M_FLOAT_FLAG | M_ARITH_FLAG },
-
- // Logical operations
- { "AND", 3, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_FLAG},
- { "ANDcc", 4, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEU1, M_INT_FLAG | M_LOGICAL_FLAG},
- { "ANDN", 3, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_FLAG},
- { "ANDNcc", 4, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEU1, M_INT_FLAG | M_LOGICAL_FLAG},
- { "OR", 3, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_FLAG},
- { "ORcc", 4, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEU1, M_INT_FLAG | M_LOGICAL_FLAG},
- { "ORN", 3, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_FLAG},
- { "ORNcc", 4, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEU1, M_INT_FLAG | M_LOGICAL_FLAG},
- { "XOR", 3, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_FLAG},
- { "XORcc", 4, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEU1, M_INT_FLAG | M_LOGICAL_FLAG},
- { "XNOR", 3, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEUN, M_INT_FLAG | M_LOGICAL_FLAG},
- { "XNORcc", 4, 2, (1 << 12) - 1, true, 0, 1, SPARC_IEU1, M_INT_FLAG | M_LOGICAL_FLAG},
-
- // Shift operations
- { "SLL", 3, 2, (1 << 5) - 1, true, 0, 1, SPARC_IEU0, M_INT_FLAG | M_LOGICAL_FLAG},
- { "SRL", 3, 2, (1 << 5) - 1, true, 0, 1, SPARC_IEU0, M_INT_FLAG | M_LOGICAL_FLAG},
- { "SRA", 3, 2, (1 << 5) - 1, true, 0, 1, SPARC_IEU0, M_INT_FLAG | M_ARITH_FLAG },
- { "SLLX", 3, 2, (1 << 6) - 1, true, 0, 1, SPARC_IEU0, M_INT_FLAG | M_LOGICAL_FLAG},
- { "SRLX", 3, 2, (1 << 6) - 1, true, 0, 1, SPARC_IEU0, M_INT_FLAG | M_LOGICAL_FLAG},
- { "SRAX", 3, 2, (1 << 6) - 1, true, 0, 1, SPARC_IEU0, M_INT_FLAG | M_ARITH_FLAG },
-
- // Floating point move, negate, and abs instructions
- { "FMOVS", 2, 1, 0, false, 0, 1, SPARC_FPA, M_FLOAT_FLAG },
- { "FMOVD", 2, 1, 0, false, 0, 1, SPARC_FPA, M_FLOAT_FLAG },
-//{ "FMOVQ", 2, 1, 0, false, 0, ?, SPARC_FPA, M_FLOAT_FLAG },
- { "FNEGS", 2, 1, 0, false, 0, 1, SPARC_FPA, M_FLOAT_FLAG },
- { "FNEGD", 2, 1, 0, false, 0, 1, SPARC_FPA, M_FLOAT_FLAG },
-//{ "FNEGQ", 2, 1, 0, false, 0, ?, SPARC_FPA, M_FLOAT_FLAG },
- { "FABSS", 2, 1, 0, false, 0, 1, SPARC_FPA, M_FLOAT_FLAG },
- { "FABSD", 2, 1, 0, false, 0, 1, SPARC_FPA, M_FLOAT_FLAG },
-//{ "FABSQ", 2, 1, 0, false, 0, ?, SPARC_FPA, M_FLOAT_FLAG },
-
- // Convert from floating point to floating point formats
- { "FSTOD", 2, 1, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG },
- { "FSTOQ", 2, 1, 0, false, 0, 0, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG },
- { "FDTOS", 2, 1, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG },
- { "FDTOQ", 2, 1, 0, false, 0, 0, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG },
- { "FQTOS", 2, 1, 0, false, 0, 0, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG },
- { "FQTOD", 2, 1, 0, false, 0, 0, SPARC_FPA, M_FLOAT_FLAG | M_ARITH_FLAG },
-
- // Convert from floating point to integer formats.
- // Note that this accesses both integer and floating point registers.
- { "FSTOX", 2, 1, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG },
- { "FDTOX", 2, 1, 0, false, 0, 0, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG },
- { "FQTOX", 2, 1, 0, false, 0, 2, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG },
- { "FSTOI", 2, 1, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG },
- { "FDTOI", 2, 1, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG },
- { "FQTOI", 2, 1, 0, false, 0, 0, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG },
-
- // Convert from integer to floating point formats
- // Note that this accesses both integer and floating point registers.
- { "FXTOS", 2, 1, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG },
- { "FXTOD", 2, 1, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG },
- { "FXTOQ", 2, 1, 0, false, 0, 0, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG },
- { "FITOS", 2, 1, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG },
- { "FITOD", 2, 1, 0, false, 0, 3, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG },
- { "FITOQ", 2, 1, 0, false, 0, 0, SPARC_FPA, M_FLOAT_FLAG | M_INT_FLAG | M_ARITH_FLAG },
-
- // Branch on integer comparison with zero.
- // Latency includes the delay slot.
- { "BRZ", 2, -1, (1 << 15) - 1, true, 1, 2, SPARC_CTI, M_INT_FLAG | M_BRANCH_FLAG },
- { "BRLEZ", 2, -1, (1 << 15) - 1, true, 1, 2, SPARC_CTI, M_INT_FLAG | M_BRANCH_FLAG },
- { "BRLZ", 2, -1, (1 << 15) - 1, true, 1, 2, SPARC_CTI, M_INT_FLAG | M_BRANCH_FLAG },
- { "BRNZ", 2, -1, (1 << 15) - 1, true, 1, 2, SPARC_CTI, M_INT_FLAG | M_BRANCH_FLAG },
- { "BRGZ", 2, -1, (1 << 15) - 1, true, 1, 2, SPARC_CTI, M_INT_FLAG | M_BRANCH_FLAG },
- { "BRGEZ", 2, -1, (1 << 15) - 1, true, 1, 2, SPARC_CTI, M_INT_FLAG | M_BRANCH_FLAG },
-
- // Branch on condition code.
- // The first argument specifies the ICC register: %icc or %xcc
- // Latency includes the delay slot.
- { "BA", 2, -1, (1 << 21) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG },
- { "BN", 2, -1, (1 << 21) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG },
- { "BNE", 2, -1, (1 << 21) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG },
- { "BE", 2, -1, (1 << 21) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG },
- { "BG", 2, -1, (1 << 21) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG },
- { "BLE", 2, -1, (1 << 21) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG },
- { "BGE", 2, -1, (1 << 21) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG },
- { "BL", 2, -1, (1 << 21) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG },
- { "BGU", 2, -1, (1 << 21) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG },
- { "BLEU", 2, -1, (1 << 21) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG },
- { "BCC", 2, -1, (1 << 21) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG },
- { "BCS", 2, -1, (1 << 21) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG },
- { "BPOS", 2, -1, (1 << 21) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG },
- { "BNEG", 2, -1, (1 << 21) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG },
- { "BVC", 2, -1, (1 << 21) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG },
- { "BVS", 2, -1, (1 << 21) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG },
-
- // Branch on floating point condition code.
- // Annul bit specifies if intruction in delay slot is annulled(1) or not(0).
- // PredictTaken bit hints if branch should be predicted taken(1) or not(0).
- // The first argument is the FCCn register (0 <= n <= 3).
- // Latency includes the delay slot.
- { "FBA", 2, -1, (1 << 18) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG },
- { "FBN", 2, -1, (1 << 18) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG },
- { "FBU", 2, -1, (1 << 18) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG },
- { "FBG", 2, -1, (1 << 18) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG },
- { "FBUG", 2, -1, (1 << 18) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG },
- { "FBL", 2, -1, (1 << 18) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG },
- { "FBUL", 2, -1, (1 << 18) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG },
- { "FBLG", 2, -1, (1 << 18) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG },
- { "FBNE", 2, -1, (1 << 18) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG },
- { "FBE", 2, -1, (1 << 18) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG },
- { "FBUE", 2, -1, (1 << 18) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG },
- { "FBGE", 2, -1, (1 << 18) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG },
- { "FBUGE", 2, -1, (1 << 18) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG },
- { "FBLE", 2, -1, (1 << 18) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG },
- { "FBULE", 2, -1, (1 << 18) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG },
- { "FBO", 2, -1, (1 << 18) - 1, true, 1, 2, SPARC_CTI, M_CC_FLAG | M_BRANCH_FLAG },
-
- // Conditional move on integer comparison with zero.
- { "MOVRZ", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG },
- { "MOVRLEZ", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG },
- { "MOVRLZ", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG },
- { "MOVRNZ", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG },
- { "MOVRGZ", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG },
- { "MOVRGEZ", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_INT_FLAG },
-
- // Conditional move on integer condition code.
- // The first argument specifies the ICC register: %icc or %xcc
- { "MOVA", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG },
- { "MOVN", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG },
- { "MOVNE", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG },
- { "MOVE", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG },
- { "MOVG", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG },
- { "MOVLE", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG },
- { "MOVGE", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG },
- { "MOVL", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG },
- { "MOVGU", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG },
- { "MOVLEU", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG },
- { "MOVCC", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG },
- { "MOVCS", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG },
- { "MOVPOS", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG },
- { "MOVNEG", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG },
- { "MOVVC", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG },
- { "MOVVS", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG },
-
- // Conditional move (of integer register) on floating point condition code.
- // The first argument is the FCCn register (0 <= n <= 3).
- // Note that the enum name above is not the same as the assembly mnemonic
- // because some of the assembly mnemonics are the same as the move on
- // integer CC (e.g., MOVG), and we cannot have the same enum entry twice.
- { "MOVA", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG },
- { "MOVN", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG },
- { "MOVU", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG },
- { "MOVG", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG },
- { "MOVUG", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG },
- { "MOVL", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG },
- { "MOVUL", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG },
- { "MOVLG", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG },
- { "MOVNE", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG },
- { "MOVE", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG },
- { "MOVUE", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG },
- { "MOVGE", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG },
- { "MOVUGE", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG },
- { "MOVLE", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG },
- { "MOVULE", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG },
- { "MOVO", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_INT_FLAG },
-
- // Conditional move of floating point register on each of the above:
- // i. on integer comparison with zero.
- // ii. on integer condition code
- // iii. on floating point condition code
- // Note that the same set is repeated for S,D,Q register classes.
- { "FMOVRSZ", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG },
- { "FMOVRSLEZ",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG },
- { "FMOVRSLZ", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG },
- { "FMOVRSNZ", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG },
- { "FMOVRSGZ", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG },
- { "FMOVRSGEZ",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG },
-
- { "FMOVSA", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVSN", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVSNE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVSE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVSG", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVSLE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVSGE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVSL", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVSGU", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVSLEU", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVSCC", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVSCS", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVSPOS", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVSNEG", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVSVC", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVSVS", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
-
- { "FMOVSA", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVSN", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVSU", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVSG", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVSUG", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVSL", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVSUL", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVSLG", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVSNE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVSE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVSUE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVSGE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVSUGE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVSLE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVSULE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVSO", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
-
- { "FMOVRDZ", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG },
- { "FMOVRDLEZ",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG },
- { "FMOVRDLZ", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG },
- { "FMOVRDNZ", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG },
- { "FMOVRDGZ", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG },
- { "FMOVRDGEZ",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG },
-
- { "FMOVDA", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVDN", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVDNE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVDE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVDG", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVDLE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVDGE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVDL", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVDGU", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVDLEU", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVDCC", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVDCS", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVDPOS", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVDNEG", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVDVC", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVDVS", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
-
- { "FMOVDA", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVDN", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVDU", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVDG", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVDUG", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVDL", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVDUL", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVDLG", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVDNE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVDE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVDUE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVDGE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVDUGE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVDLE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVDULE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVDO", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
-
- { "FMOVRQZ", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG },
- { "FMOVRQLEZ",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG },
- { "FMOVRQLZ", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG },
- { "FMOVRQNZ", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG },
- { "FMOVRQGZ", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG },
- { "FMOVRQGEZ",3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CONDL_FLAG | M_FLOAT_FLAG | M_INT_FLAG },
-
- { "FMOVQA", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVQN", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVQNE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVQE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVQG", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVQLE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVQGE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVQL", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVQGU", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVQLEU", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVQCC", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVQCS", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVQPOS", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVQNEG", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVQVC", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVQVS", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
-
- { "FMOVQA", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVQN", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVQU", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVQG", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVQUG", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVQL", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVQUL", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVQLG", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVQNE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVQE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVQUE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVQGE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVQUGE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVQLE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVQULE", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
- { "FMOVQO", 3, 2, 0, false, 0, 2, SPARC_SINGLE, M_CC_FLAG | M_FLOAT_FLAG },
-
- // Load integer instructions
- // Latency includes 1 cycle for address generation (Sparc IIi)
- // Signed loads of less than 64 bits need an extra cycle for sign-extension.
- //
- // Not reflected here: After a 3-cycle loads, all subsequent consecutive
- // loads also require 3 cycles to avoid contention for the load return
- // stage. Latency returns to 2 cycles after the first cycle with no load.
- { "LDSB", 3, 2, (1 << 12) - 1, true, 0, 3, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG },
- { "LDSH", 3, 2, (1 << 12) - 1, true, 0, 3, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG },
- { "LDSW", 3, 2, (1 << 12) - 1, true, 0, 3, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG },
- { "LDUB", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG },
- { "LDUH", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG },
- { "LDUW", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG },
- { "LDX", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_LD, M_INT_FLAG | M_LOAD_FLAG },
-
- // Load floating-point instructions
- // Latency includes 1 cycle for address generation (Sparc IIi)
- { "LD", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_LD, M_FLOAT_FLAG | M_LOAD_FLAG },
- { "LDD", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_LD, M_FLOAT_FLAG | M_LOAD_FLAG },
- { "LDQ", 3, 2, (1 << 12) - 1, true, 0, 2, SPARC_LD, M_FLOAT_FLAG | M_LOAD_FLAG },
-
- // Store integer instructions
- // Latency includes 1 cycle for address generation (Sparc IIi)
- { "STB", 3, -1, (1 << 12) - 1, true, 0, 2, SPARC_ST, M_INT_FLAG | M_STORE_FLAG },
- { "STH", 3, -1, (1 << 12) - 1, true, 0, 2, SPARC_ST, M_INT_FLAG | M_STORE_FLAG },
- { "STW", 3, -1, (1 << 12) - 1, true, 0, 2, SPARC_ST, M_INT_FLAG | M_STORE_FLAG },
- { "STX", 3, -1, (1 << 12) - 1, true, 0, 3, SPARC_ST, M_INT_FLAG | M_STORE_FLAG },
-
- // Store floating-point instructions (Sparc IIi)
- { "ST", 3, -1, (1 << 12) - 1, true, 0, 2, SPARC_ST, M_FLOAT_FLAG | M_STORE_FLAG},
- { "STD", 3, -1, (1 << 12) - 1, true, 0, 2, SPARC_ST, M_FLOAT_FLAG | M_STORE_FLAG},
-
- // Call, Return and "Jump and link".
- // Latency includes the delay slot.
- { "CALL", 1, -1, (1 << 29) - 1, true, 1, 2, SPARC_CTI, M_BRANCH_FLAG | M_CALL_FLAG},
- { "JMPL", 3, -1, (1 << 12) - 1, true, 1, 2, SPARC_CTI, M_BRANCH_FLAG | M_CALL_FLAG},
- { "RETURN", 2, -1, 0, false, 1, 2, SPARC_CTI, M_BRANCH_FLAG | M_RET_FLAG },
-
- // Synthetic phi operation for near-SSA form of machine code
- // Number of operands is variable, indicated by -1. Result is the first op.
-
- { "PHI", -1, 0, 0, false, 0, 0, SPARC_INV, M_DUMMY_PHI_FLAG },
-
-};
+// Array of machine instruction descriptions...
+extern const MachineInstrDescriptor SparcMachineInstrDesc[];
//---------------------------------------------------------------------------
class UltraSparcInstrInfo : public MachineInstrInfo {
public:
- /*ctor*/ UltraSparcInstrInfo();
+ /*ctor*/ UltraSparcInstrInfo(const TargetMachine& tgt);
- virtual bool hasResultInterlock (MachineOpCode opCode)
+ virtual bool hasResultInterlock (MachineOpCode opCode) const
{
// All UltraSPARC instructions have interlocks (note that delay slots
// are not considered here).
return (opCode == FCMPS || opCode == FCMPD || opCode == FCMPQ);
}
+ //-------------------------------------------------------------------------
+ // Code generation support for creating individual machine instructions
+ //-------------------------------------------------------------------------
+
+ // Create an instruction sequence to put the constant `val' into
+ // the virtual register `dest'. The generated instructions are
+ // returned in `minstrVec'. Any temporary registers (TmpInstruction)
+ // created are returned in `tempVec'.
+ //
+ virtual void CreateCodeToLoadConst(Value* val,
+ Instruction* dest,
+ vector<MachineInstr*>& minstrVec,
+ vector<TmpInstruction*>& tempVec) const;
+
+
+ // Create an instruction sequence to copy an integer value `val'
+ // to a floating point value `dest' by copying to memory and back.
+ // val must be an integral type. dest must be a Float or Double.
+ // The generated instructions are returned in `minstrVec'.
+ // Any temp. registers (TmpInstruction) created are returned in `tempVec'.
+ //
+ virtual void CreateCodeToCopyIntToFloat(Method* method,
+ Value* val,
+ Instruction* dest,
+ vector<MachineInstr*>& minstrVec,
+ vector<TmpInstruction*>& tempVec,
+ TargetMachine& target) const;
+
+ // Similarly, create an instruction sequence to copy an FP value
+ // `val' to an integer value `dest' by copying to memory and back.
+ // See the previous function for information about return values.
+ //
+ virtual void CreateCodeToCopyFloatToInt(Method* method,
+ Value* val,
+ Instruction* dest,
+ vector<MachineInstr*>& minstrVec,
+ vector<TmpInstruction*>& tempVec,
+ TargetMachine& target) const;
+
+ // create copy instruction(s)
+ virtual void
+ CreateCopyInstructionsByType(const TargetMachine& target,
+ Value* src,
+ Instruction* dest,
+ vector<MachineInstr*>& minstrVec) const;
+
+
};
-//---------------------------------------------------------------------------
-// class UltraSparcInstrInfo
-//
-// Purpose:
-// This class provides info about sparc register classes.
-//---------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+// class UltraSparcRegInfo
+//
+//----------------------------------------------------------------------------
+
class LiveRange;
+class UltraSparc;
+class PhyRegAlloc;
+
class UltraSparcRegInfo : public MachineRegInfo
{
private:
- enum RegClassIDs { IntRegClassID, FloatRegClassID, FloatCCREgClassID };
+
+ // The actual register classes in the Sparc
+
+ enum RegClassIDs {
+ IntRegClassID,
+ FloatRegClassID,
+ IntCCRegClassID,
+ FloatCCRegClassID
+ };
+
+
+ // Type of registers available in Sparc. There can be several reg types
+ // in the same class. For instace, the float reg class has Single/Double
+ // types
+ enum RegTypes {
+ IntRegType,
+ FPSingleRegType,
+ FPDoubleRegType,
+ IntCCRegType,
+ FloatCCRegType
+ };
+
+ // the size of a value (int, float, etc..) stored in the stack frame
+
+
+
+ // WARNING: If the above enum order must be changed, also modify
+ // getRegisterClassOfValue method below since it assumes this particular
+ // order for efficiency.
+
// reverse pointer to get info about the ultra sparc machine
const UltraSparc *const UltraSparcInfo;
- // Int arguments can be passed in 6 int regs - %o0 to %o5 (cannot be changed)
+ // Both int and float rguments can be passed in 6 int regs -
+ // %o0 to %o5 (cannot be changed)
unsigned const NumOfIntArgRegs;
-
- // Float arguments can be passed in this many regs - can be canged if needed
- // %f0 - %f5 are used (can hold 6 floats or 3 doubles)
unsigned const NumOfFloatArgRegs;
+ int const InvalidRegNum;
+ int SizeOfOperandOnStack;
+
+
+
+ //void setCallArgColor(LiveRange *const LR, const unsigned RegNo) const;
+
+ void setCallOrRetArgCol(LiveRange *const LR, const unsigned RegNo,
+ const MachineInstr *MI,AddedInstrMapType &AIMap)const;
+
+ MachineInstr * getCopy2RegMI(const Value *SrcVal, const unsigned Reg,
+ unsigned RegClassID) const ;
+
+
+ void suggestReg4RetAddr(const MachineInstr * RetMI,
+ LiveRangeInfo& LRI) const;
+
+ void suggestReg4CallAddr(const MachineInstr * CallMI, LiveRangeInfo& LRI,
+ vector<RegClass *> RCList) const;
+
+
+ Value *getValue4ReturnAddr( const MachineInstr * MInst ) const ;
+
+ int getRegType(const LiveRange *const LR) const {
+
+ unsigned Typ;
+
+ switch( (LR->getRegClass())->getID() ) {
+
+ case IntRegClassID: return IntRegType;
+
+ case FloatRegClassID:
+ Typ = LR->getTypeID();
+ if( Typ == Type::FloatTyID )
+ return FPSingleRegType;
+ else if( Typ == Type::DoubleTyID )
+ return FPDoubleRegType;
+ else assert(0 && "Unknown type in FloatRegClass");
+
+ case IntCCRegClassID: return IntCCRegType;
+
+ case FloatCCRegClassID: return FloatCCRegType ;
+
+ default: assert( 0 && "Unknown reg class ID");
+ return 0;
+ }
+
+ }
+
+ int getRegType(const Value *const Val) const {
+
+ unsigned Typ;
+
+ switch( getRegClassIDOfValue(Val) ) {
+
+ case IntRegClassID: return IntRegType;
+
+ case FloatRegClassID:
+ Typ = (Val->getType())->getPrimitiveID();
+ if( Typ == Type::FloatTyID )
+ return FPSingleRegType;
+ else if( Typ == Type::DoubleTyID )
+ return FPDoubleRegType;
+ else assert(0 && "Unknown type in FloatRegClass");
+
+ case IntCCRegClassID: return IntCCRegType;
+
+ case FloatCCRegClassID: return FloatCCRegType ;
+
+ default: assert( 0 && "Unknown reg class ID");
+ return 0;
+ }
+
+ }
+
+
+ int getRegType(int reg) const {
+ if( reg < 32 )
+ return IntRegType;
+ else if ( reg < (32 + 32) )
+ return FPSingleRegType;
+ else if ( reg < (64 + 32) )
+ return FPDoubleRegType;
+ else if( reg < (64+32+4) )
+ return FloatCCRegType;
+ else if( reg < (64+32+4+2) )
+ return IntCCRegType;
+ else
+ assert(0 && "Invalid register number in getRegType");
+ }
+
+
+
+ // ***TODO: See this method is necessary
+
+ MachineInstr * cpValue2RegMI(Value * Val, const unsigned DestReg,
+ const int RegType) const;
+
+ const Value *getCallInstRetAddr(const MachineInstr *CallMI) const;
+ const unsigned getCallInstNumArgs(const MachineInstr *CallMI) const;
+
+
+ MachineInstr * cpCCR2IntMI(const unsigned IntReg) const;
+ MachineInstr * cpInt2CCRMI(const unsigned IntReg) const;
+
+
+
+ void moveInst2OrdVec(vector<MachineInstr *> &OrdVec, MachineInstr *UnordInst,
+ PhyRegAlloc &PRA ) const;
+
+ void OrderAddedInstrns( vector<MachineInstr *> &UnordVec,
+ vector<MachineInstr *> &OrdVec,
+ PhyRegAlloc &PRA) const;
+
+
+
+
- void setCallArgColor(LiveRange *const LR, const unsigned RegNo) const;
public:
- UltraSparcRegInfo(const UltraSparc *USI ) : UltraSparcInfo(USI),
- NumOfIntArgRegs(6),
- NumOfFloatArgRegs(6)
- {
+ UltraSparcRegInfo(const TargetMachine& tgt ) : MachineRegInfo(tgt),
+ UltraSparcInfo(& (const UltraSparc&) tgt),
+ NumOfIntArgRegs(6),
+ NumOfFloatArgRegs(32),
+ InvalidRegNum(1000),
+ SizeOfOperandOnStack(8)
+ {
MachineRegClassArr.push_back( new SparcIntRegClass(IntRegClassID) );
MachineRegClassArr.push_back( new SparcFloatRegClass(FloatRegClassID) );
+ MachineRegClassArr.push_back( new SparcIntCCRegClass(IntCCRegClassID) );
+ MachineRegClassArr.push_back( new SparcFloatCCRegClass(FloatCCRegClassID));
- assert( SparcFloatRegOrder::StartOfNonVolatileRegs == 6 &&
- "6 Float regs are used for float arg passing");
+ assert( SparcFloatRegOrder::StartOfNonVolatileRegs == 32 &&
+ "32 Float regs are used for float arg passing");
}
+ // ***** TODO Delete
+ ~UltraSparcRegInfo(void) { } // empty destructor
+
+
inline const UltraSparc & getUltraSparcInfo() const {
return *UltraSparcInfo;
}
- inline unsigned getRegClassIDOfValue (const Value *const Val) const {
+
+
+ inline unsigned getRegClassIDOfValue (const Value *const Val,
+ bool isCCReg = false) const {
+
Type::PrimitiveID ty = (Val->getType())->getPrimitiveID();
+
+ unsigned res;
- if( ty && ty <= Type::LongTyID || (ty == Type::PointerTyID) )
- return IntRegClassID; // sparc int reg (ty=0: void)
+ if( (ty && ty <= Type::LongTyID) || (ty == Type::LabelTyID) ||
+ (ty == Type::MethodTyID) || (ty == Type::PointerTyID) )
+ res = IntRegClassID; // sparc int reg (ty=0: void)
else if( ty <= Type::DoubleTyID)
- return FloatRegClassID; // sparc float reg class
+ res = FloatRegClassID; // sparc float reg class
else {
- cout << "TypeID: " << ty << endl;
+ cerr << "TypeID: " << ty << endl;
assert(0 && "Cannot resolve register class for type");
-
+ return 0;
}
+
+ if(isCCReg)
+ return res + 2; // corresponidng condition code regiser
+ else
+ return res;
}
-
- void colorArgs(const Method *const Meth, LiveRangeInfo& LRI) const;
- static void printReg(const LiveRange *const LR) ;
+ // returns the register tha contains always zero
+ // this is the unified register number
+ inline int getZeroRegNum() const { return SparcIntRegOrder::g0; }
- void colorCallArgs(vector<const Instruction *> & CallInstrList,
- LiveRangeInfo& LRI,
- AddedInstrMapType& AddedInstrMap ) const;
+ // returns the reg used for pushing the address when a method is called.
+ // This can be used for other purposes between calls
+ unsigned getCallAddressReg() const { return SparcIntRegOrder::o7; }
+
+
+ // and when we return from a method. It should be made sure that this
+ // register contains the return value when a return instruction is reached.
+ unsigned getReturnAddressReg() const { return SparcIntRegOrder::i7; }
+
+ void suggestRegs4MethodArgs(const Method *const Meth,
+ LiveRangeInfo& LRI) const;
+
+ void suggestRegs4CallArgs(const MachineInstr *const CallMI,
+ LiveRangeInfo& LRI, vector<RegClass *> RCL) const;
+
+ void suggestReg4RetValue(const MachineInstr *const RetMI,
+ LiveRangeInfo& LRI ) const;
+
+
+ void colorMethodArgs(const Method *const Meth, LiveRangeInfo& LRI,
+ AddedInstrns *const FirstAI) const;
+
+ void colorCallArgs(const MachineInstr *const CallMI, LiveRangeInfo& LRI,
+ AddedInstrns *const CallAI, PhyRegAlloc &PRA) const;
+
+ void colorRetValue(const MachineInstr *const RetI, LiveRangeInfo& LRI,
+ AddedInstrns *const RetAI) const;
+
+
+ // bool handleSpecialMInstr(const MachineInstr * MInst,
+ // LiveRangeInfo& LRI, vector<RegClass *> RCL) const;
+
+
+ static void printReg(const LiveRange *const LR) ;
// this method provides a unique number for each register
inline int getUnifiedRegNum(int RegClassID, int reg) const {
return reg;
else if ( RegClassID == FloatRegClassID && reg < 64)
return reg + 32; // we have 32 int regs
- else if( RegClassID == FloatCCREgClassID && reg < 4)
+ else if( RegClassID == FloatCCRegClassID && reg < 4)
return reg + 32 + 64; // 32 int, 64 float
- else
+ else if( RegClassID == IntCCRegClassID )
+ return 4+ 32 + 64; // only int cc reg
+ else if (reg==InvalidRegNum)
+ return InvalidRegNum;
+ else
assert(0 && "Invalid register class or reg number");
-
+ return 0;
}
// given the unified register number, this gives the name
inline const string getUnifiedRegName(int reg) const {
-
if( reg < 32 )
return SparcIntRegOrder::getRegName(reg);
else if ( reg < (64 + 32) )
return SparcFloatRegOrder::getRegName( reg - 32);
else if( reg < (64+32+4) )
- assert( 0 && "no float condition reg class yet");
- // return reg + 32 + 64;
+ return SparcFloatCCRegOrder::getRegName( reg -32 - 64);
+ else if( reg < (64+32+4+2) ) // two names: %xcc and %ccr
+ return SparcIntCCRegOrder::getRegName( reg -32 - 64 - 4);
+ else if (reg== InvalidRegNum) //****** TODO: Remove */
+ return "<*NoReg*>";
else
assert(0 && "Invalid register number");
+ return "";
}
+ inline unsigned int getRegNumInCallersWindow(int reg) {
+ if (reg == InvalidRegNum || reg >= 32)
+ return reg;
+ return SparcIntRegOrder::getRegNumInCallersWindow(reg);
+ }
+
+ inline bool mustBeRemappedInCallersWindow(int reg) {
+ return (reg != InvalidRegNum && reg < 32);
+ }
+
+ const Value * getCallInstRetVal(const MachineInstr *CallMI) const;
-};
+ MachineInstr * cpReg2RegMI(const unsigned SrcReg, const unsigned DestReg,
+ const int RegType) const;
+
+ MachineInstr * cpReg2MemMI(const unsigned SrcReg, const unsigned DestPtrReg,
+ const int Offset, const int RegType) const;
+
+ MachineInstr * cpMem2RegMI(const unsigned SrcPtrReg, const int Offset,
+ const unsigned DestReg, const int RegType) const;
+
+ MachineInstr* cpValue2Value(Value *Src, Value *Dest) const;
+
+
+ inline bool isRegVolatile(const int RegClassID, const int Reg) const {
+ return (MachineRegClassArr[RegClassID])->isRegVolatile(Reg);
+ }
+
+
+ inline unsigned getFramePointer() const {
+ return SparcIntRegOrder::i6;
+ }
+
+ inline unsigned getStackPointer() const {
+ return SparcIntRegOrder::o6;
+ }
+
+ inline int getInvalidRegNum() const {
+ return InvalidRegNum;
+ }
+ void insertCallerSavingCode(const MachineInstr *MInst,
+ const BasicBlock *BB, PhyRegAlloc &PRA ) const;
+};
/*numEntries*/ 0,
/* V[] */ {
/*Cycle G */
- /*Cycle E */
+ /*Ccle E */
/*Cycle C */
/*Cycle N1*/
/*Cycle N1*/
{ ADDCcc, true, true, 0 },
{ SUBC, true, true, 0 },
{ SUBCcc, true, true, 0 },
-//{ SAVE, true, true, 0 },
-//{ RESTORE, true, true, 0 },
//{ LDSTUB, true, true, 0 },
//{ SWAP, true, true, 0 },
//{ SWAPA, true, true, 0 },
{ RETURN, true, true, 0 },
//{ DONE, true, true, 0 },
//{ RETRY, true, true, 0 },
-//{ WR, true, true, 0 },
-//{ WRPR, true, true, 4 },
-//{ RD, true, true, 0 },
-//{ RDPR, true, true, 0 },
//{ TCC, true, true, 0 },
//{ SHUTDOWN, true, true, 0 },
// Special cases for breaking group *before*
// CURRENTLY NOT SUPPORTED!
{ CALL, false, false, 0 },
- { JMPL, false, false, 0 },
+ { JMPLCALL, false, false, 0 },
+ { JMPLRET, false, false, 0 },
// Special cases for breaking the group *after*
{ MULX, true, true, (4+34)/2 },
{ UDIVX, true, true, 68 },
//{ SDIVcc, true, true, 36 },
//{ UDIVcc, true, true, 37 },
-//{ WR, false, false, 4 },
-//{ WRPR, false, false, 4 },
+ { WRCCR, true, true, 4 },
+//{ WRPR, true, true, 4 },
+//{ RDCCR, true, true, 0 }, // no bubbles after, but see below
+//{ RDPR, true, true, 0 },
};
//
// JMPL counts as a load/store instruction for issue!
//
- { JMPL, LSIssueSlots.rid, 0, 1 },
+ { JMPLCALL, LSIssueSlots.rid, 0, 1 },
+ { JMPLRET, LSIssueSlots.rid, 0, 1 },
//
// Many instructions cannot issue for the next 2 cycles after an FCMP
//
// Some instructions are stalled in the GROUP stage if a CTI is in
- // the E or C stage
+ // the E or C stage. We model that with a fake resource CTIDelayCycle.
//
{ LDD, CTIDelayCycle.rid, 1, 1 },
//{ LDDA, CTIDelayCycle.rid, 1, 1 },
{ LDSW, LdReturn.rid, 2, -1 },
{ LDSW, LdReturn.rid, 3, 1 },
+ //
+ // RDPR from certain registers and RD from any register are not dispatchable
+ // until four clocks after they reach the head of the instr. buffer.
+ // Together with their single-issue requirement, this means all four issue
+ // slots are effectively blocked for those cycles, plus the issue cycle.
+ // This does not increase the latency of the instruction itself.
+ //
+ { RDCCR, AllIssueSlots.rid, 0, 5 },
+ { RDCCR, AllIssueSlots.rid, 0, 5 },
+ { RDCCR, AllIssueSlots.rid, 0, 5 },
+ { RDCCR, AllIssueSlots.rid, 0, 5 },
#undef EXPLICIT_BUBBLES_NEEDED
#ifdef EXPLICIT_BUBBLES_NEEDED
//{ RETRY, AllIssueSlots.rid, 2, 9-1 },
//{ RETRY, AllIssueSlots.rid, 2, 9-1 },
-#endif EXPLICIT_BUBBLES_NEEDED
+#endif /*EXPLICIT_BUBBLES_NEEDED */
};
class UltraSparcSchedInfo: public MachineSchedInfo {
public:
- /*ctor*/ UltraSparcSchedInfo (const MachineInstrInfo* mii);
+ /*ctor*/ UltraSparcSchedInfo (const TargetMachine& tgt);
/*dtor*/ virtual ~UltraSparcSchedInfo () {}
protected:
virtual void initializeResources ();
};
+//---------------------------------------------------------------------------
+// class UltraSparcFrameInfo
+//
+// Purpose:
+// Interface to stack frame layout info for the UltraSPARC.
+//---------------------------------------------------------------------------
+
+class UltraSparcFrameInfo: public MachineFrameInfo {
+public:
+ /*ctor*/ UltraSparcFrameInfo(const TargetMachine& tgt) : MachineFrameInfo(tgt) {}
+
+public:
+ int getStackFrameSizeAlignment () const { return StackFrameSizeAlignment;}
+ int getMinStackFrameSize () const { return MinStackFrameSize; }
+ int getNumFixedOutgoingArgs () const { return NumFixedOutgoingArgs; }
+ int getSizeOfEachArgOnStack () const { return SizeOfEachArgOnStack; }
+ bool argsOnStackHaveFixedSize () const { return true; }
+
+ //
+ // These methods compute offsets using the frame contents for a
+ // particular method. The frame contents are obtained from the
+ // MachineCodeInfoForMethod object for the given method.
+ //
+ int getFirstIncomingArgOffset (MachineCodeForMethod& mcInfo,
+ bool& pos) const
+ {
+ pos = true; // arguments area grows upwards
+ return FirstIncomingArgOffsetFromFP;
+ }
+ int getFirstOutgoingArgOffset (MachineCodeForMethod& mcInfo,
+ bool& pos) const
+ {
+ pos = true; // arguments area grows upwards
+ return FirstOutgoingArgOffsetFromSP;
+ }
+ int getFirstOptionalOutgoingArgOffset(MachineCodeForMethod& mcInfo,
+ bool& pos)const
+ {
+ pos = true; // arguments area grows upwards
+ return FirstOptionalOutgoingArgOffsetFromSP;
+ }
+
+ int getFirstAutomaticVarOffset (MachineCodeForMethod& mcInfo,
+ bool& pos) const;
+ int getRegSpillAreaOffset (MachineCodeForMethod& mcInfo,
+ bool& pos) const;
+ int getTmpAreaOffset (MachineCodeForMethod& mcInfo,
+ bool& pos) const;
+ int getDynamicAreaOffset (MachineCodeForMethod& mcInfo,
+ bool& pos) const;
+
+ //
+ // These methods specify the base register used for each stack area
+ // (generally FP or SP)
+ //
+ virtual int getIncomingArgBaseRegNum() const {
+ return (int) target.getRegInfo().getFramePointer();
+ }
+ virtual int getOutgoingArgBaseRegNum() const {
+ return (int) target.getRegInfo().getStackPointer();
+ }
+ virtual int getOptionalOutgoingArgBaseRegNum() const {
+ return (int) target.getRegInfo().getStackPointer();
+ }
+ virtual int getAutomaticVarBaseRegNum() const {
+ return (int) target.getRegInfo().getFramePointer();
+ }
+ virtual int getRegSpillAreaBaseRegNum() const {
+ return (int) target.getRegInfo().getFramePointer();
+ }
+ virtual int getDynamicAreaBaseRegNum() const {
+ return (int) target.getRegInfo().getStackPointer();
+ }
+
+private:
+ // All stack addresses must be offset by 0x7ff (2047) on Sparc V9.
+ static const int OFFSET = (int) 0x7ff;
+ static const int StackFrameSizeAlignment = 16;
+ static const int MinStackFrameSize = 176;
+ static const int NumFixedOutgoingArgs = 6;
+ static const int SizeOfEachArgOnStack = 8;
+ static const int StaticAreaOffsetFromFP = 0 + OFFSET;
+ static const int FirstIncomingArgOffsetFromFP = 128 + OFFSET;
+ static const int FirstOptionalIncomingArgOffsetFromFP = 176 + OFFSET;
+ static const int FirstOutgoingArgOffsetFromSP = 128 + OFFSET;
+ static const int FirstOptionalOutgoingArgOffsetFromSP = 176 + OFFSET;
+};
+
+
+//---------------------------------------------------------------------------
+// class UltraSparcCacheInfo
+//
+// Purpose:
+// Interface to cache parameters for the UltraSPARC.
+// Just use defaults for now.
+//---------------------------------------------------------------------------
+
+class UltraSparcCacheInfo: public MachineCacheInfo {
+public:
+ /*ctor*/ UltraSparcCacheInfo (const TargetMachine& target) :
+ MachineCacheInfo(target) {}
+};
+
+
//---------------------------------------------------------------------------
// class UltraSparcMachine
//
// Primary interface to machine description for the UltraSPARC.
// Primarily just initializes machine-dependent parameters in
// class TargetMachine, and creates machine-dependent subclasses
-// for classes such as MachineInstrInfo.
+// for classes such as InstrInfo, SchedInfo and RegInfo.
//---------------------------------------------------------------------------
class UltraSparc : public TargetMachine {
- UltraSparcInstrInfo InstInfo;
- UltraSparcSchedInfo InstSchedulingInfo;
+private:
+ UltraSparcInstrInfo instrInfo;
+ UltraSparcSchedInfo schedInfo;
+ UltraSparcRegInfo regInfo;
+ UltraSparcFrameInfo frameInfo;
+ UltraSparcCacheInfo cacheInfo;
public:
UltraSparc();
virtual ~UltraSparc() {}
-
- virtual const MachineInstrInfo& getInstrInfo() const { return InstInfo; }
-
+
+ virtual const MachineInstrInfo &getInstrInfo() const { return instrInfo; }
+ virtual const MachineSchedInfo &getSchedInfo() const { return schedInfo; }
+ virtual const MachineRegInfo &getRegInfo() const { return regInfo; }
+ virtual const MachineFrameInfo &getFrameInfo() const { return frameInfo; }
+ virtual const MachineCacheInfo &getCacheInfo() const { return cacheInfo; }
+
// compileMethod - For the sparc, we do instruction selection, followed by
// delay slot scheduling, then register allocation.
//
virtual bool compileMethod(Method *M);
+
+ //
+ // emitAssembly - Output assembly language code (a .s file) for the specified
+ // module. The specified module must have been compiled before this may be
+ // used.
+ //
+ virtual void emitAssembly(const Module *M, ostream &OutStr) const;
};
projects / oota-llvm.git / blobdiff