-//===-- SparcV9RegInfo.cpp - SparcV9 Target Register Information --------------===//
-//
+//===-- SparcV9RegInfo.cpp - SparcV9 Target Register Information ----------===//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
-// This file contains implementation of SparcV9 specific helper methods
+// This file contains implementations of SparcV9 specific helper methods
// used for register allocation.
//
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/MachineFunctionInfo.h"
-#include "llvm/CodeGen/InstrSelection.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineCodeForInstruction.h"
+#include "MachineFunctionInfo.h"
+#include "MachineCodeForInstruction.h"
#include "MachineInstrAnnot.h"
#include "RegAlloc/LiveRangeInfo.h"
#include "RegAlloc/LiveRange.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Function.h"
-#include "llvm/iTerminators.h"
-#include "llvm/iOther.h"
+#include "llvm/Instructions.h"
#include "SparcV9Internals.h"
#include "SparcV9RegClassInfo.h"
#include "SparcV9RegInfo.h"
+#include "SparcV9FrameInfo.h"
#include "SparcV9TargetMachine.h"
+#include "SparcV9TmpInstr.h"
+#include <iostream>
namespace llvm {
};
SparcV9RegInfo::SparcV9RegInfo(const SparcV9TargetMachine &tgt)
- : TargetRegInfo(tgt), NumOfIntArgRegs(6), NumOfFloatArgRegs(32)
+ : target (tgt), NumOfIntArgRegs (6), NumOfFloatArgRegs (32)
{
MachineRegClassArr.push_back(new SparcV9IntRegClass(IntRegClassID));
MachineRegClassArr.push_back(new SparcV9FloatRegClass(FloatRegClassID));
MachineRegClassArr.push_back(new SparcV9IntCCRegClass(IntCCRegClassID));
MachineRegClassArr.push_back(new SparcV9FloatCCRegClass(FloatCCRegClassID));
MachineRegClassArr.push_back(new SparcV9SpecialRegClass(SpecialRegClassID));
-
- assert(SparcV9FloatRegClass::StartOfNonVolatileRegs == 32 &&
+
+ assert(SparcV9FloatRegClass::StartOfNonVolatileRegs == 32 &&
"32 Float regs are used for float arg passing");
}
}
// Returns the register containing the return address.
-// It should be made sure that this register contains the return
+// It should be made sure that this register contains the return
// value when a return instruction is reached.
//
unsigned SparcV9RegInfo::getReturnAddressReg() const {
static const char * const IntRegNames[] = {
"o0", "o1", "o2", "o3", "o4", "o5", "o7",
"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
- "i0", "i1", "i2", "i3", "i4", "i5",
+ "i0", "i1", "i2", "i3", "i4", "i5",
"i6", "i7",
- "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
+ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
"o6"
-};
+};
const char * const SparcV9IntRegClass::getRegName(unsigned reg) const {
assert(reg < NumOfAllRegs);
return IntRegNames[reg];
}
-static const char * const FloatRegNames[] = {
- "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",
+static const char * const FloatRegNames[] = {
+ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",
"f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19",
"f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29",
"f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
return FloatRegNames[reg];
}
-
-static const char * const IntCCRegNames[] = {
+static const char * const IntCCRegNames[] = {
"xcc", "icc", "ccr"
};
return IntCCRegNames[reg];
}
-static const char * const FloatCCRegNames[] = {
+static const char * const FloatCCRegNames[] = {
"fcc0", "fcc1", "fcc2", "fcc3"
};
const char * const SparcV9FloatCCRegClass::getRegName(unsigned reg) const {
- assert (reg < 5);
+ assert (reg < 4);
return FloatCCRegNames[reg];
}
-static const char * const SpecialRegNames[] = {
+static const char * const SpecialRegNames[] = {
"fsr"
};
// Get the register number for the specified argument #argNo,
-//
+//
// Return value:
-// getInvalidRegNum(), if there is no int register available for the arg.
+// getInvalidRegNum(), if there is no int register available for the arg.
// regNum, otherwise (this is NOT the unified reg. num).
// regClassId is set to the register class ID.
-//
+//
int
SparcV9RegInfo::regNumForIntArg(bool inCallee, bool isVarArgsCall,
unsigned argNo, unsigned& regClassId) const
// Get the register number for the specified FP argument #argNo,
// Use INT regs for FP args if this is a varargs call.
-//
+//
// Return value:
-// getInvalidRegNum(), if there is no int register available for the arg.
+// getInvalidRegNum(), if there is no int register available for the arg.
// regNum, otherwise (this is NOT the unified reg. num).
// regClassId is set to the register class ID.
-//
+//
int
SparcV9RegInfo::regNumForFPArg(unsigned regType,
bool inCallee, bool isVarArgsCall,
getInvalidRegNum() : SparcV9FloatRegClass::f0 + (argNo * 2);
else
assert(0 && "Illegal FP register type");
- return 0;
+ return 0;
}
}
//---------------------------------------------------------------------------
// The following 4 methods are used to find the RegType (SparcV9Internals.h)
-// of a LiveRange, a Value, and for a given register unified reg number.
+// of a V9LiveRange, a Value, and for a given register unified reg number.
//
int SparcV9RegInfo::getRegTypeForClassAndType(unsigned regClassID,
const Type* type) const
{
switch (regClassID) {
- case IntRegClassID: return IntRegType;
+ case IntRegClassID: return IntRegType;
case FloatRegClassID:
if (type == Type::FloatTy) return FPSingleRegType;
else if (type == Type::DoubleTy) return FPDoubleRegType;
assert(0 && "Unknown type in FloatRegClass"); return 0;
- case IntCCRegClassID: return IntCCRegType;
- case FloatCCRegClassID: return FloatCCRegType;
- case SpecialRegClassID: return SpecialRegType;
+ case IntCCRegClassID: return IntCCRegType;
+ case FloatCCRegClassID: return FloatCCRegType;
+ case SpecialRegClassID: return SpecialRegType;
default: assert( 0 && "Unknown reg class ID"); return 0;
}
}
return getRegTypeForClassAndType(getRegClassIDOfType(type), type);
}
-int SparcV9RegInfo::getRegTypeForLR(const LiveRange *LR) const
+int SparcV9RegInfo::getRegTypeForLR(const V9LiveRange *LR) const
{
return getRegTypeForClassAndType(LR->getRegClassID(), LR->getType());
}
int SparcV9RegInfo::getRegType(int unifiedRegNum) const
{
- if (unifiedRegNum < 32)
+ if (unifiedRegNum < 32)
return IntRegType;
else if (unifiedRegNum < (32 + 32))
return FPSingleRegType;
else if (unifiedRegNum < (64 + 32))
return FPDoubleRegType;
- else if (unifiedRegNum < (64+32+4))
+ else if (unifiedRegNum < (64+32+3))
+ return IntCCRegType;
+ else if (unifiedRegNum < (64+32+3+4))
return FloatCCRegType;
- else if (unifiedRegNum < (64+32+4+2))
- return IntCCRegType;
- else
+ else if (unifiedRegNum < (64+32+3+4+1))
+ return SpecialRegType;
+ else
assert(0 && "Invalid unified register number in getRegType");
return 0;
}
//
unsigned SparcV9RegInfo::getRegClassIDOfType(const Type *type,
bool isCCReg) const {
- Type::PrimitiveID ty = type->getPrimitiveID();
+ Type::TypeID ty = type->getTypeID();
unsigned res;
-
+
// FIXME: Comparing types like this isn't very safe...
if ((ty && ty <= Type::LongTyID) || (ty == Type::LabelTyID) ||
(ty == Type::FunctionTyID) || (ty == Type::PointerTyID) )
res = IntRegClassID; // sparc int reg (ty=0: void)
else if (ty <= Type::DoubleTyID)
res = FloatRegClassID; // sparc float reg class
- else {
+ else {
//std::cerr << "TypeID: " << ty << "\n";
assert(0 && "Cannot resolve register class for type");
return 0;
}
-
+
if (isCCReg)
- return res + 2; // corresponding condition code register
- else
+ return res + 2; // corresponding condition code register
+ else
return res;
}
case FPDoubleRegType: return FloatRegClassID;
case IntCCRegType: return IntCCRegClassID;
case FloatCCRegType: return FloatCCRegClassID;
+ case SpecialRegType: return SpecialRegClassID;
default:
assert(0 && "Invalid register type in getRegClassIDOfRegType");
return 0;
// Suggests a register for the ret address in the RET machine instruction.
// We always suggest %i7 by convention.
//---------------------------------------------------------------------------
-void SparcV9RegInfo::suggestReg4RetAddr(MachineInstr *RetMI,
- LiveRangeInfo& LRI) const {
+void SparcV9RegInfo::suggestReg4RetAddr(MachineInstr *RetMI,
+ LiveRangeInfo& LRI) const {
+
+ assert(target.getInstrInfo()->isReturn(RetMI->getOpcode()));
- assert(target.getInstrInfo().isReturn(RetMI->getOpcode()));
-
// return address is always mapped to i7 so set it immediately
RetMI->SetRegForOperand(0, getUnifiedRegNum(IntRegClassID,
SparcV9IntRegClass::i7));
-
- // Possible Optimization:
+
+ // Possible Optimization:
// Instead of setting the color, we can suggest one. In that case,
// we have to test later whether it received the suggested color.
// In that case, a LR has to be created at the start of method.
// MachineOperand & MO = RetMI->getOperand(0);
// const Value *RetAddrVal = MO.getVRegValue();
// assert( RetAddrVal && "LR for ret address must be created at start");
- // LiveRange * RetAddrLR = LRI.getLiveRangeForValue( RetAddrVal);
- // RetAddrLR->setSuggestedColor(getUnifiedRegNum( IntRegClassID,
+ // V9LiveRange * RetAddrLR = LRI.getLiveRangeForValue( RetAddrVal);
+ // RetAddrLR->setSuggestedColor(getUnifiedRegNum( IntRegClassID,
// SparcV9IntRegOrdr::i7) );
}
SparcV9RegInfo::suggestReg4CallAddr(MachineInstr * CallMI,
LiveRangeInfo& LRI) const
{
- CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
+ CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
const Value *RetAddrVal = argDesc->getReturnAddrReg();
assert(RetAddrVal && "INTERNAL ERROR: Return address value is required");
// A LR must already exist for the return address.
- LiveRange *RetAddrLR = LRI.getLiveRangeForValue(RetAddrVal);
+ V9LiveRange *RetAddrLR = LRI.getLiveRangeForValue(RetAddrVal);
assert(RetAddrLR && "INTERNAL ERROR: No LR for return address of call!");
unsigned RegClassID = RetAddrLR->getRegClassID();
//---------------------------------------------------------------------------
-// This method will suggest colors to incoming args to a method.
-// According to the SparcV9 ABI, the first 6 incoming args are in
+// This method will suggest colors to incoming args to a method.
+// According to the SparcV9 ABI, the first 6 incoming args are in
// %i0 - %i5 (if they are integer) OR in %f0 - %f31 (if they are float).
// If the arg is passed on stack due to the lack of regs, NOTHING will be
// done - it will be colored (or spilled) as a normal live range.
//---------------------------------------------------------------------------
-void SparcV9RegInfo::suggestRegs4MethodArgs(const Function *Meth,
- LiveRangeInfo& LRI) const
+void SparcV9RegInfo::suggestRegs4MethodArgs(const Function *Meth,
+ LiveRangeInfo& LRI) const
{
// Check if this is a varArgs function. needed for choosing regs.
bool isVarArgs = isVarArgsFunction(Meth->getType());
-
+
// Count the arguments, *ignoring* whether they are int or FP args.
// Use this common arg numbering to pick the right int or fp register.
unsigned argNo=0;
- for(Function::const_aiterator I = Meth->abegin(), E = Meth->aend();
+ for(Function::const_arg_iterator I = Meth->arg_begin(), E = Meth->arg_end();
I != E; ++I, ++argNo) {
- LiveRange *LR = LRI.getLiveRangeForValue(I);
+ V9LiveRange *LR = LRI.getLiveRangeForValue(I);
assert(LR && "No live range found for method arg");
-
+
unsigned regType = getRegTypeForLR(LR);
unsigned regClassIDOfArgReg = BadRegClass; // for chosen reg (unused)
-
+
int regNum = (regType == IntRegType)
? regNumForIntArg(/*inCallee*/ true, isVarArgs, argNo, regClassIDOfArgReg)
: regNumForFPArg(regType, /*inCallee*/ true, isVarArgs, argNo,
- regClassIDOfArgReg);
-
+ regClassIDOfArgReg);
+
if (regNum != getInvalidRegNum())
LR->setSuggestedColor(regNum);
}
// the correct hardware registers if they did not receive the correct
// (suggested) color through graph coloring.
//---------------------------------------------------------------------------
-void SparcV9RegInfo::colorMethodArgs(const Function *Meth,
+void SparcV9RegInfo::colorMethodArgs(const Function *Meth,
LiveRangeInfo &LRI,
std::vector<MachineInstr*>& InstrnsBefore,
std::vector<MachineInstr*>& InstrnsAfter) const {
// for each argument
// for each argument. count INT and FP arguments separately.
unsigned argNo=0, intArgNo=0, fpArgNo=0;
- for(Function::const_aiterator I = Meth->abegin(), E = Meth->aend();
+ for(Function::const_arg_iterator I = Meth->arg_begin(), E = Meth->arg_end();
I != E; ++I, ++argNo) {
// get the LR of arg
- LiveRange *LR = LRI.getLiveRangeForValue(I);
+ V9LiveRange *LR = LRI.getLiveRangeForValue(I);
assert( LR && "No live range found for method arg");
unsigned regType = getRegTypeForLR(LR);
unsigned RegClassID = LR->getRegClassID();
-
+
// Find whether this argument is coming in a register (if not, on stack)
// Also find the correct register the argument must use (UniArgReg)
//
bool isArgInReg = false;
unsigned UniArgReg = getInvalidRegNum(); // reg that LR MUST be colored with
unsigned regClassIDOfArgReg = BadRegClass; // reg class of chosen reg
-
+
int regNum = (regType == IntRegType)
? regNumForIntArg(/*inCallee*/ true, isVarArgs,
argNo, regClassIDOfArgReg)
: regNumForFPArg(regType, /*inCallee*/ true, isVarArgs,
argNo, regClassIDOfArgReg);
-
+
if(regNum != getInvalidRegNum()) {
isArgInReg = true;
UniArgReg = getUnifiedRegNum( regClassIDOfArgReg, regNum);
}
-
+
if( ! LR->isMarkedForSpill() ) { // if this arg received a register
unsigned UniLRReg = getUnifiedRegNum( RegClassID, LR->getColor() );
// if LR received the correct color, nothing to do
//
if( UniLRReg == UniArgReg )
- continue;
+ continue;
- // We are here because the LR did not receive the suggested
+ // We are here because the LR did not receive the suggested
// but LR received another register.
- // Now we have to copy the %i reg (or stack pos of arg)
+ // Now we have to copy the %i reg (or stack pos of arg)
// to the register the LR was colored with.
-
+
// if the arg is coming in UniArgReg register, it MUST go into
// the UniLRReg register
//
if( isArgInReg ) {
- if( regClassIDOfArgReg != RegClassID ) {
- assert(0 && "This could should work but it is not tested yet");
-
- // It is a variable argument call: the float reg must go in a %o reg.
- // We have to move an int reg to a float reg via memory.
- //
+ if( regClassIDOfArgReg != RegClassID ) {
+ // NOTE: This code has not been well-tested.
+
+ // It is a variable argument call: the float reg must go in a %o reg.
+ // We have to move an int reg to a float reg via memory.
+ //
assert(isVarArgs &&
- RegClassID == FloatRegClassID &&
+ RegClassID == FloatRegClassID &&
regClassIDOfArgReg == IntRegClassID &&
"This should only be an Int register for an FP argument");
-
- int TmpOff = MachineFunction::get(Meth).getInfo()->pushTempValue(
+
+ int TmpOff = MachineFunction::get(Meth).getInfo<SparcV9FunctionInfo>()->pushTempValue(
getSpilledRegSize(regType));
- cpReg2MemMI(InstrnsBefore,
+ cpReg2MemMI(InstrnsBefore,
UniArgReg, getFramePointer(), TmpOff, IntRegType);
-
- cpMem2RegMI(InstrnsBefore,
+
+ cpMem2RegMI(InstrnsBefore,
getFramePointer(), TmpOff, UniLRReg, regType);
- }
- else {
- cpReg2RegMI(InstrnsBefore, UniArgReg, UniLRReg, regType);
- }
+ }
+ else {
+ cpReg2RegMI(InstrnsBefore, UniArgReg, UniLRReg, regType);
+ }
}
else {
- // Now the arg is coming on stack. Since the LR received a register,
- // we just have to load the arg on stack into that register
- //
- const TargetFrameInfo& frameInfo = target.getFrameInfo();
- int offsetFromFP =
+ // Now the arg is coming on stack. Since the LR received a register,
+ // we just have to load the arg on stack into that register
+ //
+ const TargetFrameInfo& frameInfo = *target.getFrameInfo();
+ int offsetFromFP =
frameInfo.getIncomingArgOffset(MachineFunction::get(Meth),
argNo);
// a full double-word so the offset does not need to be adjusted.
if (regType == FPSingleRegType) {
unsigned argSize = target.getTargetData().getTypeSize(LR->getType());
- unsigned slotSize = frameInfo.getSizeOfEachArgOnStack();
+ unsigned slotSize = SparcV9FrameInfo::SizeOfEachArgOnStack;
assert(argSize <= slotSize && "Insufficient slot size!");
offsetFromFP += slotSize - argSize;
}
- cpMem2RegMI(InstrnsBefore,
+ cpMem2RegMI(InstrnsBefore,
getFramePointer(), offsetFromFP, UniLRReg, regType);
}
-
+
} // if LR received a color
- else {
+ else {
// Now, the LR did not receive a color. But it has a stack offset for
// spilling.
// that on to the stack pos of LR
if( isArgInReg ) {
-
- if( regClassIDOfArgReg != RegClassID ) {
+
+ if( regClassIDOfArgReg != RegClassID ) {
assert(0 &&
"FP arguments to a varargs function should be explicitly "
"copied to/from int registers by instruction selection!");
-
- // It must be a float arg for a variable argument call, which
+
+ // It must be a float arg for a variable argument call, which
// must come in a %o reg. Move the int reg to the stack.
- //
+ //
assert(isVarArgs && regClassIDOfArgReg == IntRegClassID &&
"This should only be an Int register for an FP argument");
-
+
cpReg2MemMI(InstrnsBefore, UniArgReg,
getFramePointer(), LR->getSpillOffFromFP(), IntRegType);
}
else {
- // Now the arg is coming on stack. Since the LR did NOT
- // received a register as well, it is allocated a stack position. We
- // can simply change the stack position of the LR. We can do this,
- // since this method is called before any other method that makes
- // uses of the stack pos of the LR (e.g., updateMachineInstr)
- //
- const TargetFrameInfo& frameInfo = target.getFrameInfo();
- int offsetFromFP =
+ // Now the arg is coming on stack. Since the LR did NOT
+ // received a register as well, it is allocated a stack position. We
+ // can simply change the stack position of the LR. We can do this,
+ // since this method is called before any other method that makes
+ // uses of the stack pos of the LR (e.g., updateMachineInstr)
+ //
+ const TargetFrameInfo& frameInfo = *target.getFrameInfo();
+ int offsetFromFP =
frameInfo.getIncomingArgOffset(MachineFunction::get(Meth),
argNo);
// a full double-word so the offset does not need to be adjusted.
if (regType == FPSingleRegType) {
unsigned argSize = target.getTargetData().getTypeSize(LR->getType());
- unsigned slotSize = frameInfo.getSizeOfEachArgOnStack();
+ unsigned slotSize = SparcV9FrameInfo::SizeOfEachArgOnStack;
assert(argSize <= slotSize && "Insufficient slot size!");
offsetFromFP += slotSize - argSize;
}
-
- LR->modifySpillOffFromFP( offsetFromFP );
+
+ LR->modifySpillOffFromFP( offsetFromFP );
}
}
// This method is called before graph coloring to suggest colors to the
// outgoing call args and the return value of the call.
//---------------------------------------------------------------------------
-void SparcV9RegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
- LiveRangeInfo& LRI) const {
- assert ( (target.getInstrInfo()).isCall(CallMI->getOpcode()) );
+void SparcV9RegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
+ LiveRangeInfo& LRI) const {
+ assert ( (target.getInstrInfo())->isCall(CallMI->getOpcode()) );
+
+ CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
- CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
-
suggestReg4CallAddr(CallMI, LRI);
// First color the return value of the call instruction, if any.
// The return value will be in %o0 if the value is an integer type,
// or in %f0 if the value is a float type.
- //
+ //
if (const Value *RetVal = argDesc->getReturnValue()) {
- LiveRange *RetValLR = LRI.getLiveRangeForValue(RetVal);
+ V9LiveRange *RetValLR = LRI.getLiveRangeForValue(RetVal);
assert(RetValLR && "No LR for return Value of call!");
unsigned RegClassID = RetValLR->getRegClassID();
// now suggest a register depending on the register class of ret arg
- if( RegClassID == IntRegClassID )
+ if( RegClassID == IntRegClassID )
RetValLR->setSuggestedColor(SparcV9IntRegClass::o0);
- else if (RegClassID == FloatRegClassID )
+ else if (RegClassID == FloatRegClassID )
RetValLR->setSuggestedColor(SparcV9FloatRegClass::f0 );
else assert( 0 && "Unknown reg class for return value of call\n");
}
// Now, go thru call args - implicit operands of the call MI
unsigned NumOfCallArgs = argDesc->getNumArgs();
-
+
for(unsigned argNo=0, i=0, intArgNo=0, fpArgNo=0;
- i < NumOfCallArgs; ++i, ++argNo) {
+ i < NumOfCallArgs; ++i, ++argNo) {
const Value *CallArg = argDesc->getArgInfo(i).getArgVal();
-
+
// get the LR of call operand (parameter)
- LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
+ V9LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
if (!LR)
continue; // no live ranges for constants and labels
? regNumForIntArg(/*inCallee*/ false, /*isVarArgs*/ false,
argNo, regClassIDOfArgReg)
: regNumForFPArg(regType, /*inCallee*/ false, /*isVarArgs*/ false,
- argNo, regClassIDOfArgReg);
-
+ argNo, regClassIDOfArgReg);
+
// If a register could be allocated, use it.
// If not, do NOTHING as this will be colored as a normal value.
if(regNum != getInvalidRegNum())
// this method is called for an LLVM return instruction to identify which
// values will be returned from this method and to suggest colors.
//---------------------------------------------------------------------------
-void SparcV9RegInfo::suggestReg4RetValue(MachineInstr *RetMI,
+void SparcV9RegInfo::suggestReg4RetValue(MachineInstr *RetMI,
LiveRangeInfo& LRI) const {
- assert( (target.getInstrInfo()).isReturn( RetMI->getOpcode() ) );
+ assert( target.getInstrInfo()->isReturn( RetMI->getOpcode() ) );
suggestReg4RetAddr(RetMI, LRI);
Value* tmpI = RetMI->getOperand(0).getVRegValue();
ReturnInst* retI=cast<ReturnInst>(cast<TmpInstruction>(tmpI)->getOperand(0));
if (const Value *RetVal = retI->getReturnValue())
- if (LiveRange *const LR = LRI.getLiveRangeForValue(RetVal))
+ if (V9LiveRange *const LR = LRI.getLiveRangeForValue(RetVal))
LR->setSuggestedColor(LR->getRegClassID() == IntRegClassID
? (unsigned) SparcV9IntRegClass::i0
: (unsigned) SparcV9FloatRegClass::f0);
unsigned SrcReg,
unsigned DestReg,
int RegType) const {
- assert( ((int)SrcReg != getInvalidRegNum()) &&
+ assert( ((int)SrcReg != getInvalidRegNum()) &&
((int)DestReg != getInvalidRegNum()) &&
- "Invalid Register");
-
+ "Invalid Register");
+
MachineInstr * MI = NULL;
-
+
switch( RegType ) {
-
+
case IntCCRegType:
if (getRegType(DestReg) == IntRegType) {
// copy intCC reg to int reg
MachineOperand::Def));
}
break;
-
- case FloatCCRegType:
+
+ case FloatCCRegType:
assert(0 && "Cannot copy FPCC register to any other register");
break;
-
+
case IntRegType:
MI = BuildMI(V9::ADDr, 3).addMReg(SrcReg).addMReg(getZeroRegNum())
.addMReg(DestReg, MachineOperand::Def);
break;
-
+
case FPSingleRegType:
MI = BuildMI(V9::FMOVS, 2).addMReg(SrcReg)
.addMReg(DestReg, MachineOperand::Def);
assert(0 && "Unknown RegType");
break;
}
-
+
if (MI)
mvec.push_back(MI);
}
-//---------------------------------------------------------------------------
-// Copy from a register to memory (i.e., Store). Register number must
-// be the unified register number
-//---------------------------------------------------------------------------
-
-
-void
-SparcV9RegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec,
- unsigned SrcReg,
- unsigned PtrReg,
- int Offset, int RegType,
- int scratchReg) const {
- MachineInstr * MI = NULL;
- int OffReg = -1;
-
- // If the Offset will not fit in the signed-immediate field, find an
- // unused register to hold the offset value. This takes advantage of
- // the fact that all the opcodes used below have the same size immed. field.
- // Use the register allocator, PRA, to find an unused reg. at this MI.
- //
- if (RegType != IntCCRegType) // does not use offset below
- if (! target.getInstrInfo().constantFitsInImmedField(V9::LDXi, Offset)) {
-#ifdef CAN_FIND_FREE_REGISTER_TRANSPARENTLY
- RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType));
- OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
-#else
- // Default to using register g4 for holding large offsets
- OffReg = getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
- SparcV9IntRegClass::g4);
-#endif
- assert(OffReg >= 0 && "FIXME: cpReg2MemMI cannot find an unused reg.");
- mvec.push_back(BuildMI(V9::SETSW, 2).addZImm(Offset).addReg(OffReg));
- }
+/// cpReg2MemMI - Generate SparcV9 MachineInstrs to store a register
+/// (SrcReg) to memory, at [PtrReg + Offset]. Register numbers must be the
+/// unified register numbers. RegType must be the SparcV9 register type
+/// of SrcReg. When SrcReg is %ccr, scratchReg must be the
+/// number of a free integer register. The newly-generated MachineInstrs
+/// are appended to mvec.
+///
+void SparcV9RegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec,
+ unsigned SrcReg, unsigned PtrReg, int Offset,
+ int RegType, int scratchReg) const {
+ unsigned OffReg = SparcV9::g4; // Use register g4 for holding large offsets
+ bool useImmediateOffset = true;
+
+ // If the Offset will not fit in the signed-immediate field, we put it in
+ // register g4. This takes advantage of the fact that all the opcodes
+ // used below have the same size immed. field.
+ if (RegType != IntCCRegType
+ && !target.getInstrInfo()->constantFitsInImmedField(V9::LDXi, Offset)) {
+ // Put the offset into a register. We could do this in fewer steps,
+ // in some cases (see CreateSETSWConst()) but we're being lazy.
+ MachineInstr *MI = BuildMI(V9::SETHI, 2).addZImm(Offset).addMReg(OffReg,
+ MachineOperand::Def);
+ MI->getOperand(0).markHi32();
+ mvec.push_back(MI);
+ MI = BuildMI(V9::ORi,3).addMReg(OffReg).addZImm(Offset).addMReg(OffReg,
+ MachineOperand::Def);
+ MI->getOperand(1).markLo32();
+ mvec.push_back(MI);
+ MI = BuildMI(V9::SRAi5,3).addMReg(OffReg).addZImm(0).addMReg(OffReg,
+ MachineOperand::Def);
+ mvec.push_back(MI);
+ useImmediateOffset = false;
+ }
+ MachineInstr *MI = 0;
switch (RegType) {
case IntRegType:
- if (target.getInstrInfo().constantFitsInImmedField(V9::STXi, Offset))
+ if (useImmediateOffset)
MI = BuildMI(V9::STXi,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset);
else
MI = BuildMI(V9::STXr,3).addMReg(SrcReg).addMReg(PtrReg).addMReg(OffReg);
break;
case FPSingleRegType:
- if (target.getInstrInfo().constantFitsInImmedField(V9::STFi, Offset))
+ if (useImmediateOffset)
MI = BuildMI(V9::STFi, 3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset);
else
MI = BuildMI(V9::STFr, 3).addMReg(SrcReg).addMReg(PtrReg).addMReg(OffReg);
break;
case FPDoubleRegType:
- if (target.getInstrInfo().constantFitsInImmedField(V9::STDFi, Offset))
+ if (useImmediateOffset)
MI = BuildMI(V9::STDFi,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset);
else
MI = BuildMI(V9::STDFr,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(OffReg);
break;
case IntCCRegType:
- assert(scratchReg >= 0 && "Need scratch reg to store %ccr to memory");
- assert(getRegType(scratchReg) ==IntRegType && "Invalid scratch reg");
- MI = (BuildMI(V9::RDCCR, 2)
- .addMReg(getUnifiedRegNum(SparcV9RegInfo::IntCCRegClassID,
- SparcV9IntCCRegClass::ccr))
- .addMReg(scratchReg, MachineOperand::Def));
+ assert(scratchReg >= 0 && getRegType(scratchReg) == IntRegType
+ && "Need a scratch reg of integer type to load or store %ccr");
+ MI = BuildMI(V9::RDCCR, 2).addMReg(SparcV9::ccr)
+ .addMReg(scratchReg, MachineOperand::Def);
mvec.push_back(MI);
-
cpReg2MemMI(mvec, scratchReg, PtrReg, Offset, IntRegType);
return;
+ case SpecialRegType: // used only for %fsr itself.
case FloatCCRegType: {
- unsigned fsrReg = getUnifiedRegNum(SparcV9RegInfo::SpecialRegClassID,
- SparcV9SpecialRegClass::fsr);
- if (target.getInstrInfo().constantFitsInImmedField(V9::STXFSRi, Offset))
- MI=BuildMI(V9::STXFSRi,3).addMReg(fsrReg).addMReg(PtrReg).addSImm(Offset);
+ if (useImmediateOffset)
+ MI = BuildMI(V9::STXFSRi,3).addMReg(SparcV9::fsr).addMReg(PtrReg)
+ .addSImm(Offset);
else
- MI=BuildMI(V9::STXFSRr,3).addMReg(fsrReg).addMReg(PtrReg).addMReg(OffReg);
+ MI = BuildMI(V9::STXFSRr,3).addMReg(SparcV9::fsr).addMReg(PtrReg)
+ .addMReg(OffReg);
break;
}
default:
mvec.push_back(MI);
}
+/// cpMem2RegMI - Generate SparcV9 MachineInstrs to load a register
+/// (DestReg) from memory, at [PtrReg + Offset]. Register numbers must be the
+/// unified register numbers. RegType must be the SparcV9 register type
+/// of DestReg. When DestReg is %ccr, scratchReg must be the
+/// number of a free integer register. The newly-generated MachineInstrs
+/// are appended to mvec.
+///
+void SparcV9RegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
+ unsigned PtrReg, int Offset, unsigned DestReg,
+ int RegType, int scratchReg) const {
+ unsigned OffReg = SparcV9::g4; // Use register g4 for holding large offsets
+ bool useImmediateOffset = true;
+
+ // If the Offset will not fit in the signed-immediate field, we put it in
+ // register g4. This takes advantage of the fact that all the opcodes
+ // used below have the same size immed. field.
+ if (RegType != IntCCRegType
+ && !target.getInstrInfo()->constantFitsInImmedField(V9::LDXi, Offset)) {
+ MachineInstr *MI = BuildMI(V9::SETHI, 2).addZImm(Offset).addMReg(OffReg,
+ MachineOperand::Def);
+ MI->getOperand(0).markHi32();
+ mvec.push_back(MI);
+ MI = BuildMI(V9::ORi,3).addMReg(OffReg).addZImm(Offset).addMReg(OffReg,
+ MachineOperand::Def);
+ MI->getOperand(1).markLo32();
+ mvec.push_back(MI);
+ MI = BuildMI(V9::SRAi5,3).addMReg(OffReg).addZImm(0).addMReg(OffReg,
+ MachineOperand::Def);
+ mvec.push_back(MI);
+ useImmediateOffset = false;
+ }
-//---------------------------------------------------------------------------
-// Copy from memory to a reg (i.e., Load) Register number must be the unified
-// register number
-//---------------------------------------------------------------------------
-
-
-void
-SparcV9RegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
- unsigned PtrReg,
- int Offset,
- unsigned DestReg,
- int RegType,
- int scratchReg) const {
- MachineInstr * MI = NULL;
- int OffReg = -1;
-
- // If the Offset will not fit in the signed-immediate field, find an
- // unused register to hold the offset value. This takes advantage of
- // the fact that all the opcodes used below have the same size immed. field.
- // Use the register allocator, PRA, to find an unused reg. at this MI.
- //
- if (RegType != IntCCRegType) // does not use offset below
- if (! target.getInstrInfo().constantFitsInImmedField(V9::LDXi, Offset)) {
-#ifdef CAN_FIND_FREE_REGISTER_TRANSPARENTLY
- RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType));
- OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
-#else
- // Default to using register g4 for holding large offsets
- OffReg = getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
- SparcV9IntRegClass::g4);
-#endif
- assert(OffReg >= 0 && "FIXME: cpReg2MemMI cannot find an unused reg.");
- mvec.push_back(BuildMI(V9::SETSW, 2).addZImm(Offset).addReg(OffReg));
- }
-
+ MachineInstr *MI = 0;
switch (RegType) {
case IntRegType:
- if (target.getInstrInfo().constantFitsInImmedField(V9::LDXi, Offset))
+ if (useImmediateOffset)
MI = BuildMI(V9::LDXi, 3).addMReg(PtrReg).addSImm(Offset)
.addMReg(DestReg, MachineOperand::Def);
else
break;
case FPSingleRegType:
- if (target.getInstrInfo().constantFitsInImmedField(V9::LDFi, Offset))
+ if (useImmediateOffset)
MI = BuildMI(V9::LDFi, 3).addMReg(PtrReg).addSImm(Offset)
.addMReg(DestReg, MachineOperand::Def);
else
break;
case FPDoubleRegType:
- if (target.getInstrInfo().constantFitsInImmedField(V9::LDDFi, Offset))
+ if (useImmediateOffset)
MI= BuildMI(V9::LDDFi, 3).addMReg(PtrReg).addSImm(Offset)
.addMReg(DestReg, MachineOperand::Def);
else
break;
case IntCCRegType:
- assert(scratchReg >= 0 && "Need scratch reg to load %ccr from memory");
- assert(getRegType(scratchReg) ==IntRegType && "Invalid scratch reg");
+ assert(scratchReg >= 0 && getRegType(scratchReg) == IntRegType
+ && "Need a scratch reg of integer type to load or store %ccr");
cpMem2RegMI(mvec, PtrReg, Offset, scratchReg, IntRegType);
- MI = (BuildMI(V9::WRCCRr, 3)
- .addMReg(scratchReg)
- .addMReg(SparcV9IntRegClass::g0)
- .addMReg(getUnifiedRegNum(SparcV9RegInfo::IntCCRegClassID,
- SparcV9IntCCRegClass::ccr), MachineOperand::Def));
+ MI = BuildMI(V9::WRCCRr, 3).addMReg(scratchReg).addMReg(SparcV9::g0)
+ .addMReg(SparcV9::ccr, MachineOperand::Def);
break;
-
+
+ case SpecialRegType: // used only for %fsr itself
case FloatCCRegType: {
- unsigned fsrRegNum = getUnifiedRegNum(SparcV9RegInfo::SpecialRegClassID,
- SparcV9SpecialRegClass::fsr);
- if (target.getInstrInfo().constantFitsInImmedField(V9::LDXFSRi, Offset))
+ if (useImmediateOffset)
MI = BuildMI(V9::LDXFSRi, 3).addMReg(PtrReg).addSImm(Offset)
- .addMReg(fsrRegNum, MachineOperand::UseAndDef);
+ .addMReg(SparcV9::fsr, MachineOperand::Def);
else
MI = BuildMI(V9::LDXFSRr, 3).addMReg(PtrReg).addMReg(OffReg)
- .addMReg(fsrRegNum, MachineOperand::UseAndDef);
+ .addMReg(SparcV9::fsr, MachineOperand::Def);
break;
}
default:
void
SparcV9RegInfo::cpValue2Value(Value *Src, Value *Dest,
- std::vector<MachineInstr*>& mvec) const {
+ std::vector<MachineInstr*>& mvec) const {
int RegType = getRegTypeForDataType(Src->getType());
MachineInstr * MI = NULL;
- switch( RegType ) {
+ switch (RegType) {
case IntRegType:
MI = BuildMI(V9::ADDr, 3).addReg(Src).addMReg(getZeroRegNum())
.addRegDef(Dest);
MI = BuildMI(V9::FMOVD, 2).addReg(Src).addRegDef(Dest);
break;
default:
- assert(0 && "Unknow RegType in CpValu2Value");
+ assert(0 && "Unknown RegType in cpValue2Value");
}
mvec.push_back(MI);
// Print the register assigned to a LR
//---------------------------------------------------------------------------
-void SparcV9RegInfo::printReg(const LiveRange *LR) const {
+void SparcV9RegInfo::printReg(const V9LiveRange *LR) const {
unsigned RegClassID = LR->getRegClassID();
std::cerr << " Node ";
std::cerr << " - could not find a color\n";
return;
}
-
+
// if a color is found
std::cerr << " colored with color "<< LR->getColor();
unsigned uRegName = getUnifiedRegNum(RegClassID, LR->getColor());
-
+
std::cerr << "[";
std::cerr<< getUnifiedRegName(uRegName);
if (RegClassID == FloatRegClassID && LR->getType() == Type::DoubleTy)
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