-//===-- SparcRegInfo.cpp - Sparc Target Register Information --------------===//
+//===-- SparcV9RegInfo.cpp - SparcV9 Target Register Information ----------===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// This file contains implementation of Sparc specific helper methods
+// This file contains implementations of SparcV9 specific helper methods
// used for register allocation.
//
//===----------------------------------------------------------------------===//
-#include "SparcInternals.h"
-#include "SparcRegClassInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/MachineFunctionInfo.h"
-#include "llvm/CodeGen/InstrSelection.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineCodeForInstruction.h"
-#include "llvm/CodeGen/MachineInstrAnnot.h"
-#include "../../CodeGen/RegAlloc/LiveRangeInfo.h" // FIXME!!
-#include "../../CodeGen/RegAlloc/LiveRange.h" // FIXME!!
-#include "llvm/iTerminators.h"
-#include "llvm/iOther.h"
-#include "llvm/Function.h"
+#include "MachineFunctionInfo.h"
+#include "MachineCodeForInstruction.h"
+#include "MachineInstrAnnot.h"
+#include "RegAlloc/LiveRangeInfo.h"
+#include "RegAlloc/LiveRange.h"
#include "llvm/DerivedTypes.h"
+#include "llvm/Function.h"
+#include "llvm/Instructions.h"
+#include "SparcV9Internals.h"
+#include "SparcV9RegClassInfo.h"
+#include "SparcV9RegInfo.h"
+#include "SparcV9FrameInfo.h"
+#include "SparcV9TargetMachine.h"
+#include "SparcV9TmpInstr.h"
+#include <iostream>
+
+namespace llvm {
enum {
BadRegClass = ~0
};
-UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt)
- : TargetRegInfo(tgt), NumOfIntArgRegs(6), NumOfFloatArgRegs(32)
+SparcV9RegInfo::SparcV9RegInfo(const SparcV9TargetMachine &tgt)
+ : target (tgt), NumOfIntArgRegs (6), NumOfFloatArgRegs (32)
{
- MachineRegClassArr.push_back(new SparcIntRegClass(IntRegClassID));
- MachineRegClassArr.push_back(new SparcFloatRegClass(FloatRegClassID));
- MachineRegClassArr.push_back(new SparcIntCCRegClass(IntCCRegClassID));
- MachineRegClassArr.push_back(new SparcFloatCCRegClass(FloatCCRegClassID));
- MachineRegClassArr.push_back(new SparcSpecialRegClass(SpecialRegClassID));
+ MachineRegClassArr.push_back(new SparcV9IntRegClass(IntRegClassID));
+ MachineRegClassArr.push_back(new SparcV9FloatRegClass(FloatRegClassID));
+ MachineRegClassArr.push_back(new SparcV9IntCCRegClass(IntCCRegClassID));
+ MachineRegClassArr.push_back(new SparcV9FloatCCRegClass(FloatCCRegClassID));
+ MachineRegClassArr.push_back(new SparcV9SpecialRegClass(SpecialRegClassID));
- assert(SparcFloatRegClass::StartOfNonVolatileRegs == 32 &&
+ assert(SparcV9FloatRegClass::StartOfNonVolatileRegs == 32 &&
"32 Float regs are used for float arg passing");
}
// getZeroRegNum - returns the register that contains always zero.
// this is the unified register number
//
-int UltraSparcRegInfo::getZeroRegNum() const {
- return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
- SparcIntRegClass::g0);
+unsigned SparcV9RegInfo::getZeroRegNum() const {
+ return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
+ SparcV9IntRegClass::g0);
}
// getCallAddressReg - returns the reg used for pushing the address when a
// method is called. This can be used for other purposes between calls
//
-unsigned UltraSparcRegInfo::getCallAddressReg() const {
- return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
- SparcIntRegClass::o7);
+unsigned SparcV9RegInfo::getCallAddressReg() const {
+ return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
+ SparcV9IntRegClass::o7);
}
// Returns the register containing the return address.
// It should be made sure that this register contains the return
// value when a return instruction is reached.
//
-unsigned UltraSparcRegInfo::getReturnAddressReg() const {
- return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
- SparcIntRegClass::i7);
+unsigned SparcV9RegInfo::getReturnAddressReg() const {
+ return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
+ SparcV9IntRegClass::i7);
}
// Register get name implementations...
-// Int register names in same order as enum in class SparcIntRegClass
+// Int register names in same order as enum in class SparcV9IntRegClass
static const char * const IntRegNames[] = {
"o0", "o1", "o2", "o3", "o4", "o5", "o7",
"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
"o6"
};
-const char * const SparcIntRegClass::getRegName(unsigned reg) const {
+const char * const SparcV9IntRegClass::getRegName(unsigned reg) const {
assert(reg < NumOfAllRegs);
return IntRegNames[reg];
}
"f60", "f61", "f62", "f63"
};
-const char * const SparcFloatRegClass::getRegName(unsigned reg) const {
+const char * const SparcV9FloatRegClass::getRegName(unsigned reg) const {
assert (reg < NumOfAllRegs);
return FloatRegNames[reg];
}
-
static const char * const IntCCRegNames[] = {
"xcc", "icc", "ccr"
};
-const char * const SparcIntCCRegClass::getRegName(unsigned reg) const {
+const char * const SparcV9IntCCRegClass::getRegName(unsigned reg) const {
assert(reg < 3);
return IntCCRegNames[reg];
}
"fcc0", "fcc1", "fcc2", "fcc3"
};
-const char * const SparcFloatCCRegClass::getRegName(unsigned reg) const {
- assert (reg < 5);
+const char * const SparcV9FloatCCRegClass::getRegName(unsigned reg) const {
+ assert (reg < 4);
return FloatCCRegNames[reg];
}
"fsr"
};
-const char * const SparcSpecialRegClass::getRegName(unsigned reg) const {
+const char * const SparcV9SpecialRegClass::getRegName(unsigned reg) const {
assert (reg < 1);
return SpecialRegNames[reg];
}
// Get unified reg number for frame pointer
-unsigned UltraSparcRegInfo::getFramePointer() const {
- return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
- SparcIntRegClass::i6);
+unsigned SparcV9RegInfo::getFramePointer() const {
+ return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
+ SparcV9IntRegClass::i6);
}
// Get unified reg number for stack pointer
-unsigned UltraSparcRegInfo::getStackPointer() const {
- return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
- SparcIntRegClass::o6);
+unsigned SparcV9RegInfo::getStackPointer() const {
+ return getUnifiedRegNum(SparcV9RegInfo::IntRegClassID,
+ SparcV9IntRegClass::o6);
}
// regClassId is set to the register class ID.
//
int
-UltraSparcRegInfo::regNumForIntArg(bool inCallee, bool isVarArgsCall,
+SparcV9RegInfo::regNumForIntArg(bool inCallee, bool isVarArgsCall,
unsigned argNo, unsigned& regClassId) const
{
regClassId = IntRegClassID;
if (argNo >= NumOfIntArgRegs)
return getInvalidRegNum();
else
- return argNo + (inCallee? SparcIntRegClass::i0 : SparcIntRegClass::o0);
+ return argNo + (inCallee? SparcV9IntRegClass::i0 : SparcV9IntRegClass::o0);
}
// Get the register number for the specified FP argument #argNo,
// regClassId is set to the register class ID.
//
int
-UltraSparcRegInfo::regNumForFPArg(unsigned regType,
+SparcV9RegInfo::regNumForFPArg(unsigned regType,
bool inCallee, bool isVarArgsCall,
unsigned argNo, unsigned& regClassId) const
{
regClassId = FloatRegClassID;
if (regType == FPSingleRegType)
return (argNo*2+1 >= NumOfFloatArgRegs)?
- getInvalidRegNum() : SparcFloatRegClass::f0 + (argNo * 2 + 1);
+ getInvalidRegNum() : SparcV9FloatRegClass::f0 + (argNo * 2 + 1);
else if (regType == FPDoubleRegType)
return (argNo*2 >= NumOfFloatArgRegs)?
- getInvalidRegNum() : SparcFloatRegClass::f0 + (argNo * 2);
+ getInvalidRegNum() : SparcV9FloatRegClass::f0 + (argNo * 2);
else
assert(0 && "Illegal FP register type");
return 0;
// Finds the return address of a call sparc specific call instruction
//---------------------------------------------------------------------------
-// The following 4 methods are used to find the RegType (SparcInternals.h)
+// The following 4 methods are used to find the RegType (SparcV9Internals.h)
// of a LiveRange, a Value, and for a given register unified reg number.
//
-int UltraSparcRegInfo::getRegTypeForClassAndType(unsigned regClassID,
+int SparcV9RegInfo::getRegTypeForClassAndType(unsigned regClassID,
const Type* type) const
{
switch (regClassID) {
}
}
-int UltraSparcRegInfo::getRegTypeForDataType(const Type* type) const
+int SparcV9RegInfo::getRegTypeForDataType(const Type* type) const
{
return getRegTypeForClassAndType(getRegClassIDOfType(type), type);
}
-int UltraSparcRegInfo::getRegTypeForLR(const LiveRange *LR) const
+int SparcV9RegInfo::getRegTypeForLR(const LiveRange *LR) const
{
return getRegTypeForClassAndType(LR->getRegClassID(), LR->getType());
}
-int UltraSparcRegInfo::getRegType(int unifiedRegNum) const
+int SparcV9RegInfo::getRegType(int unifiedRegNum) const
{
if (unifiedRegNum < 32)
return IntRegType;
return FPSingleRegType;
else if (unifiedRegNum < (64 + 32))
return FPDoubleRegType;
- else if (unifiedRegNum < (64+32+4))
- return FloatCCRegType;
- else if (unifiedRegNum < (64+32+4+2))
- return IntCCRegType;
+ else if (unifiedRegNum < (64+32+3))
+ return IntCCRegType;
+ else if (unifiedRegNum < (64+32+3+4))
+ return FloatCCRegType;
+ else if (unifiedRegNum < (64+32+3+4+1))
+ return SpecialRegType;
else
assert(0 && "Invalid unified register number in getRegType");
return 0;
// To find the register class used for a specified Type
//
-unsigned UltraSparcRegInfo::getRegClassIDOfType(const Type *type,
+unsigned SparcV9RegInfo::getRegClassIDOfType(const Type *type,
bool isCCReg) const {
- Type::PrimitiveID ty = type->getPrimitiveID();
+ Type::TypeID ty = type->getTypeID();
unsigned res;
// FIXME: Comparing types like this isn't very safe...
return res;
}
-unsigned UltraSparcRegInfo::getRegClassIDOfRegType(int regType) const {
+unsigned SparcV9RegInfo::getRegClassIDOfRegType(int regType) const {
switch(regType) {
case IntRegType: return IntRegClassID;
case FPSingleRegType:
case FPDoubleRegType: return FloatRegClassID;
case IntCCRegType: return IntCCRegClassID;
case FloatCCRegType: return FloatCCRegClassID;
+ case SpecialRegType: return SpecialRegClassID;
default:
assert(0 && "Invalid register type in getRegClassIDOfRegType");
return 0;
// Suggests a register for the ret address in the RET machine instruction.
// We always suggest %i7 by convention.
//---------------------------------------------------------------------------
-void UltraSparcRegInfo::suggestReg4RetAddr(MachineInstr *RetMI,
+void SparcV9RegInfo::suggestReg4RetAddr(MachineInstr *RetMI,
LiveRangeInfo& LRI) const {
- assert(target.getInstrInfo().isReturn(RetMI->getOpCode()));
+ assert(target.getInstrInfo()->isReturn(RetMI->getOpcode()));
// return address is always mapped to i7 so set it immediately
RetMI->SetRegForOperand(0, getUnifiedRegNum(IntRegClassID,
- SparcIntRegClass::i7));
+ SparcV9IntRegClass::i7));
// Possible Optimization:
// Instead of setting the color, we can suggest one. In that case,
// assert( RetAddrVal && "LR for ret address must be created at start");
// LiveRange * RetAddrLR = LRI.getLiveRangeForValue( RetAddrVal);
// RetAddrLR->setSuggestedColor(getUnifiedRegNum( IntRegClassID,
- // SparcIntRegOrdr::i7) );
+ // SparcV9IntRegOrdr::i7) );
}
//---------------------------------------------------------------------------
// Suggests a register for the ret address in the JMPL/CALL machine instr.
-// Sparc ABI dictates that %o7 be used for this purpose.
+// SparcV9 ABI dictates that %o7 be used for this purpose.
//---------------------------------------------------------------------------
void
-UltraSparcRegInfo::suggestReg4CallAddr(MachineInstr * CallMI,
+SparcV9RegInfo::suggestReg4CallAddr(MachineInstr * CallMI,
LiveRangeInfo& LRI) const
{
CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
assert(RetAddrLR && "INTERNAL ERROR: No LR for return address of call!");
unsigned RegClassID = RetAddrLR->getRegClassID();
- RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID, SparcIntRegClass::o7));
+ RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID, SparcV9IntRegClass::o7));
}
//---------------------------------------------------------------------------
// This method will suggest colors to incoming args to a method.
-// According to the Sparc ABI, the first 6 incoming args are in
+// According to the SparcV9 ABI, the first 6 incoming args are in
// %i0 - %i5 (if they are integer) OR in %f0 - %f31 (if they are float).
// If the arg is passed on stack due to the lack of regs, NOTHING will be
// done - it will be colored (or spilled) as a normal live range.
//---------------------------------------------------------------------------
-void UltraSparcRegInfo::suggestRegs4MethodArgs(const Function *Meth,
+void SparcV9RegInfo::suggestRegs4MethodArgs(const Function *Meth,
LiveRangeInfo& LRI) const
{
// Check if this is a varArgs function. needed for choosing regs.
// Count the arguments, *ignoring* whether they are int or FP args.
// Use this common arg numbering to pick the right int or fp register.
unsigned argNo=0;
- for(Function::const_aiterator I = Meth->abegin(), E = Meth->aend();
+ for(Function::const_arg_iterator I = Meth->arg_begin(), E = Meth->arg_end();
I != E; ++I, ++argNo) {
LiveRange *LR = LRI.getLiveRangeForValue(I);
assert(LR && "No live range found for method arg");
// the correct hardware registers if they did not receive the correct
// (suggested) color through graph coloring.
//---------------------------------------------------------------------------
-void UltraSparcRegInfo::colorMethodArgs(const Function *Meth,
+void SparcV9RegInfo::colorMethodArgs(const Function *Meth,
LiveRangeInfo &LRI,
std::vector<MachineInstr*>& InstrnsBefore,
std::vector<MachineInstr*>& InstrnsAfter) const {
// for each argument
// for each argument. count INT and FP arguments separately.
unsigned argNo=0, intArgNo=0, fpArgNo=0;
- for(Function::const_aiterator I = Meth->abegin(), E = Meth->aend();
+ for(Function::const_arg_iterator I = Meth->arg_begin(), E = Meth->arg_end();
I != E; ++I, ++argNo) {
// get the LR of arg
LiveRange *LR = LRI.getLiveRangeForValue(I);
//
if( isArgInReg ) {
if( regClassIDOfArgReg != RegClassID ) {
- assert(0 && "This could should work but it is not tested yet");
+ // NOTE: This code has not been well-tested.
// It is a variable argument call: the float reg must go in a %o reg.
// We have to move an int reg to a float reg via memory.
regClassIDOfArgReg == IntRegClassID &&
"This should only be an Int register for an FP argument");
- int TmpOff = MachineFunction::get(Meth).getInfo()->pushTempValue(
+ int TmpOff = MachineFunction::get(Meth).getInfo<SparcV9FunctionInfo>()->pushTempValue(
getSpilledRegSize(regType));
cpReg2MemMI(InstrnsBefore,
UniArgReg, getFramePointer(), TmpOff, IntRegType);
// Now the arg is coming on stack. Since the LR received a register,
// we just have to load the arg on stack into that register
//
- const TargetFrameInfo& frameInfo = target.getFrameInfo();
+ const TargetFrameInfo& frameInfo = *target.getFrameInfo();
int offsetFromFP =
frameInfo.getIncomingArgOffset(MachineFunction::get(Meth),
argNo);
// a full double-word so the offset does not need to be adjusted.
if (regType == FPSingleRegType) {
unsigned argSize = target.getTargetData().getTypeSize(LR->getType());
- unsigned slotSize = frameInfo.getSizeOfEachArgOnStack();
+ unsigned slotSize = SparcV9FrameInfo::SizeOfEachArgOnStack;
assert(argSize <= slotSize && "Insufficient slot size!");
offsetFromFP += slotSize - argSize;
}
// since this method is called before any other method that makes
// uses of the stack pos of the LR (e.g., updateMachineInstr)
//
- const TargetFrameInfo& frameInfo = target.getFrameInfo();
+ const TargetFrameInfo& frameInfo = *target.getFrameInfo();
int offsetFromFP =
frameInfo.getIncomingArgOffset(MachineFunction::get(Meth),
argNo);
// a full double-word so the offset does not need to be adjusted.
if (regType == FPSingleRegType) {
unsigned argSize = target.getTargetData().getTypeSize(LR->getType());
- unsigned slotSize = frameInfo.getSizeOfEachArgOnStack();
+ unsigned slotSize = SparcV9FrameInfo::SizeOfEachArgOnStack;
assert(argSize <= slotSize && "Insufficient slot size!");
offsetFromFP += slotSize - argSize;
}
// This method is called before graph coloring to suggest colors to the
// outgoing call args and the return value of the call.
//---------------------------------------------------------------------------
-void UltraSparcRegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
+void SparcV9RegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
LiveRangeInfo& LRI) const {
- assert ( (target.getInstrInfo()).isCall(CallMI->getOpCode()) );
+ assert ( (target.getInstrInfo())->isCall(CallMI->getOpcode()) );
CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
// now suggest a register depending on the register class of ret arg
if( RegClassID == IntRegClassID )
- RetValLR->setSuggestedColor(SparcIntRegClass::o0);
+ RetValLR->setSuggestedColor(SparcV9IntRegClass::o0);
else if (RegClassID == FloatRegClassID )
- RetValLR->setSuggestedColor(SparcFloatRegClass::f0 );
+ RetValLR->setSuggestedColor(SparcV9FloatRegClass::f0 );
else assert( 0 && "Unknown reg class for return value of call\n");
}
// this method is called for an LLVM return instruction to identify which
// values will be returned from this method and to suggest colors.
//---------------------------------------------------------------------------
-void UltraSparcRegInfo::suggestReg4RetValue(MachineInstr *RetMI,
+void SparcV9RegInfo::suggestReg4RetValue(MachineInstr *RetMI,
LiveRangeInfo& LRI) const {
- assert( (target.getInstrInfo()).isReturn( RetMI->getOpCode() ) );
+ assert( target.getInstrInfo()->isReturn( RetMI->getOpcode() ) );
suggestReg4RetAddr(RetMI, LRI);
if (const Value *RetVal = retI->getReturnValue())
if (LiveRange *const LR = LRI.getLiveRangeForValue(RetVal))
LR->setSuggestedColor(LR->getRegClassID() == IntRegClassID
- ? (unsigned) SparcIntRegClass::i0
- : (unsigned) SparcFloatRegClass::f0);
+ ? (unsigned) SparcV9IntRegClass::i0
+ : (unsigned) SparcV9FloatRegClass::f0);
}
//---------------------------------------------------------------------------
//---------------------------------------------------------------------------
bool
-UltraSparcRegInfo::regTypeNeedsScratchReg(int RegType,
+SparcV9RegInfo::regTypeNeedsScratchReg(int RegType,
int& scratchRegType) const
{
if (RegType == IntCCRegType)
//---------------------------------------------------------------------------
void
-UltraSparcRegInfo::cpReg2RegMI(std::vector<MachineInstr*>& mvec,
+SparcV9RegInfo::cpReg2RegMI(std::vector<MachineInstr*>& mvec,
unsigned SrcReg,
unsigned DestReg,
int RegType) const {
if (getRegType(DestReg) == IntRegType) {
// copy intCC reg to int reg
MI = (BuildMI(V9::RDCCR, 2)
- .addMReg(getUnifiedRegNum(UltraSparcRegInfo::IntCCRegClassID,
- SparcIntCCRegClass::ccr))
- .addMReg(DestReg,MOTy::Def));
+ .addMReg(getUnifiedRegNum(SparcV9RegInfo::IntCCRegClassID,
+ SparcV9IntCCRegClass::ccr))
+ .addMReg(DestReg,MachineOperand::Def));
} else {
// copy int reg to intCC reg
assert(getRegType(SrcReg) == IntRegType
&& "Can only copy CC reg to/from integer reg");
MI = (BuildMI(V9::WRCCRr, 3)
.addMReg(SrcReg)
- .addMReg(SparcIntRegClass::g0)
- .addMReg(getUnifiedRegNum(UltraSparcRegInfo::IntCCRegClassID,
- SparcIntCCRegClass::ccr), MOTy::Def));
+ .addMReg(SparcV9IntRegClass::g0)
+ .addMReg(getUnifiedRegNum(SparcV9RegInfo::IntCCRegClassID,
+ SparcV9IntCCRegClass::ccr),
+ MachineOperand::Def));
}
break;
case IntRegType:
MI = BuildMI(V9::ADDr, 3).addMReg(SrcReg).addMReg(getZeroRegNum())
- .addMReg(DestReg, MOTy::Def);
+ .addMReg(DestReg, MachineOperand::Def);
break;
case FPSingleRegType:
- MI = BuildMI(V9::FMOVS, 2).addMReg(SrcReg).addMReg(DestReg, MOTy::Def);
+ MI = BuildMI(V9::FMOVS, 2).addMReg(SrcReg)
+ .addMReg(DestReg, MachineOperand::Def);
break;
case FPDoubleRegType:
- MI = BuildMI(V9::FMOVD, 2).addMReg(SrcReg).addMReg(DestReg, MOTy::Def);
+ MI = BuildMI(V9::FMOVD, 2).addMReg(SrcReg)
+ .addMReg(DestReg, MachineOperand::Def);
break;
default:
mvec.push_back(MI);
}
-//---------------------------------------------------------------------------
-// Copy from a register to memory (i.e., Store). Register number must
-// be the unified register number
-//---------------------------------------------------------------------------
-
-
-void
-UltraSparcRegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec,
- unsigned SrcReg,
- unsigned PtrReg,
- int Offset, int RegType,
- int scratchReg) const {
- MachineInstr * MI = NULL;
- int OffReg = -1;
-
- // If the Offset will not fit in the signed-immediate field, find an
- // unused register to hold the offset value. This takes advantage of
- // the fact that all the opcodes used below have the same size immed. field.
- // Use the register allocator, PRA, to find an unused reg. at this MI.
- //
- if (RegType != IntCCRegType) // does not use offset below
- if (! target.getInstrInfo().constantFitsInImmedField(V9::LDXi, Offset)) {
-#ifdef CAN_FIND_FREE_REGISTER_TRANSPARENTLY
- RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType));
- OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
-#else
- // Default to using register g2 for holding large offsets
- OffReg = getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
- SparcIntRegClass::g4);
-#endif
- assert(OffReg >= 0 && "FIXME: cpReg2MemMI cannot find an unused reg.");
- mvec.push_back(BuildMI(V9::SETSW, 2).addZImm(Offset).addReg(OffReg));
- }
+/// cpReg2MemMI - Generate SparcV9 MachineInstrs to store a register
+/// (SrcReg) to memory, at [PtrReg + Offset]. Register numbers must be the
+/// unified register numbers. RegType must be the SparcV9 register type
+/// of SrcReg. When SrcReg is %ccr, scratchReg must be the
+/// number of a free integer register. The newly-generated MachineInstrs
+/// are appended to mvec.
+///
+void SparcV9RegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec,
+ unsigned SrcReg, unsigned PtrReg, int Offset,
+ int RegType, int scratchReg) const {
+ unsigned OffReg = SparcV9::g4; // Use register g4 for holding large offsets
+ bool useImmediateOffset = true;
+
+ // If the Offset will not fit in the signed-immediate field, we put it in
+ // register g4. This takes advantage of the fact that all the opcodes
+ // used below have the same size immed. field.
+ if (RegType != IntCCRegType
+ && !target.getInstrInfo()->constantFitsInImmedField(V9::LDXi, Offset)) {
+ // Put the offset into a register. We could do this in fewer steps,
+ // in some cases (see CreateSETSWConst()) but we're being lazy.
+ MachineInstr *MI = BuildMI(V9::SETHI, 2).addZImm(Offset).addMReg(OffReg,
+ MachineOperand::Def);
+ MI->getOperand(0).markHi32();
+ mvec.push_back(MI);
+ MI = BuildMI(V9::ORi,3).addMReg(OffReg).addZImm(Offset).addMReg(OffReg,
+ MachineOperand::Def);
+ MI->getOperand(1).markLo32();
+ mvec.push_back(MI);
+ MI = BuildMI(V9::SRAi5,3).addMReg(OffReg).addZImm(0).addMReg(OffReg,
+ MachineOperand::Def);
+ mvec.push_back(MI);
+ useImmediateOffset = false;
+ }
+ MachineInstr *MI = 0;
switch (RegType) {
case IntRegType:
- if (target.getInstrInfo().constantFitsInImmedField(V9::STXi, Offset))
+ if (useImmediateOffset)
MI = BuildMI(V9::STXi,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset);
else
MI = BuildMI(V9::STXr,3).addMReg(SrcReg).addMReg(PtrReg).addMReg(OffReg);
break;
case FPSingleRegType:
- if (target.getInstrInfo().constantFitsInImmedField(V9::STFi, Offset))
+ if (useImmediateOffset)
MI = BuildMI(V9::STFi, 3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset);
else
MI = BuildMI(V9::STFr, 3).addMReg(SrcReg).addMReg(PtrReg).addMReg(OffReg);
break;
case FPDoubleRegType:
- if (target.getInstrInfo().constantFitsInImmedField(V9::STDFi, Offset))
+ if (useImmediateOffset)
MI = BuildMI(V9::STDFi,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(Offset);
else
MI = BuildMI(V9::STDFr,3).addMReg(SrcReg).addMReg(PtrReg).addSImm(OffReg);
break;
case IntCCRegType:
- assert(scratchReg >= 0 && "Need scratch reg to store %ccr to memory");
- assert(getRegType(scratchReg) ==IntRegType && "Invalid scratch reg");
- MI = (BuildMI(V9::RDCCR, 2)
- .addMReg(getUnifiedRegNum(UltraSparcRegInfo::IntCCRegClassID,
- SparcIntCCRegClass::ccr))
- .addMReg(scratchReg, MOTy::Def));
+ assert(scratchReg >= 0 && getRegType(scratchReg) == IntRegType
+ && "Need a scratch reg of integer type to load or store %ccr");
+ MI = BuildMI(V9::RDCCR, 2).addMReg(SparcV9::ccr)
+ .addMReg(scratchReg, MachineOperand::Def);
mvec.push_back(MI);
-
cpReg2MemMI(mvec, scratchReg, PtrReg, Offset, IntRegType);
return;
+ case SpecialRegType: // used only for %fsr itself.
case FloatCCRegType: {
- unsigned fsrReg = getUnifiedRegNum(UltraSparcRegInfo::SpecialRegClassID,
- SparcSpecialRegClass::fsr);
- if (target.getInstrInfo().constantFitsInImmedField(V9::STXFSRi, Offset))
- MI=BuildMI(V9::STXFSRi,3).addMReg(fsrReg).addMReg(PtrReg).addSImm(Offset);
+ if (useImmediateOffset)
+ MI = BuildMI(V9::STXFSRi,3).addMReg(SparcV9::fsr).addMReg(PtrReg)
+ .addSImm(Offset);
else
- MI=BuildMI(V9::STXFSRr,3).addMReg(fsrReg).addMReg(PtrReg).addMReg(OffReg);
+ MI = BuildMI(V9::STXFSRr,3).addMReg(SparcV9::fsr).addMReg(PtrReg)
+ .addMReg(OffReg);
break;
}
default:
mvec.push_back(MI);
}
+/// cpMem2RegMI - Generate SparcV9 MachineInstrs to load a register
+/// (DestReg) from memory, at [PtrReg + Offset]. Register numbers must be the
+/// unified register numbers. RegType must be the SparcV9 register type
+/// of DestReg. When DestReg is %ccr, scratchReg must be the
+/// number of a free integer register. The newly-generated MachineInstrs
+/// are appended to mvec.
+///
+void SparcV9RegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
+ unsigned PtrReg, int Offset, unsigned DestReg,
+ int RegType, int scratchReg) const {
+ unsigned OffReg = SparcV9::g4; // Use register g4 for holding large offsets
+ bool useImmediateOffset = true;
+
+ // If the Offset will not fit in the signed-immediate field, we put it in
+ // register g4. This takes advantage of the fact that all the opcodes
+ // used below have the same size immed. field.
+ if (RegType != IntCCRegType
+ && !target.getInstrInfo()->constantFitsInImmedField(V9::LDXi, Offset)) {
+ MachineInstr *MI = BuildMI(V9::SETHI, 2).addZImm(Offset).addMReg(OffReg,
+ MachineOperand::Def);
+ MI->getOperand(0).markHi32();
+ mvec.push_back(MI);
+ MI = BuildMI(V9::ORi,3).addMReg(OffReg).addZImm(Offset).addMReg(OffReg,
+ MachineOperand::Def);
+ MI->getOperand(1).markLo32();
+ mvec.push_back(MI);
+ MI = BuildMI(V9::SRAi5,3).addMReg(OffReg).addZImm(0).addMReg(OffReg,
+ MachineOperand::Def);
+ mvec.push_back(MI);
+ useImmediateOffset = false;
+ }
-//---------------------------------------------------------------------------
-// Copy from memory to a reg (i.e., Load) Register number must be the unified
-// register number
-//---------------------------------------------------------------------------
-
-
-void
-UltraSparcRegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
- unsigned PtrReg,
- int Offset,
- unsigned DestReg,
- int RegType,
- int scratchReg) const {
- MachineInstr * MI = NULL;
- int OffReg = -1;
-
- // If the Offset will not fit in the signed-immediate field, find an
- // unused register to hold the offset value. This takes advantage of
- // the fact that all the opcodes used below have the same size immed. field.
- // Use the register allocator, PRA, to find an unused reg. at this MI.
- //
- if (RegType != IntCCRegType) // does not use offset below
- if (! target.getInstrInfo().constantFitsInImmedField(V9::LDXi, Offset)) {
-#ifdef CAN_FIND_FREE_REGISTER_TRANSPARENTLY
- RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType));
- OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
-#else
- // Default to using register g2 for holding large offsets
- OffReg = getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
- SparcIntRegClass::g4);
-#endif
- assert(OffReg >= 0 && "FIXME: cpReg2MemMI cannot find an unused reg.");
- mvec.push_back(BuildMI(V9::SETSW, 2).addZImm(Offset).addReg(OffReg));
- }
-
+ MachineInstr *MI = 0;
switch (RegType) {
case IntRegType:
- if (target.getInstrInfo().constantFitsInImmedField(V9::LDXi, Offset))
- MI = BuildMI(V9::LDXi, 3).addMReg(PtrReg).addSImm(Offset).addMReg(DestReg,
- MOTy::Def);
+ if (useImmediateOffset)
+ MI = BuildMI(V9::LDXi, 3).addMReg(PtrReg).addSImm(Offset)
+ .addMReg(DestReg, MachineOperand::Def);
else
- MI = BuildMI(V9::LDXr, 3).addMReg(PtrReg).addMReg(OffReg).addMReg(DestReg,
- MOTy::Def);
+ MI = BuildMI(V9::LDXr, 3).addMReg(PtrReg).addMReg(OffReg)
+ .addMReg(DestReg, MachineOperand::Def);
break;
case FPSingleRegType:
- if (target.getInstrInfo().constantFitsInImmedField(V9::LDFi, Offset))
- MI = BuildMI(V9::LDFi, 3).addMReg(PtrReg).addSImm(Offset).addMReg(DestReg,
- MOTy::Def);
+ if (useImmediateOffset)
+ MI = BuildMI(V9::LDFi, 3).addMReg(PtrReg).addSImm(Offset)
+ .addMReg(DestReg, MachineOperand::Def);
else
- MI = BuildMI(V9::LDFr, 3).addMReg(PtrReg).addMReg(OffReg).addMReg(DestReg,
- MOTy::Def);
+ MI = BuildMI(V9::LDFr, 3).addMReg(PtrReg).addMReg(OffReg)
+ .addMReg(DestReg, MachineOperand::Def);
break;
case FPDoubleRegType:
- if (target.getInstrInfo().constantFitsInImmedField(V9::LDDFi, Offset))
- MI= BuildMI(V9::LDDFi, 3).addMReg(PtrReg).addSImm(Offset).addMReg(DestReg,
- MOTy::Def);
+ if (useImmediateOffset)
+ MI= BuildMI(V9::LDDFi, 3).addMReg(PtrReg).addSImm(Offset)
+ .addMReg(DestReg, MachineOperand::Def);
else
- MI= BuildMI(V9::LDDFr, 3).addMReg(PtrReg).addMReg(OffReg).addMReg(DestReg,
- MOTy::Def);
+ MI= BuildMI(V9::LDDFr, 3).addMReg(PtrReg).addMReg(OffReg)
+ .addMReg(DestReg, MachineOperand::Def);
break;
case IntCCRegType:
- assert(scratchReg >= 0 && "Need scratch reg to load %ccr from memory");
- assert(getRegType(scratchReg) ==IntRegType && "Invalid scratch reg");
+ assert(scratchReg >= 0 && getRegType(scratchReg) == IntRegType
+ && "Need a scratch reg of integer type to load or store %ccr");
cpMem2RegMI(mvec, PtrReg, Offset, scratchReg, IntRegType);
- MI = (BuildMI(V9::WRCCRr, 3)
- .addMReg(scratchReg)
- .addMReg(SparcIntRegClass::g0)
- .addMReg(getUnifiedRegNum(UltraSparcRegInfo::IntCCRegClassID,
- SparcIntCCRegClass::ccr), MOTy::Def));
+ MI = BuildMI(V9::WRCCRr, 3).addMReg(scratchReg).addMReg(SparcV9::g0)
+ .addMReg(SparcV9::ccr, MachineOperand::Def);
break;
+ case SpecialRegType: // used only for %fsr itself
case FloatCCRegType: {
- unsigned fsrRegNum = getUnifiedRegNum(UltraSparcRegInfo::SpecialRegClassID,
- SparcSpecialRegClass::fsr);
- if (target.getInstrInfo().constantFitsInImmedField(V9::LDXFSRi, Offset))
+ if (useImmediateOffset)
MI = BuildMI(V9::LDXFSRi, 3).addMReg(PtrReg).addSImm(Offset)
- .addMReg(fsrRegNum, MOTy::UseAndDef);
+ .addMReg(SparcV9::fsr, MachineOperand::Def);
else
MI = BuildMI(V9::LDXFSRr, 3).addMReg(PtrReg).addMReg(OffReg)
- .addMReg(fsrRegNum, MOTy::UseAndDef);
+ .addMReg(SparcV9::fsr, MachineOperand::Def);
break;
}
default:
void
-UltraSparcRegInfo::cpValue2Value(Value *Src, Value *Dest,
- std::vector<MachineInstr*>& mvec) const {
+SparcV9RegInfo::cpValue2Value(Value *Src, Value *Dest,
+ std::vector<MachineInstr*>& mvec) const {
int RegType = getRegTypeForDataType(Src->getType());
MachineInstr * MI = NULL;
- switch( RegType ) {
+ switch (RegType) {
case IntRegType:
MI = BuildMI(V9::ADDr, 3).addReg(Src).addMReg(getZeroRegNum())
.addRegDef(Dest);
MI = BuildMI(V9::FMOVD, 2).addReg(Src).addRegDef(Dest);
break;
default:
- assert(0 && "Unknow RegType in CpValu2Value");
+ assert(0 && "Unknown RegType in cpValue2Value");
}
mvec.push_back(MI);
// Print the register assigned to a LR
//---------------------------------------------------------------------------
-void UltraSparcRegInfo::printReg(const LiveRange *LR) const {
+void SparcV9RegInfo::printReg(const LiveRange *LR) const {
unsigned RegClassID = LR->getRegClassID();
std::cerr << " Node ";
std::cerr << "+" << getUnifiedRegName(uRegName+1);
std::cerr << "]\n";
}
+
+} // End llvm namespace
projects / oota-llvm.git / blobdiff