#include "SparcInternals.h"
#include "SparcRegClassInfo.h"
#include "llvm/Target/Sparc.h"
-#include "llvm/CodeGen/MachineCodeForMethod.h"
+#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/PhyRegAlloc.h"
#include "llvm/CodeGen/InstrSelection.h"
+#include "llvm/CodeGen/InstrSelectionSupport.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrAnnot.h"
#include "llvm/CodeGen/RegAllocCommon.h"
#include <iostream>
#include <values.h>
using std::cerr;
+using std::vector;
UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt)
- : MachineRegInfo(tgt), UltraSparcInfo(&tgt), NumOfIntArgRegs(6),
+ : MachineRegInfo(tgt), NumOfIntArgRegs(6),
NumOfFloatArgRegs(32), InvalidRegNum(1000) {
MachineRegClassArr.push_back(new SparcIntRegClass(IntRegClassID));
MachineRegClassArr.push_back(new SparcFloatRegClass(FloatRegClassID));
MachineRegClassArr.push_back(new SparcIntCCRegClass(IntCCRegClassID));
MachineRegClassArr.push_back(new SparcFloatCCRegClass(FloatCCRegClassID));
-
- assert(SparcFloatRegOrder::StartOfNonVolatileRegs == 32 &&
+
+ assert(SparcFloatRegClass::StartOfNonVolatileRegs == 32 &&
"32 Float regs are used for float arg passing");
}
// this is the unified register number
//
int UltraSparcRegInfo::getZeroRegNum() const {
- return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
- SparcIntRegOrder::g0);
+ return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
+ SparcIntRegClass::g0);
}
// getCallAddressReg - returns the reg used for pushing the address when a
// method is called. This can be used for other purposes between calls
//
unsigned UltraSparcRegInfo::getCallAddressReg() const {
- return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
- SparcIntRegOrder::o7);
+ return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
+ SparcIntRegClass::o7);
}
// Returns the register containing the return address.
// value when a return instruction is reached.
//
unsigned UltraSparcRegInfo::getReturnAddressReg() const {
- return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
- SparcIntRegOrder::i7);
+ return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
+ SparcIntRegClass::i7);
+}
+
+// Register get name implementations...
+
+// Int register names in same order as enum in class SparcIntRegClass
+static const char * const IntRegNames[] = {
+ "o0", "o1", "o2", "o3", "o4", "o5", "o7",
+ "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
+ "i0", "i1", "i2", "i3", "i4", "i5",
+ "i6", "i7",
+ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
+ "o6"
+};
+
+const char * const SparcIntRegClass::getRegName(unsigned reg) {
+ assert(reg < NumOfAllRegs);
+ return IntRegNames[reg];
+}
+
+static const char * const FloatRegNames[] = {
+ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",
+ "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19",
+ "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29",
+ "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
+ "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49",
+ "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59",
+ "f60", "f61", "f62", "f63"
+};
+
+const char * const SparcFloatRegClass::getRegName(unsigned reg) {
+ assert (reg < NumOfAllRegs);
+ return FloatRegNames[reg];
+}
+
+
+static const char * const IntCCRegNames[] = {
+ "xcc", "ccr"
+};
+
+const char * const SparcIntCCRegClass::getRegName(unsigned reg) {
+ assert(reg < 2);
+ return IntCCRegNames[reg];
+}
+
+static const char * const FloatCCRegNames[] = {
+ "fcc0", "fcc1", "fcc2", "fcc3"
+};
+
+const char * const SparcFloatCCRegClass::getRegName(unsigned reg) {
+ assert (reg < 4);
+ return FloatCCRegNames[reg];
}
// given the unified register number, this gives the name
// for generating assembly code or debugging.
//
-const std::string UltraSparcRegInfo::getUnifiedRegName(int reg) const {
+const char * const UltraSparcRegInfo::getUnifiedRegName(int reg) const {
if( reg < 32 )
- return SparcIntRegOrder::getRegName(reg);
+ return SparcIntRegClass::getRegName(reg);
else if ( reg < (64 + 32) )
- return SparcFloatRegOrder::getRegName( reg - 32);
+ return SparcFloatRegClass::getRegName( reg - 32);
else if( reg < (64+32+4) )
- return SparcFloatCCRegOrder::getRegName( reg -32 - 64);
+ return SparcFloatCCRegClass::getRegName( reg -32 - 64);
else if( reg < (64+32+4+2) ) // two names: %xcc and %ccr
- return SparcIntCCRegOrder::getRegName( reg -32 - 64 - 4);
+ return SparcIntCCRegClass::getRegName( reg -32 - 64 - 4);
else if (reg== InvalidRegNum) //****** TODO: Remove */
return "<*NoReg*>";
else
// Get unified reg number for frame pointer
unsigned UltraSparcRegInfo::getFramePointer() const {
- return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
- SparcIntRegOrder::i6);
+ return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
+ SparcIntRegClass::i6);
}
// Get unified reg number for stack pointer
unsigned UltraSparcRegInfo::getStackPointer() const {
- return this->getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
- SparcIntRegOrder::o6);
+ return getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
+ SparcIntRegClass::o6);
}
if (argNo >= NumOfIntArgRegs)
return InvalidRegNum;
else
- return argNo + (inCallee? SparcIntRegOrder::i0 : SparcIntRegOrder::o0);
+ return argNo + (inCallee? SparcIntRegClass::i0 : SparcIntRegClass::o0);
}
// Get the register number for the specified FP arg#,
regClassId = FloatRegClassID;
if (regType == FPSingleRegType)
return (argNo*2+1 >= NumOfFloatArgRegs)?
- InvalidRegNum : SparcFloatRegOrder::f0 + (argNo * 2 + 1);
+ InvalidRegNum : SparcFloatRegClass::f0 + (argNo * 2 + 1);
else if (regType == FPDoubleRegType)
return (argNo*2 >= NumOfFloatArgRegs)?
- InvalidRegNum : SparcFloatRegOrder::f0 + (argNo * 2);
+ InvalidRegNum : SparcFloatRegClass::f0 + (argNo * 2);
else
assert(0 && "Illegal FP register type");
+ return 0;
}
}
// Finds the return address of a call sparc specific call instruction
//---------------------------------------------------------------------------
-// The following 4 methods are used to find the RegType (see enum above)
+// The following 4 methods are used to find the RegType (SparcInternals.h)
// of a LiveRange, a Value, and for a given register unified reg number.
//
int UltraSparcRegInfo::getRegType(unsigned regClassID,
return getRegType(getRegClassIDOfValue(Val), Val->getType());
}
-int UltraSparcRegInfo::getRegType(int reg) const {
- if (reg < 32)
+int UltraSparcRegInfo::getRegType(int unifiedRegNum) const {
+ if (unifiedRegNum < 32)
return IntRegType;
- else if (reg < (32 + 32))
+ else if (unifiedRegNum < (32 + 32))
return FPSingleRegType;
- else if (reg < (64 + 32))
+ else if (unifiedRegNum < (64 + 32))
return FPDoubleRegType;
- else if (reg < (64+32+4))
+ else if (unifiedRegNum < (64+32+4))
return FloatCCRegType;
- else if (reg < (64+32+4+2))
+ else if (unifiedRegNum < (64+32+4+2))
return IntCCRegType;
else
- assert(0 && "Invalid register number in getRegType");
+ assert(0 && "Invalid unified register number in getRegType");
return 0;
}
+// To find the register class used for a specified Type
+//
+unsigned UltraSparcRegInfo::getRegClassIDOfType(const Type *type,
+ bool isCCReg) const {
+ Type::PrimitiveID ty = type->getPrimitiveID();
+ unsigned res;
+
+ // FIXME: Comparing types like this isn't very safe...
+ if ((ty && ty <= Type::LongTyID) || (ty == Type::LabelTyID) ||
+ (ty == Type::FunctionTyID) || (ty == Type::PointerTyID) )
+ res = IntRegClassID; // sparc int reg (ty=0: void)
+ else if (ty <= Type::DoubleTyID)
+ res = FloatRegClassID; // sparc float reg class
+ else {
+ //std::cerr << "TypeID: " << ty << "\n";
+ assert(0 && "Cannot resolve register class for type");
+ return 0;
+ }
+
+ if(isCCReg)
+ return res + 2; // corresponidng condition code regiser
+ else
+ return res;
+}
+
+// To find the register class to which a specified register belongs
+//
+unsigned UltraSparcRegInfo::getRegClassIDOfReg(int unifiedRegNum) const {
+ unsigned classId = 0;
+ (void) getClassRegNum(unifiedRegNum, classId);
+ return classId;
+}
+
+unsigned UltraSparcRegInfo::getRegClassIDOfRegType(int regType) const {
+ switch(regType) {
+ case IntRegType: return IntRegClassID;
+ case FPSingleRegType:
+ case FPDoubleRegType: return FloatRegClassID;
+ case IntCCRegType: return IntCCRegClassID;
+ case FloatCCRegType: return FloatCCRegClassID;
+ default:
+ assert(0 && "Invalid register type in getRegClassIDOfRegType");
+ return 0;
+ }
+}
+
//---------------------------------------------------------------------------
// Suggests a register for the ret address in the RET machine instruction.
// We always suggest %i7 by convention.
//---------------------------------------------------------------------------
-void UltraSparcRegInfo::suggestReg4RetAddr(const MachineInstr *RetMI,
+void UltraSparcRegInfo::suggestReg4RetAddr(MachineInstr *RetMI,
LiveRangeInfo& LRI) const {
- assert( (RetMI->getNumOperands() >= 2)
- && "JMPL/RETURN must have 3 and 2 operands respectively");
+ assert(target.getInstrInfo().isReturn(RetMI->getOpCode()));
- MachineOperand & MO = ( MachineOperand &) RetMI->getOperand(0);
-
- // return address is always mapped to i7
- //
- MO.setRegForValue( getUnifiedRegNum( IntRegClassID, SparcIntRegOrder::i7) );
+ // return address is always mapped to i7 so set it immediately
+ RetMI->SetRegForOperand(0, getUnifiedRegNum(IntRegClassID,
+ SparcIntRegClass::i7));
// Possible Optimization:
// Instead of setting the color, we can suggest one. In that case,
// In that case, a LR has to be created at the start of method.
// It has to be done as follows (remove the setRegVal above):
+ // MachineOperand & MO = RetMI->getOperand(0);
// const Value *RetAddrVal = MO.getVRegValue();
// assert( RetAddrVal && "LR for ret address must be created at start");
// LiveRange * RetAddrLR = LRI.getLiveRangeForValue( RetAddrVal);
// RetAddrLR->setSuggestedColor(getUnifiedRegNum( IntRegClassID,
- // SparcIntRegOrdr::i7) );
+ // SparcIntRegOrdr::i7) );
}
// Suggests a register for the ret address in the JMPL/CALL machine instr.
// Sparc ABI dictates that %o7 be used for this purpose.
//---------------------------------------------------------------------------
-void UltraSparcRegInfo::suggestReg4CallAddr(const MachineInstr * CallMI,
- LiveRangeInfo& LRI,
- std::vector<RegClass *> RCList) const {
+void
+UltraSparcRegInfo::suggestReg4CallAddr(MachineInstr * CallMI,
+ LiveRangeInfo& LRI) const
+{
CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
const Value *RetAddrVal = argDesc->getReturnAddrReg();
- assert(RetAddrVal && "Return address value is required");
-
- // create a new LR for the return address and color it
- LiveRange * RetAddrLR = new LiveRange();
- RetAddrLR->insert( RetAddrVal );
- unsigned RegClassID = getRegClassIDOfValue( RetAddrVal );
- RetAddrLR->setRegClass( RCList[RegClassID] );
- RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID,SparcIntRegOrder::o7));
- LRI.addLRToMap( RetAddrVal, RetAddrLR);
-
-}
+ assert(RetAddrVal && "INTERNAL ERROR: Return address value is required");
+
+ // A LR must already exist for the return address.
+ LiveRange *RetAddrLR = LRI.getLiveRangeForValue(RetAddrVal);
+ assert(RetAddrLR && "INTERNAL ERROR: No LR for return address of call!");
+ unsigned RegClassID = RetAddrLR->getRegClass()->getID();
+ RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID, SparcIntRegClass::o7));
+}
regClassIDOfArgReg == IntRegClassID &&
"This should only be an Int register for an FP argument");
- int TmpOff = MachineCodeForMethod::get(Meth).pushTempValue(target,
+ int TmpOff = MachineFunction::get(Meth).pushTempValue(target,
getSpilledRegSize(regType));
- cpReg2MemMI(UniArgReg, getFramePointer(), TmpOff, IntRegType,
- FirstAI->InstrnsBefore);
+ cpReg2MemMI(FirstAI->InstrnsBefore,
+ UniArgReg, getFramePointer(), TmpOff, IntRegType);
- cpMem2RegMI(getFramePointer(), TmpOff, UniLRReg, regType,
- FirstAI->InstrnsBefore);
+ cpMem2RegMI(FirstAI->InstrnsBefore,
+ getFramePointer(), TmpOff, UniLRReg, regType);
}
else {
- cpReg2RegMI(UniArgReg, UniLRReg, regType, FirstAI->InstrnsBefore);
+ cpReg2RegMI(FirstAI->InstrnsBefore, UniArgReg, UniLRReg, regType);
}
}
else {
//
const MachineFrameInfo& frameInfo = target.getFrameInfo();
int offsetFromFP =
- frameInfo.getIncomingArgOffset(MachineCodeForMethod::get(Meth),
+ frameInfo.getIncomingArgOffset(MachineFunction::get(Meth),
argNo);
- cpMem2RegMI(getFramePointer(), offsetFromFP, UniLRReg, regType,
- FirstAI->InstrnsBefore);
+ cpMem2RegMI(FirstAI->InstrnsBefore,
+ getFramePointer(), offsetFromFP, UniLRReg, regType);
}
} // if LR received a color
assert(isVarArgs && regClassIDOfArgReg == IntRegClassID &&
"This should only be an Int register for an FP argument");
- cpReg2MemMI(UniArgReg, getFramePointer(), LR->getSpillOffFromFP(),
- IntRegType, FirstAI->InstrnsBefore);
+ cpReg2MemMI(FirstAI->InstrnsBefore, UniArgReg,
+ getFramePointer(), LR->getSpillOffFromFP(), IntRegType);
}
else {
- cpReg2MemMI(UniArgReg, getFramePointer(), LR->getSpillOffFromFP(),
- regType, FirstAI->InstrnsBefore);
+ cpReg2MemMI(FirstAI->InstrnsBefore, UniArgReg,
+ getFramePointer(), LR->getSpillOffFromFP(), regType);
}
}
const MachineFrameInfo& frameInfo = target.getFrameInfo();
int offsetFromFP =
- frameInfo.getIncomingArgOffset(MachineCodeForMethod::get(Meth),
+ frameInfo.getIncomingArgOffset(MachineFunction::get(Meth),
argNo);
LR->modifySpillOffFromFP( offsetFromFP );
// This method is called before graph coloring to suggest colors to the
// outgoing call args and the return value of the call.
//---------------------------------------------------------------------------
-void UltraSparcRegInfo::suggestRegs4CallArgs(const MachineInstr *CallMI,
- LiveRangeInfo& LRI,
- std::vector<RegClass *> RCList) const {
- assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
+void UltraSparcRegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
+ LiveRangeInfo& LRI) const {
+ assert ( (target.getInstrInfo()).isCall(CallMI->getOpCode()) );
CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
- suggestReg4CallAddr(CallMI, LRI, RCList);
-
- // First color the return value of the call instruction. The return value
- // will be in %o0 if the value is an integer type, or in %f0 if the
- // value is a float type.
-
- // the return value cannot have a LR in machine instruction since it is
- // only defined by the call instruction
+ suggestReg4CallAddr(CallMI, LRI);
- // if type is not void, create a new live range and set its
- // register class and add to LRI
+ // First color the return value of the call instruction, if any.
+ // The return value will be in %o0 if the value is an integer type,
+ // or in %f0 if the value is a float type.
+ //
+ if (const Value *RetVal = argDesc->getReturnValue()) {
+ LiveRange *RetValLR = LRI.getLiveRangeForValue(RetVal);
+ assert(RetValLR && "No LR for return Value of call!");
- const Value *RetVal = argDesc->getReturnValue();
+ unsigned RegClassID = RetValLR->getRegClass()->getID();
- if (RetVal) {
- assert ((!LRI.getLiveRangeForValue(RetVal)) &&
- "LR for ret Value of call already definded!");
-
- // create a new LR for the return value
- LiveRange *RetValLR = new LiveRange();
- RetValLR->insert(RetVal);
- unsigned RegClassID = getRegClassIDOfValue(RetVal);
- RetValLR->setRegClass(RCList[RegClassID]);
- LRI.addLRToMap(RetVal, RetValLR);
-
// now suggest a register depending on the register class of ret arg
-
if( RegClassID == IntRegClassID )
- RetValLR->setSuggestedColor(SparcIntRegOrder::o0);
+ RetValLR->setSuggestedColor(SparcIntRegClass::o0);
else if (RegClassID == FloatRegClassID )
- RetValLR->setSuggestedColor(SparcFloatRegOrder::f0 );
+ RetValLR->setSuggestedColor(SparcFloatRegClass::f0 );
else assert( 0 && "Unknown reg class for return value of call\n");
}
-
// Now suggest colors for arguments (operands) of the call instruction.
// Colors are suggested only if the arg number is smaller than the
// the number of registers allocated for argument passing.
// get the LR of call operand (parameter)
LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
-
- // not possible to have a null LR since all args (even consts)
- // must be defined before
- if (!LR) {
- cerr << " ERROR: In call instr, no LR for arg: " << RAV(CallArg) << "\n";
- assert(0 && "NO LR for call arg");
- }
-
+ assert (LR && "Must have a LR for all arguments since "
+ "all args (even consts) must be defined before");
+
unsigned regType = getRegType( LR );
unsigned regClassIDOfArgReg = MAXINT; // reg class of chosen reg (unused)
-
+
// Choose a register for this arg depending on whether it is
// an INT or FP value. Here we ignore whether or not it is a
// varargs calls, because FP arguments will be explicitly copied
const Value *argCopy = argDesc->getArgInfo(i).getArgCopy();
if (argCopy != NULL)
{
- assert(regType != IntRegType && argCopy->getType()->isIntegral()
+ assert(regType != IntRegType && argCopy->getType()->isInteger()
&& "Must be passing copy of FP argument in int register");
int copyRegNum = regNumForIntArg(/*inCallee*/false, /*isVarArgs*/false,
argNo, intArgNo, fpArgNo-1,
//---------------------------------------------------------------------------
void
-UltraSparcRegInfo::InitializeOutgoingArg(const MachineInstr* CallMI,
+UltraSparcRegInfo::InitializeOutgoingArg(MachineInstr* CallMI,
AddedInstrns *CallAI,
PhyRegAlloc &PRA, LiveRange* LR,
unsigned regType, unsigned RegClassID,
{
isArgInReg = true;
UniArgReg = (unsigned) UniArgRegOrNone;
+ CallMI->insertUsedReg(UniArgReg); // mark the reg as used
}
if (LR->hasColor()) {
//
if( isArgInReg ) {
// Copy UniLRReg to UniArgReg
- cpReg2RegMI(UniLRReg, UniArgReg, regType, AddedInstrnsBefore);
+ cpReg2RegMI(AddedInstrnsBefore, UniLRReg, UniArgReg, regType);
}
else {
// Copy UniLRReg to the stack to pass the arg on stack.
const MachineFrameInfo& frameInfo = target.getFrameInfo();
int argOffset = frameInfo.getOutgoingArgOffset(PRA.mcInfo, argNo);
- cpReg2MemMI(UniLRReg, getStackPointer(), argOffset, regType,
- CallAI->InstrnsBefore);
+ cpReg2MemMI(CallAI->InstrnsBefore,
+ UniLRReg, getStackPointer(), argOffset, regType);
}
} else { // LR is not colored (i.e., spilled)
if( isArgInReg ) {
// Insert a load instruction to load the LR to UniArgReg
- cpMem2RegMI(getFramePointer(), LR->getSpillOffFromFP(),
- UniArgReg, regType, AddedInstrnsBefore);
+ cpMem2RegMI(AddedInstrnsBefore, getFramePointer(),
+ LR->getSpillOffFromFP(), UniArgReg, regType);
// Now add the instruction
}
//
// NOTE: We directly add to CallAI->InstrnsBefore instead of adding to
// AddedInstrnsBefore since these instructions must not be reordered.
- cpReg2MemMI(TReg, getFramePointer(), TmpOff, regType,
- CallAI->InstrnsBefore);
- cpMem2RegMI(getFramePointer(), LR->getSpillOffFromFP(), TReg, regType,
- CallAI->InstrnsBefore);
- cpReg2MemMI(TReg, getStackPointer(), argOffset, regType,
- CallAI->InstrnsBefore);
- cpMem2RegMI(getFramePointer(), TmpOff, TReg, regType,
- CallAI->InstrnsBefore);
+ cpReg2MemMI(CallAI->InstrnsBefore,
+ TReg, getFramePointer(), TmpOff, regType);
+ cpMem2RegMI(CallAI->InstrnsBefore,
+ getFramePointer(), LR->getSpillOffFromFP(), TReg, regType);
+ cpReg2MemMI(CallAI->InstrnsBefore,
+ TReg, getStackPointer(), argOffset, regType);
+ cpMem2RegMI(CallAI->InstrnsBefore,
+ getFramePointer(), TmpOff, TReg, regType);
}
}
}
// to instert copy instructions.
//---------------------------------------------------------------------------
-void UltraSparcRegInfo::colorCallArgs(const MachineInstr *CallMI,
+void UltraSparcRegInfo::colorCallArgs(MachineInstr *CallMI,
LiveRangeInfo &LRI,
AddedInstrns *CallAI,
PhyRegAlloc &PRA,
const BasicBlock *BB) const {
- assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
+ assert ( (target.getInstrInfo()).isCall(CallMI->getOpCode()) );
CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
}
unsigned RegClassID = (RetValLR->getRegClass())->getID();
- bool recvCorrectColor = false;
-
+ bool recvCorrectColor;
unsigned CorrectCol; // correct color for ret value
+ unsigned UniRetReg; // unified number for CorrectCol
+
if(RegClassID == IntRegClassID)
- CorrectCol = SparcIntRegOrder::o0;
+ CorrectCol = SparcIntRegClass::o0;
else if(RegClassID == FloatRegClassID)
- CorrectCol = SparcFloatRegOrder::f0;
+ CorrectCol = SparcFloatRegClass::f0;
else {
assert( 0 && "Unknown RegClass");
return;
}
+
+ // convert to unified number
+ UniRetReg = getUnifiedRegNum(RegClassID, CorrectCol);
+ // Mark the register as used by this instruction
+ CallMI->insertUsedReg(UniRetReg);
+
// if the LR received the correct color, NOTHING to do
-
- if( RetValLR->hasColor() )
- if( RetValLR->getColor() == CorrectCol )
- recvCorrectColor = true;
-
-
+ recvCorrectColor = RetValLR->hasColor()? RetValLR->getColor() == CorrectCol
+ : false;
+
// if we didn't receive the correct color for some reason,
// put copy instruction
-
if( !recvCorrectColor ) {
-
+
unsigned regType = getRegType( RetValLR );
- // the reg that LR must be colored with
- unsigned UniRetReg = getUnifiedRegNum( RegClassID, CorrectCol);
-
if( RetValLR->hasColor() ) {
- unsigned
- UniRetLRReg=getUnifiedRegNum(RegClassID,RetValLR->getColor());
+ unsigned UniRetLRReg=getUnifiedRegNum(RegClassID,RetValLR->getColor());
// the return value is coming in UniRetReg but has to go into
// the UniRetLRReg
- cpReg2RegMI(UniRetReg, UniRetLRReg, regType, CallAI->InstrnsAfter);
+ cpReg2RegMI(CallAI->InstrnsAfter, UniRetReg, UniRetLRReg, regType);
} // if LR has color
else {
// if the LR did NOT receive a color, we have to move the return
// value coming in UniRetReg to the stack pos of spilled LR
- cpReg2MemMI(UniRetReg, getFramePointer(),RetValLR->getSpillOffFromFP(),
- regType, CallAI->InstrnsAfter);
+ cpReg2MemMI(CallAI->InstrnsAfter, UniRetReg,
+ getFramePointer(),RetValLR->getSpillOffFromFP(), regType);
}
} // the LR didn't receive the suggested color
// Repeat for the second copy of the argument, which would be
// an FP argument being passed to a function with no prototype.
+ // It may either be passed as a copy in an integer register
+ // (in argCopy), or on the stack (useStackSlot).
const Value *argCopy = argDesc->getArgInfo(i).getArgCopy();
if (argCopy != NULL)
{
- assert(regType != IntRegType && argCopy->getType()->isIntegral()
+ assert(regType != IntRegType && argCopy->getType()->isInteger()
&& "Must be passing copy of FP argument in int register");
unsigned copyRegClassID = getRegClassIDOfValue(argCopy);
copyRegClassID, copyRegNum, argNo,
AddedInstrnsBefore);
}
+
+ if (regNum != InvalidRegNum &&
+ argDesc->getArgInfo(i).usesStackSlot())
+ {
+ // Pass the argument via the stack in addition to regNum
+ assert(regType != IntRegType && "Passing an integer arg. twice?");
+ assert(!argCopy && "Passing FP arg in FP reg, INT reg, and stack?");
+ InitializeOutgoingArg(CallMI, CallAI, PRA, LR, regType, RegClassID,
+ InvalidRegNum, argNo, AddedInstrnsBefore);
+ }
} // for each parameter in call instruction
// If we added any instruction before the call instruction, verify
// that they are in the proper order and if not, reorder them
//
+ std::vector<MachineInstr *> ReorderedVec;
if (!AddedInstrnsBefore.empty()) {
if (DEBUG_RA) {
cerr << *(AddedInstrnsBefore[i]);
}
- std::vector<MachineInstr *> TmpVec;
- OrderAddedInstrns(AddedInstrnsBefore, TmpVec, PRA);
-
+ OrderAddedInstrns(AddedInstrnsBefore, ReorderedVec, PRA);
+ assert(ReorderedVec.size() >= AddedInstrnsBefore.size()
+ && "Dropped some instructions when reordering!");
+
if (DEBUG_RA) {
cerr << "\nAfter reordering instrns: \n";
- for(unsigned i = 0; i < TmpVec.size(); i++)
- cerr << *TmpVec[i];
+ for(unsigned i = 0; i < ReorderedVec.size(); i++)
+ cerr << *ReorderedVec[i];
}
-
- // copy the results back from TmpVec to InstrnsBefore
- for(unsigned i=0; i < TmpVec.size(); i++)
- CallAI->InstrnsBefore.push_back( TmpVec[i] );
}
- // now insert caller saving code for this call instruction
+ // Now insert caller saving code for this call instruction
//
- insertCallerSavingCode(CallMI, BB, PRA);
+ insertCallerSavingCode(CallAI->InstrnsBefore, CallAI->InstrnsAfter,
+ CallMI, BB, PRA);
+
+ // Then insert the final reordered code for the call arguments.
+ //
+ for(unsigned i=0; i < ReorderedVec.size(); i++)
+ CallAI->InstrnsBefore.push_back( ReorderedVec[i] );
}
//---------------------------------------------------------------------------
// This method is called for an LLVM return instruction to identify which
// values will be returned from this method and to suggest colors.
//---------------------------------------------------------------------------
-void UltraSparcRegInfo::suggestReg4RetValue(const MachineInstr *RetMI,
+void UltraSparcRegInfo::suggestReg4RetValue(MachineInstr *RetMI,
LiveRangeInfo &LRI) const {
- assert( (UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode() ) );
+ assert( (target.getInstrInfo()).isReturn( RetMI->getOpCode() ) );
- suggestReg4RetAddr(RetMI, LRI);
+ suggestReg4RetAddr(RetMI, LRI);
// if there is an implicit ref, that has to be the ret value
if( RetMI->getNumImplicitRefs() > 0 ) {
unsigned RegClassID = (LR->getRegClass())->getID();
if (RegClassID == IntRegClassID)
- LR->setSuggestedColor(SparcIntRegOrder::i0);
+ LR->setSuggestedColor(SparcIntRegClass::i0);
else if (RegClassID == FloatRegClassID)
- LR->setSuggestedColor(SparcFloatRegOrder::f0);
+ LR->setSuggestedColor(SparcFloatRegClass::f0);
}
}
// the LR to %i0 or %f0. When the LR is spilled, instead of the copy, we
// have to put a load instruction.
//---------------------------------------------------------------------------
-void UltraSparcRegInfo::colorRetValue(const MachineInstr *RetMI,
+void UltraSparcRegInfo::colorRetValue(MachineInstr *RetMI,
LiveRangeInfo &LRI,
AddedInstrns *RetAI) const {
- assert((UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode()));
+ assert((target.getInstrInfo()).isReturn( RetMI->getOpCode()));
// if there is an implicit ref, that has to be the ret value
if(RetMI->getNumImplicitRefs() > 0) {
unsigned CorrectCol;
if(RegClassID == IntRegClassID)
- CorrectCol = SparcIntRegOrder::i0;
+ CorrectCol = SparcIntRegClass::i0;
else if(RegClassID == FloatRegClassID)
- CorrectCol = SparcFloatRegOrder::f0;
+ CorrectCol = SparcFloatRegClass::f0;
else {
assert (0 && "Unknown RegClass");
return;
}
- // if the LR received the correct color, NOTHING to do
+ // convert to unified number
+ unsigned UniRetReg = getUnifiedRegNum(RegClassID, CorrectCol);
+ // Mark the register as used by this instruction
+ RetMI->insertUsedReg(UniRetReg);
+
+ // if the LR received the correct color, NOTHING to do
+
if (LR->hasColor() && LR->getColor() == CorrectCol)
return;
-
- unsigned UniRetReg = getUnifiedRegNum(RegClassID, CorrectCol);
-
+
if (LR->hasColor()) {
// We are here because the LR was allocted a regiter
// the LR received UniLRReg but must be colored with UniRetReg
// to pass as the return value
- cpReg2RegMI(UniLRReg, UniRetReg, regType, RetAI->InstrnsBefore);
+ cpReg2RegMI(RetAI->InstrnsBefore, UniLRReg, UniRetReg, regType);
}
else { // if the LR is spilled
- cpMem2RegMI(getFramePointer(), LR->getSpillOffFromFP(),
- UniRetReg, regType, RetAI->InstrnsBefore);
+ cpMem2RegMI(RetAI->InstrnsBefore, getFramePointer(),
+ LR->getSpillOffFromFP(), UniRetReg, regType);
cerr << "\nCopied the return value from stack\n";
}
}
+//---------------------------------------------------------------------------
+// Check if a specified register type needs a scratch register to be
+// copied to/from memory. If it does, the reg. type that must be used
+// for scratch registers is returned in scratchRegType.
+//
+// Only the int CC register needs such a scratch register.
+// The FP CC registers can (and must) be copied directly to/from memory.
+//---------------------------------------------------------------------------
+
+bool
+UltraSparcRegInfo::regTypeNeedsScratchReg(int RegType,
+ int& scratchRegType) const
+{
+ if (RegType == IntCCRegType)
+ {
+ scratchRegType = IntRegType;
+ return true;
+ }
+ return false;
+}
//---------------------------------------------------------------------------
// Copy from a register to register. Register number must be the unified
-// register number
+// register number.
//---------------------------------------------------------------------------
void
-UltraSparcRegInfo::cpReg2RegMI(unsigned SrcReg,
+UltraSparcRegInfo::cpReg2RegMI(vector<MachineInstr*>& mvec,
+ unsigned SrcReg,
unsigned DestReg,
- int RegType,
- vector<MachineInstr*>& mvec) const {
+ int RegType) const {
assert( ((int)SrcReg != InvalidRegNum) && ((int)DestReg != InvalidRegNum) &&
"Invalid Register");
switch( RegType ) {
case IntCCRegType:
+ if (getRegType(DestReg) == IntRegType)
+ { // copy intCC reg to int reg
+ // Use SrcReg+1 to get the name "%ccr" instead of "%xcc" for RDCCR
+ MI = Create2OperandInstr_Reg(RDCCR, SrcReg+1, DestReg);
+ }
+ else
+ { // copy int reg to intCC reg
+ // Use DestReg+1 to get the name "%ccr" instead of "%xcc" for WRCCR
+ assert(getRegType(SrcReg) == IntRegType
+ && "Can only copy CC reg to/from integer reg");
+ MI = Create2OperandInstr_Reg(WRCCR, SrcReg, DestReg+1);
+ }
+ break;
+
case FloatCCRegType:
- assert(0 && "This code was bogus and needs to be fixed!");
+ assert(0 && "Cannot copy FPCC register to any other register");
break;
case IntRegType:
- MI = new MachineInstr(ADD, 3);
- MI->SetMachineOperandReg(0, SrcReg, false);
- MI->SetMachineOperandReg(1, this->getZeroRegNum(), false);
- MI->SetMachineOperandReg(2, DestReg, true);
+ MI = Create3OperandInstr_Reg(ADD, SrcReg, getZeroRegNum(), DestReg);
break;
case FPSingleRegType:
- MI = new MachineInstr(FMOVS, 2);
- MI->SetMachineOperandReg(0, SrcReg, false);
- MI->SetMachineOperandReg(1, DestReg, true);
+ MI = Create2OperandInstr_Reg(FMOVS, SrcReg, DestReg);
break;
case FPDoubleRegType:
- MI = new MachineInstr(FMOVD, 2);
- MI->SetMachineOperandReg(0, SrcReg, false);
- MI->SetMachineOperandReg(1, DestReg, true);
+ MI = Create2OperandInstr_Reg(FMOVD, SrcReg, DestReg);
break;
default:
assert(0 && "Unknown RegType");
+ break;
}
if (MI)
void
-UltraSparcRegInfo::cpReg2MemMI(unsigned SrcReg,
+UltraSparcRegInfo::cpReg2MemMI(vector<MachineInstr*>& mvec,
+ unsigned SrcReg,
unsigned DestPtrReg,
int Offset, int RegType,
- vector<MachineInstr*>& mvec) const {
+ int scratchReg) const {
MachineInstr * MI = NULL;
switch( RegType ) {
case IntRegType:
- case FloatCCRegType:
+ assert(target.getInstrInfo().constantFitsInImmedField(STX, Offset));
MI = new MachineInstr(STX, 3);
MI->SetMachineOperandReg(0, SrcReg, false);
MI->SetMachineOperandReg(1, DestPtrReg, false);
MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset);
+ mvec.push_back(MI);
break;
case FPSingleRegType:
+ assert(target.getInstrInfo().constantFitsInImmedField(ST, Offset));
MI = new MachineInstr(ST, 3);
MI->SetMachineOperandReg(0, SrcReg, false);
MI->SetMachineOperandReg(1, DestPtrReg, false);
MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset);
+ mvec.push_back(MI);
break;
case FPDoubleRegType:
+ assert(target.getInstrInfo().constantFitsInImmedField(STD, Offset));
MI = new MachineInstr(STD, 3);
MI->SetMachineOperandReg(0, SrcReg, false);
MI->SetMachineOperandReg(1, DestPtrReg, false);
MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset);
+ mvec.push_back(MI);
break;
case IntCCRegType:
- assert( 0 && "Cannot directly store %ccr to memory");
+ assert(scratchReg >= 0 && "Need scratch reg to store %ccr to memory");
+ assert(getRegType(scratchReg) ==IntRegType && "Invalid scratch reg");
+
+ // Use SrcReg+1 to get the name "%ccr" instead of "%xcc" for RDCCR
+ MI = Create2OperandInstr_Reg(RDCCR, SrcReg+1, scratchReg);
+ mvec.push_back(MI);
+
+ cpReg2MemMI(mvec, scratchReg, DestPtrReg, Offset, IntRegType);
+ break;
+
+ case FloatCCRegType:
+ assert(0 && "Tell Vikram if this assertion fails: we may have to mask out the other bits here");
+ assert(target.getInstrInfo().constantFitsInImmedField(STXFSR, Offset));
+ MI = new MachineInstr(STXFSR, 3);
+ MI->SetMachineOperandReg(0, SrcReg, false);
+ MI->SetMachineOperandReg(1, DestPtrReg, false);
+ MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
+ (int64_t) Offset);
+ mvec.push_back(MI);
+ break;
default:
assert(0 && "Unknown RegType in cpReg2MemMI");
}
-
- if (MI)
- mvec.push_back(MI);
}
void
-UltraSparcRegInfo::cpMem2RegMI(unsigned SrcPtrReg,
+UltraSparcRegInfo::cpMem2RegMI(vector<MachineInstr*>& mvec,
+ unsigned SrcPtrReg,
int Offset,
unsigned DestReg,
int RegType,
- vector<MachineInstr*>& mvec) const {
+ int scratchReg) const {
MachineInstr * MI = NULL;
switch (RegType) {
case IntRegType:
- case FloatCCRegType:
+ assert(target.getInstrInfo().constantFitsInImmedField(LDX, Offset));
MI = new MachineInstr(LDX, 3);
MI->SetMachineOperandReg(0, SrcPtrReg, false);
MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset);
MI->SetMachineOperandReg(2, DestReg, true);
+ mvec.push_back(MI);
break;
case FPSingleRegType:
+ assert(target.getInstrInfo().constantFitsInImmedField(LD, Offset));
MI = new MachineInstr(LD, 3);
MI->SetMachineOperandReg(0, SrcPtrReg, false);
MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset);
MI->SetMachineOperandReg(2, DestReg, true);
-
+ mvec.push_back(MI);
break;
case FPDoubleRegType:
+ assert(target.getInstrInfo().constantFitsInImmedField(LDD, Offset));
MI = new MachineInstr(LDD, 3);
MI->SetMachineOperandReg(0, SrcPtrReg, false);
MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset);
MI->SetMachineOperandReg(2, DestReg, true);
+ mvec.push_back(MI);
break;
case IntCCRegType:
- assert( 0 && "Cannot directly load into %ccr from memory");
+ assert(scratchReg >= 0 && "Need scratch reg to load %ccr from memory");
+ assert(getRegType(scratchReg) ==IntRegType && "Invalid scratch reg");
+ cpMem2RegMI(mvec, SrcPtrReg, Offset, scratchReg, IntRegType);
+
+ // Use DestReg+1 to get the name "%ccr" instead of "%xcc" for WRCCR
+ MI = Create2OperandInstr_Reg(WRCCR, scratchReg, DestReg+1);
+ mvec.push_back(MI);
+
+ break;
+
+ case FloatCCRegType:
+ assert(0 && "Tell Vikram if this assertion fails: we may have to mask out the other bits here");
+ assert(target.getInstrInfo().constantFitsInImmedField(LDXFSR, Offset));
+ MI = new MachineInstr(LDXFSR, 3);
+ MI->SetMachineOperandReg(0, SrcPtrReg, false);
+ MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
+ (int64_t) Offset);
+ MI->SetMachineOperandReg(2, DestReg, true);
+ mvec.push_back(MI);
+ break;
default:
assert(0 && "Unknown RegType in cpMem2RegMI");
}
-
- if (MI)
- mvec.push_back(MI);
}
case IntRegType:
MI = new MachineInstr(ADD, 3);
MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false);
- MI->SetMachineOperandReg(1, this->getZeroRegNum(), false);
+ MI->SetMachineOperandReg(1, getZeroRegNum(), false);
MI->SetMachineOperandVal(2, MachineOperand:: MO_VirtualRegister, Dest, true);
break;
//----------------------------------------------------------------------------
-void UltraSparcRegInfo::insertCallerSavingCode(const MachineInstr *CallMI,
- const BasicBlock *BB,
- PhyRegAlloc &PRA) const {
-
- assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
+void
+UltraSparcRegInfo::insertCallerSavingCode(vector<MachineInstr*>& instrnsBefore,
+ vector<MachineInstr*>& instrnsAfter,
+ MachineInstr *CallMI,
+ const BasicBlock *BB,
+ PhyRegAlloc &PRA) const
+{
+ assert ( (target.getInstrInfo()).isCall(CallMI->getOpCode()) );
// has set to record which registers were saved/restored
//
- std::hash_set<unsigned> PushedRegSet;
+ hash_set<unsigned> PushedRegSet;
CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
RetValLR->getColor() ) );
}
-
const ValueSet &LVSetAft = PRA.LVI->getLiveVarSetAfterMInst(CallMI, BB);
ValueSet::const_iterator LIt = LVSetAft.begin();
// if the value is in both LV sets (i.e., live before and after
// the call machine instruction)
-
+
unsigned Reg = getUnifiedRegNum(RCID, Color);
if( PushedRegSet.find(Reg) == PushedRegSet.end() ) {
// Now get two instructions - to push on stack and pop from stack
// and add them to InstrnsBefore and InstrnsAfter of the
// call instruction
-
-
+ //
int StackOff = PRA.mcInfo.pushTempValue(target,
getSpilledRegSize(RegType));
-
- MachineInstr *AdIBefCC=NULL, *AdIAftCC=NULL, *AdICpCC;
- MachineInstr *AdIBef=NULL, *AdIAft=NULL;
-
+ vector<MachineInstr*> AdIBef, AdIAft;
+
//---- Insert code for pushing the reg on stack ----------
-
- if( RegType == IntCCRegType ) {
-
- // Handle IntCCRegType specially since we cannot directly
- // push %ccr on to the stack
-
- const ValueSet &LVSetBef =
- PRA.LVI->getLiveVarSetBeforeMInst(CallMI, BB);
-
- // get a free INTEGER register
- int FreeIntReg =
- PRA.getUsableUniRegAtMI(PRA.getRegClassByID(IntRegClassID) /*LR->getRegClass()*/,
- IntRegType, CallMI, &LVSetBef, AdIBefCC, AdIAftCC);
-
- // insert the instructions in reverse order since we are
- // adding them to the front of InstrnsBefore
- AddedInstrns& addedI = PRA.AddedInstrMap[CallMI];
- if(AdIAftCC)
- addedI.InstrnsBefore.insert(addedI.InstrnsBefore.begin(),
- AdIAftCC);
-
- AdICpCC = cpCCR2IntMI(FreeIntReg);
- addedI.InstrnsBefore.insert(addedI.InstrnsBefore.begin(),
- AdICpCC);
-
- if(AdIBefCC)
- addedI.InstrnsBefore.insert(addedI.InstrnsBefore.begin(),
- AdIBefCC);
-
- if(DEBUG_RA) {
- cerr << "\n!! Inserted caller saving (push) inst for %ccr:";
- if(AdIBefCC) cerr << "\t" << *(AdIBefCC);
- cerr << "\t" << *AdICpCC;
- if(AdIAftCC) cerr << "\t" << *(AdIAftCC);
- }
-
- } else {
- // for any other register type, just add the push inst
- cpReg2MemMI(Reg, getFramePointer(), StackOff, RegType,
- PRA.AddedInstrMap[CallMI].InstrnsBefore);
- }
-
-
+
+ // We may need a scratch register to copy the saved value
+ // to/from memory. This may itself have to insert code to
+ // free up a scratch register. Any such code should go before
+ // the save code.
+ int scratchRegType = -1;
+ int scratchReg = -1;
+ if (regTypeNeedsScratchReg(RegType, scratchRegType))
+ { // Find a register not live in the LVSet before CallMI
+ const ValueSet &LVSetBef =
+ PRA.LVI->getLiveVarSetBeforeMInst(CallMI, BB);
+ scratchReg = PRA.getUsableUniRegAtMI(scratchRegType, &LVSetBef,
+ CallMI, AdIBef, AdIAft);
+ assert(scratchReg != getInvalidRegNum());
+ CallMI->insertUsedReg(scratchReg);
+ }
+
+ if (AdIBef.size() > 0)
+ instrnsBefore.insert(instrnsBefore.end(),
+ AdIBef.begin(), AdIBef.end());
+
+ cpReg2MemMI(instrnsBefore, Reg,getFramePointer(),StackOff,RegType,
+ scratchReg);
+
+ if (AdIAft.size() > 0)
+ instrnsBefore.insert(instrnsBefore.end(),
+ AdIAft.begin(), AdIAft.end());
+
//---- Insert code for popping the reg from the stack ----------
- if (RegType == IntCCRegType) {
-
- // Handle IntCCRegType specially since we cannot directly
- // pop %ccr on from the stack
-
- // get a free INT register
- int FreeIntReg =
- PRA.getUsableUniRegAtMI(PRA.getRegClassByID(IntRegClassID) /* LR->getRegClass()*/,
- IntRegType, CallMI, &LVSetAft, AdIBefCC, AdIAftCC);
-
- if(AdIBefCC)
- PRA.AddedInstrMap[CallMI].InstrnsAfter.push_back(AdIBefCC);
-
- AdICpCC = cpInt2CCRMI(FreeIntReg);
- PRA.AddedInstrMap[CallMI].InstrnsAfter.push_back(AdICpCC);
-
- if(AdIAftCC)
- PRA.AddedInstrMap[CallMI].InstrnsAfter.push_back(AdIAftCC);
-
- if(DEBUG_RA) {
-
- cerr << "\n!! Inserted caller saving (pop) inst for %ccr:";
- if(AdIBefCC) cerr << "\t" << *(AdIBefCC);
- cerr << "\t" << *AdICpCC;
- if(AdIAftCC) cerr << "\t" << *(AdIAftCC);
- }
-
- } else {
- // for any other register type, just add the pop inst
- cpMem2RegMI(getFramePointer(), StackOff, Reg, RegType,
- PRA.AddedInstrMap[CallMI].InstrnsAfter);
- }
+ // We may need a scratch register to copy the saved value
+ // from memory. This may itself have to insert code to
+ // free up a scratch register. Any such code should go
+ // after the save code.
+ //
+ scratchRegType = -1;
+ scratchReg = -1;
+ if (regTypeNeedsScratchReg(RegType, scratchRegType))
+ { // Find a register not live in the LVSet after CallMI
+ scratchReg = PRA.getUsableUniRegAtMI(scratchRegType, &LVSetAft,
+ CallMI, AdIBef, AdIAft);
+ assert(scratchReg != getInvalidRegNum());
+ CallMI->insertUsedReg(scratchReg);
+ }
+
+ if (AdIBef.size() > 0)
+ instrnsAfter.insert(instrnsAfter.end(),
+ AdIBef.begin(), AdIBef.end());
+
+ cpMem2RegMI(instrnsAfter, getFramePointer(), StackOff,Reg,RegType,
+ scratchReg);
+
+ if (AdIAft.size() > 0)
+ instrnsAfter.insert(instrnsAfter.end(),
+ AdIAft.begin(), AdIAft.end());
PushedRegSet.insert(Reg);
-
+
if(DEBUG_RA) {
cerr << "\nFor call inst:" << *CallMI;
- cerr << " -inserted caller saving instrs:\n\t ";
- if( RegType == IntCCRegType ) {
- if(AdIBefCC) cerr << *AdIBefCC << "\t";
- if(AdIAftCC) cerr << *AdIAftCC;
- }
- else {
- if(AdIBef) cerr << *AdIBef << "\t";
- if(AdIAft) cerr << *AdIAft;
- }
+ cerr << " -inserted caller saving instrs: Before:\n\t ";
+ for_each(instrnsBefore.begin(), instrnsBefore.end(),
+ std::mem_fun(&MachineInstr::dump));
+ cerr << " -and After:\n\t ";
+ for_each(instrnsAfter.begin(), instrnsAfter.end(),
+ std::mem_fun(&MachineInstr::dump));
}
} // if not already pushed
} // if there is a LR for Var
} // for each value in the LV set after instruction
-
}
-//---------------------------------------------------------------------------
-// Copies %ccr into an integer register. IntReg is the UNIFIED register
-// number.
-//---------------------------------------------------------------------------
-
-MachineInstr * UltraSparcRegInfo::cpCCR2IntMI(unsigned IntReg) const {
- MachineInstr * MI = new MachineInstr(RDCCR, 2);
- MI->SetMachineOperandReg(0, this->getUnifiedRegNum(UltraSparcRegInfo::IntCCRegClassID,
- SparcIntCCRegOrder::ccr),
- false, true);
- MI->SetMachineOperandReg(1, IntReg, true);
- return MI;
-}
-
-//---------------------------------------------------------------------------
-// Copies an integer register into %ccr. IntReg is the UNIFIED register
-// number.
-//---------------------------------------------------------------------------
-
-MachineInstr *UltraSparcRegInfo::cpInt2CCRMI(unsigned IntReg) const {
- MachineInstr *MI = new MachineInstr(WRCCR, 3);
- MI->SetMachineOperandReg(0, IntReg, false);
- MI->SetMachineOperandReg(1, this->getZeroRegNum(), false);
- MI->SetMachineOperandReg(2, this->getUnifiedRegNum(UltraSparcRegInfo::IntCCRegClassID, SparcIntCCRegOrder::ccr),
- true, true);
- return MI;
-}
-
-
-
//---------------------------------------------------------------------------
// Print the register assigned to a LR
cerr << " colored with color "<< LR->getColor();
if (RegClassID == IntRegClassID) {
- cerr<< " [" << SparcIntRegOrder::getRegName(LR->getColor()) << "]\n";
+ cerr<< " [" << SparcIntRegClass::getRegName(LR->getColor()) << "]\n";
} else if (RegClassID == FloatRegClassID) {
- cerr << "[" << SparcFloatRegOrder::getRegName(LR->getColor());
+ cerr << "[" << SparcFloatRegClass::getRegName(LR->getColor());
if( LR->getType() == Type::DoubleTy)
- cerr << "+" << SparcFloatRegOrder::getRegName(LR->getColor()+1);
+ cerr << "+" << SparcFloatRegClass::getRegName(LR->getColor()+1);
cerr << "]\n";
}
}
//
// Since instructions are inserted in RegAlloc, this assumes that the
// first operand is the source reg and the last operand is the dest reg.
+// It also does not consider operands that are both use and def.
//
// All the uses are before THE def to a register
//---------------------------------------------------------------------------
// last operand is the def (unless for a store which has no def reg)
MachineOperand& DefOp = DefInst->getOperand(DefInst->getNumOperands()-1);
- if( DefOp.opIsDef() &&
- DefOp.getOperandType() == MachineOperand::MO_MachineRegister) {
+ if (DefOp.opIsDef() &&
+ DefOp.getType() == MachineOperand::MO_MachineRegister) {
// If the operand in DefInst is a def ...
-
bool DefEqUse = false;
std::vector<MachineInstr *>::iterator UseIt = DefIt;
// for each inst (UseInst) that is below the DefInst do ...
MachineOperand& UseOp = UseInst->getOperand(0);
- if( ! UseOp.opIsDef() &&
- UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
+ if (!UseOp.opIsDef() &&
+ UseOp.getType() == MachineOperand::MO_MachineRegister) {
// if use is a register ...
PhyRegAlloc &PRA) const {
MachineOperand& UseOp = UnordInst->getOperand(0);
- if( ! UseOp.opIsDef() &&
- UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
+ if (!UseOp.opIsDef() &&
+ UseOp.getType() == MachineOperand::MO_MachineRegister) {
// for the use of UnordInst, see whether there is a defining instr
// before in the OrdVec
OrdInst->getOperand(OrdInst->getNumOperands()-1);
if( DefOp.opIsDef() &&
- DefOp.getOperandType() == MachineOperand::MO_MachineRegister) {
+ DefOp.getType() == MachineOperand::MO_MachineRegister) {
//cerr << "\nDefining Ord Inst: " << *OrdInst;
// Save the UReg (%ox) on stack before it's destroyed
vector<MachineInstr*> mvec;
- cpReg2MemMI(UReg, getFramePointer(), StackOff, RegType, mvec);
+ cpReg2MemMI(mvec, UReg, getFramePointer(), StackOff, RegType);
for (vector<MachineInstr*>::iterator MI=mvec.begin(); MI != mvec.end(); ++MI) {
OrdIt = OrdVec.insert(OrdIt, *MI);
++OrdIt; // OrdIt must still point to current instr we processed
assert(DOp.opIsDef() && "Last operand is not the def");
const int DReg = DOp.getMachineRegNum();
- cpMem2RegMI(getFramePointer(), StackOff, DReg, RegType, OrdVec);
+ cpMem2RegMI(OrdVec, getFramePointer(), StackOff, DReg, RegType);
- cerr << "\nFixed CIRCULAR references by reordering";
-
if( DEBUG_RA ) {
+ cerr << "\nFixed CIRCULAR references by reordering:";
cerr << "\nBefore CIRCULAR Reordering:\n";
cerr << *UnordInst;
cerr << *OrdInst;
projects / oota-llvm.git / blobdiff