#include "SparcInternals.h"
#include "SparcRegClassInfo.h"
#include "llvm/Target/Sparc.h"
-#include "llvm/CodeGen/MachineCodeForMethod.h"
+#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/PhyRegAlloc.h"
#include "llvm/CodeGen/InstrSelection.h"
#include "llvm/CodeGen/InstrSelectionSupport.h"
regClassIDOfArgReg == IntRegClassID &&
"This should only be an Int register for an FP argument");
- int TmpOff = MachineCodeForMethod::get(Meth).pushTempValue(target,
+ int TmpOff = MachineFunction::get(Meth).pushTempValue(target,
getSpilledRegSize(regType));
cpReg2MemMI(FirstAI->InstrnsBefore,
UniArgReg, getFramePointer(), TmpOff, IntRegType);
//
const MachineFrameInfo& frameInfo = target.getFrameInfo();
int offsetFromFP =
- frameInfo.getIncomingArgOffset(MachineCodeForMethod::get(Meth),
+ frameInfo.getIncomingArgOffset(MachineFunction::get(Meth),
argNo);
cpMem2RegMI(FirstAI->InstrnsBefore,
const MachineFrameInfo& frameInfo = target.getFrameInfo();
int offsetFromFP =
- frameInfo.getIncomingArgOffset(MachineCodeForMethod::get(Meth),
+ frameInfo.getIncomingArgOffset(MachineFunction::get(Meth),
argNo);
LR->modifySpillOffFromFP( offsetFromFP );
{
isArgInReg = true;
UniArgReg = (unsigned) UniArgRegOrNone;
- CallMI->getRegsUsed().insert(UniArgReg); // mark the reg as used
+ CallMI->insertUsedReg(UniArgReg); // mark the reg as used
}
if (LR->hasColor()) {
else {
// Copy UniLRReg to the stack to pass the arg on stack.
const MachineFrameInfo& frameInfo = target.getFrameInfo();
- int argOffset = frameInfo.getOutgoingArgOffset(PRA.mcInfo, argNo);
+ int argOffset = frameInfo.getOutgoingArgOffset(PRA.MF, argNo);
cpReg2MemMI(CallAI->InstrnsBefore,
UniLRReg, getStackPointer(), argOffset, regType);
}
// Use TmpOff to save TReg, since that may have a live value.
//
int TReg = PRA.getUniRegNotUsedByThisInst( LR->getRegClass(), CallMI );
- int TmpOff = PRA.mcInfo.pushTempValue(target,
- getSpilledRegSize(getRegType(LR)));
+ int TmpOff = PRA.MF.pushTempValue(target,
+ getSpilledRegSize(getRegType(LR)));
const MachineFrameInfo& frameInfo = target.getFrameInfo();
- int argOffset = frameInfo.getOutgoingArgOffset(PRA.mcInfo, argNo);
+ int argOffset = frameInfo.getOutgoingArgOffset(PRA.MF, argNo);
MachineInstr *Ad1, *Ad2, *Ad3, *Ad4;
UniRetReg = getUnifiedRegNum(RegClassID, CorrectCol);
// Mark the register as used by this instruction
- CallMI->getRegsUsed().insert(UniRetReg);
+ CallMI->insertUsedReg(UniRetReg);
// if the LR received the correct color, NOTHING to do
recvCorrectColor = RetValLR->hasColor()? RetValLR->getColor() == CorrectCol
unsigned UniRetReg = getUnifiedRegNum(RegClassID, CorrectCol);
// Mark the register as used by this instruction
- RetMI->getRegsUsed().insert(UniRetReg);
+ RetMI->insertUsedReg(UniRetReg);
// if the LR received the correct color, NOTHING to do
case IntRegType:
assert(target.getInstrInfo().constantFitsInImmedField(STX, Offset));
MI = new MachineInstr(STX, 3);
- MI->SetMachineOperandReg(0, SrcReg, false);
- MI->SetMachineOperandReg(1, DestPtrReg, false);
+ MI->SetMachineOperandReg(0, SrcReg);
+ MI->SetMachineOperandReg(1, DestPtrReg);
MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset);
mvec.push_back(MI);
case FPSingleRegType:
assert(target.getInstrInfo().constantFitsInImmedField(ST, Offset));
MI = new MachineInstr(ST, 3);
- MI->SetMachineOperandReg(0, SrcReg, false);
- MI->SetMachineOperandReg(1, DestPtrReg, false);
+ MI->SetMachineOperandReg(0, SrcReg);
+ MI->SetMachineOperandReg(1, DestPtrReg);
MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset);
mvec.push_back(MI);
case FPDoubleRegType:
assert(target.getInstrInfo().constantFitsInImmedField(STD, Offset));
MI = new MachineInstr(STD, 3);
- MI->SetMachineOperandReg(0, SrcReg, false);
- MI->SetMachineOperandReg(1, DestPtrReg, false);
+ MI->SetMachineOperandReg(0, SrcReg);
+ MI->SetMachineOperandReg(1, DestPtrReg);
MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset);
mvec.push_back(MI);
assert(0 && "Tell Vikram if this assertion fails: we may have to mask out the other bits here");
assert(target.getInstrInfo().constantFitsInImmedField(STXFSR, Offset));
MI = new MachineInstr(STXFSR, 3);
- MI->SetMachineOperandReg(0, SrcReg, false);
- MI->SetMachineOperandReg(1, DestPtrReg, false);
+ MI->SetMachineOperandReg(0, SrcReg);
+ MI->SetMachineOperandReg(1, DestPtrReg);
MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset);
mvec.push_back(MI);
case IntRegType:
assert(target.getInstrInfo().constantFitsInImmedField(LDX, Offset));
MI = new MachineInstr(LDX, 3);
- MI->SetMachineOperandReg(0, SrcPtrReg, false);
+ MI->SetMachineOperandReg(0, SrcPtrReg);
MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset);
MI->SetMachineOperandReg(2, DestReg, true);
case FPSingleRegType:
assert(target.getInstrInfo().constantFitsInImmedField(LD, Offset));
MI = new MachineInstr(LD, 3);
- MI->SetMachineOperandReg(0, SrcPtrReg, false);
+ MI->SetMachineOperandReg(0, SrcPtrReg);
MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset);
MI->SetMachineOperandReg(2, DestReg, true);
case FPDoubleRegType:
assert(target.getInstrInfo().constantFitsInImmedField(LDD, Offset));
MI = new MachineInstr(LDD, 3);
- MI->SetMachineOperandReg(0, SrcPtrReg, false);
+ MI->SetMachineOperandReg(0, SrcPtrReg);
MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset);
MI->SetMachineOperandReg(2, DestReg, true);
assert(0 && "Tell Vikram if this assertion fails: we may have to mask out the other bits here");
assert(target.getInstrInfo().constantFitsInImmedField(LDXFSR, Offset));
MI = new MachineInstr(LDXFSR, 3);
- MI->SetMachineOperandReg(0, SrcPtrReg, false);
+ MI->SetMachineOperandReg(0, SrcPtrReg);
MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset);
MI->SetMachineOperandReg(2, DestReg, true);
switch( RegType ) {
case IntRegType:
MI = new MachineInstr(ADD, 3);
- MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false);
- MI->SetMachineOperandReg(1, getZeroRegNum(), false);
- MI->SetMachineOperandVal(2, MachineOperand:: MO_VirtualRegister, Dest, true);
+ MI->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, Src);
+ MI->SetMachineOperandReg(1, getZeroRegNum());
+ MI->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, Dest, true);
break;
case FPSingleRegType:
MI = new MachineInstr(FMOVS, 2);
- MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false);
- MI->SetMachineOperandVal(1, MachineOperand:: MO_VirtualRegister, Dest, true);
+ MI->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, Src);
+ MI->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, Dest, true);
break;
case FPDoubleRegType:
MI = new MachineInstr(FMOVD, 2);
- MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false);
- MI->SetMachineOperandVal(1, MachineOperand:: MO_VirtualRegister, Dest, true);
+ MI->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, Src);
+ MI->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, Dest, true);
break;
default:
assert(0 && "Unknow RegType in CpValu2Value");
}
- if (MI)
- mvec.push_back(MI);
+ mvec.push_back(MI);
}
// and add them to InstrnsBefore and InstrnsAfter of the
// call instruction
//
- int StackOff = PRA.mcInfo.pushTempValue(target,
- getSpilledRegSize(RegType));
+ int StackOff = PRA.MF.pushTempValue(target,
+ getSpilledRegSize(RegType));
vector<MachineInstr*> AdIBef, AdIAft;
scratchReg = PRA.getUsableUniRegAtMI(scratchRegType, &LVSetBef,
CallMI, AdIBef, AdIAft);
assert(scratchReg != getInvalidRegNum());
- CallMI->getRegsUsed().insert(scratchReg);
+ CallMI->insertUsedReg(scratchReg);
}
if (AdIBef.size() > 0)
scratchReg = PRA.getUsableUniRegAtMI(scratchRegType, &LVSetAft,
CallMI, AdIBef, AdIAft);
assert(scratchReg != getInvalidRegNum());
- CallMI->getRegsUsed().insert(scratchReg);
+ CallMI->insertUsedReg(scratchReg);
}
if (AdIBef.size() > 0)
// last operand is the def (unless for a store which has no def reg)
MachineOperand& DefOp = DefInst->getOperand(DefInst->getNumOperands()-1);
- if( DefOp.opIsDef() &&
- DefOp.getOperandType() == MachineOperand::MO_MachineRegister) {
+ if (DefOp.opIsDef() &&
+ DefOp.getType() == MachineOperand::MO_MachineRegister) {
// If the operand in DefInst is a def ...
-
bool DefEqUse = false;
std::vector<MachineInstr *>::iterator UseIt = DefIt;
// for each inst (UseInst) that is below the DefInst do ...
MachineOperand& UseOp = UseInst->getOperand(0);
- if( ! UseOp.opIsDef() &&
- UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
+ if (!UseOp.opIsDef() &&
+ UseOp.getType() == MachineOperand::MO_MachineRegister) {
// if use is a register ...
PhyRegAlloc &PRA) const {
MachineOperand& UseOp = UnordInst->getOperand(0);
- if( ! UseOp.opIsDef() &&
- UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
+ if (!UseOp.opIsDef() &&
+ UseOp.getType() == MachineOperand::MO_MachineRegister) {
// for the use of UnordInst, see whether there is a defining instr
// before in the OrdVec
OrdInst->getOperand(OrdInst->getNumOperands()-1);
if( DefOp.opIsDef() &&
- DefOp.getOperandType() == MachineOperand::MO_MachineRegister) {
+ DefOp.getType() == MachineOperand::MO_MachineRegister) {
//cerr << "\nDefining Ord Inst: " << *OrdInst;
// Now we are processing %ox of 1.
// We have to
- const int UReg = DefOp.getMachineRegNum();
- const int RegType = getRegType(UReg);
+ int UReg = DefOp.getMachineRegNum();
+ int RegType = getRegType(UReg);
MachineInstr *AdIBef, *AdIAft;
- const int StackOff = PRA.mcInfo.pushTempValue(target,
- getSpilledRegSize(RegType));
+ const int StackOff = PRA.MF.pushTempValue(target,
+ getSpilledRegSize(RegType));
// Save the UReg (%ox) on stack before it's destroyed
vector<MachineInstr*> mvec;
cpMem2RegMI(OrdVec, getFramePointer(), StackOff, DReg, RegType);
- cerr << "\nFixed CIRCULAR references by reordering";
-
if( DEBUG_RA ) {
+ cerr << "\nFixed CIRCULAR references by reordering:";
cerr << "\nBefore CIRCULAR Reordering:\n";
cerr << *UnordInst;
cerr << *OrdInst;