#include "SparcInternals.h"
#include "SparcRegClassInfo.h"
#include "llvm/Target/Sparc.h"
-#include "llvm/CodeGen/MachineCodeForMethod.h"
+#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/PhyRegAlloc.h"
#include "llvm/CodeGen/InstrSelection.h"
#include "llvm/CodeGen/InstrSelectionSupport.h"
using std::vector;
UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt)
- : MachineRegInfo(tgt), UltraSparcInfo(&tgt), NumOfIntArgRegs(6),
+ : MachineRegInfo(tgt), NumOfIntArgRegs(6),
NumOfFloatArgRegs(32), InvalidRegNum(1000) {
MachineRegClassArr.push_back(new SparcIntRegClass(IntRegClassID));
// Suggests a register for the ret address in the JMPL/CALL machine instr.
// Sparc ABI dictates that %o7 be used for this purpose.
//---------------------------------------------------------------------------
-void UltraSparcRegInfo::suggestReg4CallAddr(MachineInstr * CallMI,
- LiveRangeInfo& LRI,
- std::vector<RegClass *> RCList) const {
+void
+UltraSparcRegInfo::suggestReg4CallAddr(MachineInstr * CallMI,
+ LiveRangeInfo& LRI) const
+{
CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
const Value *RetAddrVal = argDesc->getReturnAddrReg();
- assert(RetAddrVal && "Return address value is required");
-
- // create a new LR for the return address and color it
- LiveRange * RetAddrLR = new LiveRange();
- RetAddrLR->insert( RetAddrVal );
- unsigned RegClassID = getRegClassIDOfValue( RetAddrVal );
- RetAddrLR->setRegClass( RCList[RegClassID] );
- RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID,SparcIntRegClass::o7));
- LRI.addLRToMap( RetAddrVal, RetAddrLR);
-
-}
+ assert(RetAddrVal && "INTERNAL ERROR: Return address value is required");
+
+ // A LR must already exist for the return address.
+ LiveRange *RetAddrLR = LRI.getLiveRangeForValue(RetAddrVal);
+ assert(RetAddrLR && "INTERNAL ERROR: No LR for return address of call!");
+ unsigned RegClassID = RetAddrLR->getRegClass()->getID();
+ RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID, SparcIntRegClass::o7));
+}
regClassIDOfArgReg == IntRegClassID &&
"This should only be an Int register for an FP argument");
- int TmpOff = MachineCodeForMethod::get(Meth).pushTempValue(target,
+ int TmpOff = MachineFunction::get(Meth).pushTempValue(target,
getSpilledRegSize(regType));
cpReg2MemMI(FirstAI->InstrnsBefore,
UniArgReg, getFramePointer(), TmpOff, IntRegType);
//
const MachineFrameInfo& frameInfo = target.getFrameInfo();
int offsetFromFP =
- frameInfo.getIncomingArgOffset(MachineCodeForMethod::get(Meth),
+ frameInfo.getIncomingArgOffset(MachineFunction::get(Meth),
argNo);
cpMem2RegMI(FirstAI->InstrnsBefore,
const MachineFrameInfo& frameInfo = target.getFrameInfo();
int offsetFromFP =
- frameInfo.getIncomingArgOffset(MachineCodeForMethod::get(Meth),
+ frameInfo.getIncomingArgOffset(MachineFunction::get(Meth),
argNo);
LR->modifySpillOffFromFP( offsetFromFP );
// outgoing call args and the return value of the call.
//---------------------------------------------------------------------------
void UltraSparcRegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
- LiveRangeInfo& LRI,
- std::vector<RegClass *> RCList) const {
- assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
+ LiveRangeInfo& LRI) const {
+ assert ( (target.getInstrInfo()).isCall(CallMI->getOpCode()) );
CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
- suggestReg4CallAddr(CallMI, LRI, RCList);
-
- // First color the return value of the call instruction. The return value
- // will be in %o0 if the value is an integer type, or in %f0 if the
- // value is a float type.
+ suggestReg4CallAddr(CallMI, LRI);
- // the return value cannot have a LR in machine instruction since it is
- // only defined by the call instruction
-
- // if type is not void, create a new live range and set its
- // register class and add to LRI
+ // First color the return value of the call instruction, if any.
+ // The return value will be in %o0 if the value is an integer type,
+ // or in %f0 if the value is a float type.
+ //
+ if (const Value *RetVal = argDesc->getReturnValue()) {
+ LiveRange *RetValLR = LRI.getLiveRangeForValue(RetVal);
+ assert(RetValLR && "No LR for return Value of call!");
- const Value *RetVal = argDesc->getReturnValue();
+ unsigned RegClassID = RetValLR->getRegClass()->getID();
- if (RetVal) {
- assert ((!LRI.getLiveRangeForValue(RetVal)) &&
- "LR for ret Value of call already definded!");
-
- // create a new LR for the return value
- LiveRange *RetValLR = new LiveRange();
- RetValLR->insert(RetVal);
- unsigned RegClassID = getRegClassIDOfValue(RetVal);
- RetValLR->setRegClass(RCList[RegClassID]);
- LRI.addLRToMap(RetVal, RetValLR);
-
// now suggest a register depending on the register class of ret arg
-
if( RegClassID == IntRegClassID )
RetValLR->setSuggestedColor(SparcIntRegClass::o0);
else if (RegClassID == FloatRegClassID )
else assert( 0 && "Unknown reg class for return value of call\n");
}
-
// Now suggest colors for arguments (operands) of the call instruction.
// Colors are suggested only if the arg number is smaller than the
// the number of registers allocated for argument passing.
// get the LR of call operand (parameter)
LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
-
- // not possible to have a null LR since all args (even consts)
- // must be defined before
- if (!LR) {
- cerr << " ERROR: In call instr, no LR for arg: " << RAV(CallArg) << "\n";
- assert(0 && "NO LR for call arg");
- }
-
+ assert (LR && "Must have a LR for all arguments since "
+ "all args (even consts) must be defined before");
+
unsigned regType = getRegType( LR );
unsigned regClassIDOfArgReg = MAXINT; // reg class of chosen reg (unused)
-
+
// Choose a register for this arg depending on whether it is
// an INT or FP value. Here we ignore whether or not it is a
// varargs calls, because FP arguments will be explicitly copied
const Value *argCopy = argDesc->getArgInfo(i).getArgCopy();
if (argCopy != NULL)
{
- assert(regType != IntRegType && argCopy->getType()->isIntegral()
+ assert(regType != IntRegType && argCopy->getType()->isInteger()
&& "Must be passing copy of FP argument in int register");
int copyRegNum = regNumForIntArg(/*inCallee*/false, /*isVarArgs*/false,
argNo, intArgNo, fpArgNo-1,
{
isArgInReg = true;
UniArgReg = (unsigned) UniArgRegOrNone;
- CallMI->getRegsUsed().insert(UniArgReg); // mark the reg as used
+ CallMI->insertUsedReg(UniArgReg); // mark the reg as used
}
if (LR->hasColor()) {
else {
// Copy UniLRReg to the stack to pass the arg on stack.
const MachineFrameInfo& frameInfo = target.getFrameInfo();
- int argOffset = frameInfo.getOutgoingArgOffset(PRA.mcInfo, argNo);
+ int argOffset = frameInfo.getOutgoingArgOffset(PRA.MF, argNo);
cpReg2MemMI(CallAI->InstrnsBefore,
UniLRReg, getStackPointer(), argOffset, regType);
}
// Use TmpOff to save TReg, since that may have a live value.
//
int TReg = PRA.getUniRegNotUsedByThisInst( LR->getRegClass(), CallMI );
- int TmpOff = PRA.mcInfo.pushTempValue(target,
- getSpilledRegSize(getRegType(LR)));
+ int TmpOff = PRA.MF.pushTempValue(target,
+ getSpilledRegSize(getRegType(LR)));
const MachineFrameInfo& frameInfo = target.getFrameInfo();
- int argOffset = frameInfo.getOutgoingArgOffset(PRA.mcInfo, argNo);
+ int argOffset = frameInfo.getOutgoingArgOffset(PRA.MF, argNo);
MachineInstr *Ad1, *Ad2, *Ad3, *Ad4;
PhyRegAlloc &PRA,
const BasicBlock *BB) const {
- assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
+ assert ( (target.getInstrInfo()).isCall(CallMI->getOpCode()) );
CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
UniRetReg = getUnifiedRegNum(RegClassID, CorrectCol);
// Mark the register as used by this instruction
- CallMI->getRegsUsed().insert(UniRetReg);
+ CallMI->insertUsedReg(UniRetReg);
// if the LR received the correct color, NOTHING to do
recvCorrectColor = RetValLR->hasColor()? RetValLR->getColor() == CorrectCol
const Value *argCopy = argDesc->getArgInfo(i).getArgCopy();
if (argCopy != NULL)
{
- assert(regType != IntRegType && argCopy->getType()->isIntegral()
+ assert(regType != IntRegType && argCopy->getType()->isInteger()
&& "Must be passing copy of FP argument in int register");
unsigned copyRegClassID = getRegClassIDOfValue(argCopy);
void UltraSparcRegInfo::suggestReg4RetValue(MachineInstr *RetMI,
LiveRangeInfo &LRI) const {
- assert( (UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode() ) );
+ assert( (target.getInstrInfo()).isReturn( RetMI->getOpCode() ) );
suggestReg4RetAddr(RetMI, LRI);
LiveRangeInfo &LRI,
AddedInstrns *RetAI) const {
- assert((UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode()));
+ assert((target.getInstrInfo()).isReturn( RetMI->getOpCode()));
// if there is an implicit ref, that has to be the ret value
if(RetMI->getNumImplicitRefs() > 0) {
unsigned UniRetReg = getUnifiedRegNum(RegClassID, CorrectCol);
// Mark the register as used by this instruction
- RetMI->getRegsUsed().insert(UniRetReg);
+ RetMI->insertUsedReg(UniRetReg);
// if the LR received the correct color, NOTHING to do
MachineInstr * MI = NULL;
switch( RegType ) {
case IntRegType:
+ assert(target.getInstrInfo().constantFitsInImmedField(STX, Offset));
MI = new MachineInstr(STX, 3);
- MI->SetMachineOperandReg(0, SrcReg, false);
- MI->SetMachineOperandReg(1, DestPtrReg, false);
+ MI->SetMachineOperandReg(0, SrcReg);
+ MI->SetMachineOperandReg(1, DestPtrReg);
MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset);
mvec.push_back(MI);
break;
case FPSingleRegType:
+ assert(target.getInstrInfo().constantFitsInImmedField(ST, Offset));
MI = new MachineInstr(ST, 3);
- MI->SetMachineOperandReg(0, SrcReg, false);
- MI->SetMachineOperandReg(1, DestPtrReg, false);
+ MI->SetMachineOperandReg(0, SrcReg);
+ MI->SetMachineOperandReg(1, DestPtrReg);
MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset);
mvec.push_back(MI);
break;
case FPDoubleRegType:
+ assert(target.getInstrInfo().constantFitsInImmedField(STD, Offset));
MI = new MachineInstr(STD, 3);
- MI->SetMachineOperandReg(0, SrcReg, false);
- MI->SetMachineOperandReg(1, DestPtrReg, false);
+ MI->SetMachineOperandReg(0, SrcReg);
+ MI->SetMachineOperandReg(1, DestPtrReg);
MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset);
mvec.push_back(MI);
case FloatCCRegType:
assert(0 && "Tell Vikram if this assertion fails: we may have to mask out the other bits here");
+ assert(target.getInstrInfo().constantFitsInImmedField(STXFSR, Offset));
MI = new MachineInstr(STXFSR, 3);
- MI->SetMachineOperandReg(0, SrcReg, false);
- MI->SetMachineOperandReg(1, DestPtrReg, false);
+ MI->SetMachineOperandReg(0, SrcReg);
+ MI->SetMachineOperandReg(1, DestPtrReg);
MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset);
mvec.push_back(MI);
MachineInstr * MI = NULL;
switch (RegType) {
case IntRegType:
+ assert(target.getInstrInfo().constantFitsInImmedField(LDX, Offset));
MI = new MachineInstr(LDX, 3);
- MI->SetMachineOperandReg(0, SrcPtrReg, false);
+ MI->SetMachineOperandReg(0, SrcPtrReg);
MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset);
MI->SetMachineOperandReg(2, DestReg, true);
break;
case FPSingleRegType:
+ assert(target.getInstrInfo().constantFitsInImmedField(LD, Offset));
MI = new MachineInstr(LD, 3);
- MI->SetMachineOperandReg(0, SrcPtrReg, false);
+ MI->SetMachineOperandReg(0, SrcPtrReg);
MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset);
MI->SetMachineOperandReg(2, DestReg, true);
break;
case FPDoubleRegType:
+ assert(target.getInstrInfo().constantFitsInImmedField(LDD, Offset));
MI = new MachineInstr(LDD, 3);
- MI->SetMachineOperandReg(0, SrcPtrReg, false);
+ MI->SetMachineOperandReg(0, SrcPtrReg);
MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset);
MI->SetMachineOperandReg(2, DestReg, true);
case FloatCCRegType:
assert(0 && "Tell Vikram if this assertion fails: we may have to mask out the other bits here");
+ assert(target.getInstrInfo().constantFitsInImmedField(LDXFSR, Offset));
MI = new MachineInstr(LDXFSR, 3);
- MI->SetMachineOperandReg(0, SrcPtrReg, false);
+ MI->SetMachineOperandReg(0, SrcPtrReg);
MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed,
(int64_t) Offset);
MI->SetMachineOperandReg(2, DestReg, true);
switch( RegType ) {
case IntRegType:
MI = new MachineInstr(ADD, 3);
- MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false);
- MI->SetMachineOperandReg(1, getZeroRegNum(), false);
- MI->SetMachineOperandVal(2, MachineOperand:: MO_VirtualRegister, Dest, true);
+ MI->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, Src);
+ MI->SetMachineOperandReg(1, getZeroRegNum());
+ MI->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, Dest, true);
break;
case FPSingleRegType:
MI = new MachineInstr(FMOVS, 2);
- MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false);
- MI->SetMachineOperandVal(1, MachineOperand:: MO_VirtualRegister, Dest, true);
+ MI->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, Src);
+ MI->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, Dest, true);
break;
case FPDoubleRegType:
MI = new MachineInstr(FMOVD, 2);
- MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false);
- MI->SetMachineOperandVal(1, MachineOperand:: MO_VirtualRegister, Dest, true);
+ MI->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, Src);
+ MI->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, Dest, true);
break;
default:
assert(0 && "Unknow RegType in CpValu2Value");
}
- if (MI)
- mvec.push_back(MI);
+ mvec.push_back(MI);
}
const BasicBlock *BB,
PhyRegAlloc &PRA) const
{
- assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
+ assert ( (target.getInstrInfo()).isCall(CallMI->getOpCode()) );
// has set to record which registers were saved/restored
//
// and add them to InstrnsBefore and InstrnsAfter of the
// call instruction
//
- int StackOff = PRA.mcInfo.pushTempValue(target,
- getSpilledRegSize(RegType));
+ int StackOff = PRA.MF.pushTempValue(target,
+ getSpilledRegSize(RegType));
vector<MachineInstr*> AdIBef, AdIAft;
scratchReg = PRA.getUsableUniRegAtMI(scratchRegType, &LVSetBef,
CallMI, AdIBef, AdIAft);
assert(scratchReg != getInvalidRegNum());
- CallMI->getRegsUsed().insert(scratchReg);
+ CallMI->insertUsedReg(scratchReg);
}
if (AdIBef.size() > 0)
scratchReg = PRA.getUsableUniRegAtMI(scratchRegType, &LVSetAft,
CallMI, AdIBef, AdIAft);
assert(scratchReg != getInvalidRegNum());
- CallMI->getRegsUsed().insert(scratchReg);
+ CallMI->insertUsedReg(scratchReg);
}
if (AdIBef.size() > 0)
// last operand is the def (unless for a store which has no def reg)
MachineOperand& DefOp = DefInst->getOperand(DefInst->getNumOperands()-1);
- if( DefOp.opIsDef() &&
- DefOp.getOperandType() == MachineOperand::MO_MachineRegister) {
+ if (DefOp.opIsDef() &&
+ DefOp.getType() == MachineOperand::MO_MachineRegister) {
// If the operand in DefInst is a def ...
-
bool DefEqUse = false;
std::vector<MachineInstr *>::iterator UseIt = DefIt;
// for each inst (UseInst) that is below the DefInst do ...
MachineOperand& UseOp = UseInst->getOperand(0);
- if( ! UseOp.opIsDef() &&
- UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
+ if (!UseOp.opIsDef() &&
+ UseOp.getType() == MachineOperand::MO_MachineRegister) {
// if use is a register ...
PhyRegAlloc &PRA) const {
MachineOperand& UseOp = UnordInst->getOperand(0);
- if( ! UseOp.opIsDef() &&
- UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
+ if (!UseOp.opIsDef() &&
+ UseOp.getType() == MachineOperand::MO_MachineRegister) {
// for the use of UnordInst, see whether there is a defining instr
// before in the OrdVec
OrdInst->getOperand(OrdInst->getNumOperands()-1);
if( DefOp.opIsDef() &&
- DefOp.getOperandType() == MachineOperand::MO_MachineRegister) {
+ DefOp.getType() == MachineOperand::MO_MachineRegister) {
//cerr << "\nDefining Ord Inst: " << *OrdInst;
// Now we are processing %ox of 1.
// We have to
- const int UReg = DefOp.getMachineRegNum();
- const int RegType = getRegType(UReg);
+ int UReg = DefOp.getMachineRegNum();
+ int RegType = getRegType(UReg);
MachineInstr *AdIBef, *AdIAft;
- const int StackOff = PRA.mcInfo.pushTempValue(target,
- getSpilledRegSize(RegType));
+ const int StackOff = PRA.MF.pushTempValue(target,
+ getSpilledRegSize(RegType));
// Save the UReg (%ox) on stack before it's destroyed
vector<MachineInstr*> mvec;
cpMem2RegMI(OrdVec, getFramePointer(), StackOff, DReg, RegType);
- cerr << "\nFixed CIRCULAR references by reordering";
-
if( DEBUG_RA ) {
+ cerr << "\nFixed CIRCULAR references by reordering:";
cerr << "\nBefore CIRCULAR Reordering:\n";
cerr << *UnordInst;
cerr << *OrdInst;
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