Remove separate vector of implicit refs from MachineInstr, and

[oota-llvm.git] / lib / Target / SparcV9 / SparcV9RegInfo.cpp

diff --git a/lib/Target/SparcV9/SparcV9RegInfo.cpp b/lib/Target/SparcV9/SparcV9RegInfo.cpp
index e80185841f67dcceb69b2a2bd3602dd850517b22..f6ad9c69387ca1a5f97d5854e517242bf7600d97 100644 (file)
--- a/lib/Target/SparcV9/SparcV9RegInfo.cpp
+++ b/lib/Target/SparcV9/SparcV9RegInfo.cpp
@@ -683,7 +683,7 @@ UltraSparcRegInfo::InitializeOutgoingArg(MachineInstr* CallMI,
     else {
       // Copy UniLRReg to the stack to pass the arg on stack.
       const MachineFrameInfo& frameInfo = target.getFrameInfo();
-      int argOffset = frameInfo.getOutgoingArgOffset(PRA.mcInfo, argNo);
+      int argOffset = frameInfo.getOutgoingArgOffset(PRA.MF, argNo);
       cpReg2MemMI(CallAI->InstrnsBefore,
                   UniLRReg, getStackPointer(), argOffset, regType);
     }
@@ -705,10 +705,10 @@ UltraSparcRegInfo::InitializeOutgoingArg(MachineInstr* CallMI,
       // Use TmpOff to save TReg, since that may have a live value.
       // 
       int TReg = PRA.getUniRegNotUsedByThisInst( LR->getRegClass(), CallMI );
-      int TmpOff = PRA.mcInfo.pushTempValue(target,  
-                                            getSpilledRegSize(getRegType(LR)));
+      int TmpOff = PRA.MF.pushTempValue(target,  
+                                        getSpilledRegSize(getRegType(LR)));
       const MachineFrameInfo& frameInfo = target.getFrameInfo();
-      int argOffset = frameInfo.getOutgoingArgOffset(PRA.mcInfo, argNo);
+      int argOffset = frameInfo.getOutgoingArgOffset(PRA.MF, argNo);
       
       MachineInstr *Ad1, *Ad2, *Ad3, *Ad4;
         
@@ -1151,8 +1151,8 @@ UltraSparcRegInfo::cpReg2MemMI(vector<MachineInstr*>& mvec,
   case IntRegType:
     assert(target.getInstrInfo().constantFitsInImmedField(STX, Offset));
     MI = new MachineInstr(STX, 3);
-    MI->SetMachineOperandReg(0, SrcReg, false);
-    MI->SetMachineOperandReg(1, DestPtrReg, false);
+    MI->SetMachineOperandReg(0, SrcReg);
+    MI->SetMachineOperandReg(1, DestPtrReg);
     MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed, 
                                (int64_t) Offset);
     mvec.push_back(MI);
@@ -1161,8 +1161,8 @@ UltraSparcRegInfo::cpReg2MemMI(vector<MachineInstr*>& mvec,
   case FPSingleRegType:
     assert(target.getInstrInfo().constantFitsInImmedField(ST, Offset));
     MI = new MachineInstr(ST, 3);
-    MI->SetMachineOperandReg(0, SrcReg, false);
-    MI->SetMachineOperandReg(1, DestPtrReg, false);
+    MI->SetMachineOperandReg(0, SrcReg);
+    MI->SetMachineOperandReg(1, DestPtrReg);
     MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed, 
                                (int64_t) Offset);
     mvec.push_back(MI);
@@ -1171,8 +1171,8 @@ UltraSparcRegInfo::cpReg2MemMI(vector<MachineInstr*>& mvec,
   case FPDoubleRegType:
     assert(target.getInstrInfo().constantFitsInImmedField(STD, Offset));
     MI = new MachineInstr(STD, 3);
-    MI->SetMachineOperandReg(0, SrcReg, false);
-    MI->SetMachineOperandReg(1, DestPtrReg, false);
+    MI->SetMachineOperandReg(0, SrcReg);
+    MI->SetMachineOperandReg(1, DestPtrReg);
     MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed, 
                                (int64_t) Offset);
     mvec.push_back(MI);
@@ -1193,8 +1193,8 @@ UltraSparcRegInfo::cpReg2MemMI(vector<MachineInstr*>& mvec,
     assert(0 && "Tell Vikram if this assertion fails: we may have to mask out the other bits here");
     assert(target.getInstrInfo().constantFitsInImmedField(STXFSR, Offset));
     MI = new MachineInstr(STXFSR, 3);
-    MI->SetMachineOperandReg(0, SrcReg, false);
-    MI->SetMachineOperandReg(1, DestPtrReg, false);
+    MI->SetMachineOperandReg(0, SrcReg);
+    MI->SetMachineOperandReg(1, DestPtrReg);
     MI->SetMachineOperandConst(2, MachineOperand:: MO_SignExtendedImmed, 
                                (int64_t) Offset);
     mvec.push_back(MI);
@@ -1224,7 +1224,7 @@ UltraSparcRegInfo::cpMem2RegMI(vector<MachineInstr*>& mvec,
   case IntRegType:
     assert(target.getInstrInfo().constantFitsInImmedField(LDX, Offset));
     MI = new MachineInstr(LDX, 3);
-    MI->SetMachineOperandReg(0, SrcPtrReg, false);
+    MI->SetMachineOperandReg(0, SrcPtrReg);
     MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed, 
                                (int64_t) Offset);
     MI->SetMachineOperandReg(2, DestReg, true);
@@ -1234,7 +1234,7 @@ UltraSparcRegInfo::cpMem2RegMI(vector<MachineInstr*>& mvec,
   case FPSingleRegType:
     assert(target.getInstrInfo().constantFitsInImmedField(LD, Offset));
     MI = new MachineInstr(LD, 3);
-    MI->SetMachineOperandReg(0, SrcPtrReg, false);
+    MI->SetMachineOperandReg(0, SrcPtrReg);
     MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed, 
                                (int64_t) Offset);
     MI->SetMachineOperandReg(2, DestReg, true);
@@ -1244,7 +1244,7 @@ UltraSparcRegInfo::cpMem2RegMI(vector<MachineInstr*>& mvec,
   case FPDoubleRegType:
     assert(target.getInstrInfo().constantFitsInImmedField(LDD, Offset));
     MI = new MachineInstr(LDD, 3);
-    MI->SetMachineOperandReg(0, SrcPtrReg, false);
+    MI->SetMachineOperandReg(0, SrcPtrReg);
     MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed, 
                                (int64_t) Offset);
     MI->SetMachineOperandReg(2, DestReg, true);
@@ -1266,7 +1266,7 @@ UltraSparcRegInfo::cpMem2RegMI(vector<MachineInstr*>& mvec,
     assert(0 && "Tell Vikram if this assertion fails: we may have to mask out the other bits here");
     assert(target.getInstrInfo().constantFitsInImmedField(LDXFSR, Offset));
     MI = new MachineInstr(LDXFSR, 3);
-    MI->SetMachineOperandReg(0, SrcPtrReg, false);
+    MI->SetMachineOperandReg(0, SrcPtrReg);
     MI->SetMachineOperandConst(1, MachineOperand:: MO_SignExtendedImmed, 
                                (int64_t) Offset);
     MI->SetMachineOperandReg(2, DestReg, true);
@@ -1298,30 +1298,29 @@ UltraSparcRegInfo::cpValue2Value(Value *Src,
   switch( RegType ) {
   case IntRegType:
     MI = new MachineInstr(ADD, 3);
-    MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false);
-    MI->SetMachineOperandReg(1, getZeroRegNum(), false);
-    MI->SetMachineOperandVal(2, MachineOperand:: MO_VirtualRegister, Dest, true);
+    MI->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, Src);
+    MI->SetMachineOperandReg(1, getZeroRegNum());
+    MI->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, Dest, true);
     break;
 
   case FPSingleRegType:
     MI = new MachineInstr(FMOVS, 2);
-    MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false);
-    MI->SetMachineOperandVal(1, MachineOperand:: MO_VirtualRegister, Dest, true);
+    MI->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, Src);
+    MI->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, Dest, true);
     break;
 
 
   case FPDoubleRegType:
     MI = new MachineInstr(FMOVD, 2);
-    MI->SetMachineOperandVal(0, MachineOperand:: MO_VirtualRegister, Src, false);
-    MI->SetMachineOperandVal(1, MachineOperand:: MO_VirtualRegister, Dest, true);
+    MI->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, Src);
+    MI->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, Dest, true);
     break;
 
   default:
     assert(0 && "Unknow RegType in CpValu2Value");
   }
 
-  if (MI)
-    mvec.push_back(MI);
+  mvec.push_back(MI);
 }
 
 
@@ -1413,8 +1412,8 @@ UltraSparcRegInfo::insertCallerSavingCode(vector<MachineInstr*>& instrnsBefore,
            // and add them to InstrnsBefore and InstrnsAfter of the
            // call instruction
             // 
-           int StackOff =  PRA.mcInfo.pushTempValue(target,  
-                                              getSpilledRegSize(RegType));
+           int StackOff =  PRA.MF.pushTempValue(target,  
+                                                 getSpilledRegSize(RegType));
             
            vector<MachineInstr*> AdIBef, AdIAft;
             
@@ -1709,12 +1708,12 @@ void UltraSparcRegInfo::moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
          // Now we are processing %ox of 1.
          // We have to 
              
-         const int UReg = DefOp.getMachineRegNum();
-         const int RegType = getRegType(UReg);
+         int UReg = DefOp.getMachineRegNum();
+         int RegType = getRegType(UReg);
          MachineInstr *AdIBef, *AdIAft;
              
-         const int StackOff =  PRA.mcInfo.pushTempValue(target,
-                                        getSpilledRegSize(RegType));
+         const int StackOff = PRA.MF.pushTempValue(target,
+                                                    getSpilledRegSize(RegType));
          
          // Save the UReg (%ox) on stack before it's destroyed
           vector<MachineInstr*> mvec;