-//===-- UltraSparcV9SchedInfo.cpp -------------------------------------------===//
-//
+//===-- SparcV9SchedInfo.cpp ----------------------------------------------===//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
-// Describe the scheduling characteristics of the UltraSparcV9
+// Describe the scheduling characteristics of the UltraSparc IIi.
//
//===----------------------------------------------------------------------===//
(see pg. 327).
** Don't put a branch in a group that crosses a 32-byte boundary!
An artificial branch is inserted after every 32 bytes, and having
- another branch will force the group to be broken into 2 groups.
+ another branch will force the group to be broken into 2 groups.
iTLB rules:
-- Don't let a loop span two memory pages, if possible
-- Shift instructions cannot be grouped with other IEU0-specific instructions.
-- CC setting instructions cannot be grouped with other IEU1-specific instrs.
-- Several instructions must be issued in a single-instruction group:
- MOVcc or MOVr, MULs/x and DIVs/x, SAVE/RESTORE, many others
+ MOVcc or MOVr, MULs/x and DIVs/x, SAVE/RESTORE, many others
-- A CALL or JMPL breaks a group, ie, is not combined with subsequent instrs.
---
---
+--
+--
Branch delay slot scheduling rules:
-- A CTI couple (two back-to-back CTI instructions in the dynamic stream)
static const CPUResource FPMIssueSlots( "FP Instr Slot 2", 1);
// IEUN instructions can use either Alu and should use IAluN.
-// IEU0 instructions must use Alu 1 and should use both IAluN and IAlu0.
-// IEU1 instructions must use Alu 2 and should use both IAluN and IAlu1.
+// IEU0 instructions must use Alu 1 and should use both IAluN and IAlu0.
+// IEU1 instructions must use Alu 2 and should use both IAluN and IAlu1.
static const CPUResource IAluN("Int ALU 1or2", 2);
static const CPUResource IAlu0("Int ALU 1", 1);
static const CPUResource IAlu1("Int ALU 2", 1);
//---------------------------------------------------------------------------
// const InstrClassRUsage SparcV9RUsageDesc[]
-//
+//
// Purpose:
// Resource usage information for instruction in each scheduling class.
// The InstrRUsage Objects for individual classes are specified first.
static const InstrClassRUsage NoneClassRUsage = {
SPARC_NONE,
/*totCycles*/ 7,
-
+
/* maxIssueNum */ 4,
/* isSingleIssue */ false,
/* breaksGroup */ false,
/* numBubbles */ 0,
-
+
/*numSlots*/ 4,
/* feasibleSlots[] */ { 0, 1, 2, 3 },
-
+
/*numEntries*/ 0,
/* V[] */ {
/*Cycle G */
static const InstrClassRUsage IEUNClassRUsage = {
SPARC_IEUN,
/*totCycles*/ 7,
-
+
/* maxIssueNum */ 3,
/* isSingleIssue */ false,
/* breaksGroup */ false,
/* numBubbles */ 0,
-
+
/*numSlots*/ 3,
/* feasibleSlots[] */ { 0, 1, 2 },
-
+
/*numEntries*/ 4,
/* V[] */ {
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
static const InstrClassRUsage IEU0ClassRUsage = {
SPARC_IEU0,
/*totCycles*/ 7,
-
+
/* maxIssueNum */ 1,
/* isSingleIssue */ false,
/* breaksGroup */ false,
/* numBubbles */ 0,
-
+
/*numSlots*/ 3,
/* feasibleSlots[] */ { 0, 1, 2 },
-
+
/*numEntries*/ 5,
/* V[] */ {
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
static const InstrClassRUsage IEU1ClassRUsage = {
SPARC_IEU1,
/*totCycles*/ 7,
-
+
/* maxIssueNum */ 1,
/* isSingleIssue */ false,
/* breaksGroup */ false,
/* numBubbles */ 0,
-
+
/*numSlots*/ 3,
/* feasibleSlots[] */ { 0, 1, 2 },
-
+
/*numEntries*/ 5,
/* V[] */ {
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
static const InstrClassRUsage FPMClassRUsage = {
SPARC_FPM,
/*totCycles*/ 7,
-
+
/* maxIssueNum */ 1,
/* isSingleIssue */ false,
/* breaksGroup */ false,
/* numBubbles */ 0,
-
+
/*numSlots*/ 4,
/* feasibleSlots[] */ { 0, 1, 2, 3 },
-
+
/*numEntries*/ 7,
/* V[] */ {
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
static const InstrClassRUsage FPAClassRUsage = {
SPARC_FPA,
/*totCycles*/ 7,
-
+
/* maxIssueNum */ 1,
/* isSingleIssue */ false,
/* breaksGroup */ false,
/* numBubbles */ 0,
-
+
/*numSlots*/ 4,
/* feasibleSlots[] */ { 0, 1, 2, 3 },
-
+
/*numEntries*/ 7,
/* V[] */ {
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
static const InstrClassRUsage LDClassRUsage = {
SPARC_LD,
/*totCycles*/ 7,
-
+
/* maxIssueNum */ 1,
/* isSingleIssue */ false,
/* breaksGroup */ false,
/* numBubbles */ 0,
-
+
/*numSlots*/ 3,
/* feasibleSlots[] */ { 0, 1, 2, },
-
+
/*numEntries*/ 6,
/* V[] */ {
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
static const InstrClassRUsage STClassRUsage = {
SPARC_ST,
/*totCycles*/ 7,
-
+
/* maxIssueNum */ 1,
/* isSingleIssue */ false,
/* breaksGroup */ false,
/* numBubbles */ 0,
-
+
/*numSlots*/ 3,
/* feasibleSlots[] */ { 0, 1, 2 },
-
+
/*numEntries*/ 4,
/* V[] */ {
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
static const InstrClassRUsage CTIClassRUsage = {
SPARC_CTI,
/*totCycles*/ 7,
-
+
/* maxIssueNum */ 1,
/* isSingleIssue */ false,
/* breaksGroup */ false,
/* numBubbles */ 0,
-
+
/*numSlots*/ 4,
/* feasibleSlots[] */ { 0, 1, 2, 3 },
-
+
/*numEntries*/ 4,
/* V[] */ {
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
- { CTIIssueSlots.rid, 0, 1 },
+ { CTIIssueSlots.rid, 0, 1 },
/*Cycle E */ { IAlu0.rid, 1, 1 },
/*Cycles E-C */ { CTIDelayCycle.rid, 1, 2 }
- /*Cycle C */
+ /*Cycle C */
/*Cycle N1*/
/*Cycle N1*/
/*Cycle N1*/
static const InstrClassRUsage SingleClassRUsage = {
SPARC_SINGLE,
/*totCycles*/ 7,
-
+
/* maxIssueNum */ 1,
/* isSingleIssue */ true,
/* breaksGroup */ false,
/* numBubbles */ 0,
-
+
/*numSlots*/ 1,
/* feasibleSlots[] */ { 0 },
-
+
/*numEntries*/ 5,
/* V[] */ {
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
//---------------------------------------------------------------------------
// const InstrIssueDelta SparcV9InstrIssueDeltas[]
-//
+//
// Purpose:
// Changes to issue restrictions information in InstrClassRUsage for
// instructions that differ from other instructions in their class.
// opCode, isSingleIssue, breaksGroup, numBubbles
- // Special cases for single-issue only
- // Other single issue cases are below.
-//{ V9::LDDA, true, true, 0 },
-//{ V9::STDA, true, true, 0 },
-//{ V9::LDDF, true, true, 0 },
-//{ V9::LDDFA, true, true, 0 },
- { V9::ADDCr, true, true, 0 },
- { V9::ADDCi, true, true, 0 },
- { V9::ADDCccr, true, true, 0 },
- { V9::ADDCcci, true, true, 0 },
- { V9::SUBCr, true, true, 0 },
- { V9::SUBCi, true, true, 0 },
- { V9::SUBCccr, true, true, 0 },
- { V9::SUBCcci, true, true, 0 },
-//{ V9::LDSTUB, true, true, 0 },
-//{ V9::SWAP, true, true, 0 },
-//{ V9::SWAPA, true, true, 0 },
-//{ V9::CAS, true, true, 0 },
-//{ V9::CASA, true, true, 0 },
-//{ V9::CASX, true, true, 0 },
-//{ V9::CASXA, true, true, 0 },
-//{ V9::LDFSR, true, true, 0 },
-//{ V9::LDFSRA, true, true, 0 },
-//{ V9::LDXFSR, true, true, 0 },
-//{ V9::LDXFSRA, true, true, 0 },
-//{ V9::STFSR, true, true, 0 },
-//{ V9::STFSRA, true, true, 0 },
-//{ V9::STXFSR, true, true, 0 },
-//{ V9::STXFSRA, true, true, 0 },
-//{ V9::SAVED, true, true, 0 },
-//{ V9::RESTORED, true, true, 0 },
-//{ V9::FLUSH, true, true, 9 },
-//{ V9::FLUSHW, true, true, 9 },
-//{ V9::ALIGNADDR, true, true, 0 },
- { V9::RETURNr, true, true, 0 },
- { V9::RETURNi, true, true, 0 },
-//{ V9::DONE, true, true, 0 },
-//{ V9::RETRY, true, true, 0 },
-//{ V9::TCC, true, true, 0 },
-//{ V9::SHUTDOWN, true, true, 0 },
-
- // Special cases for breaking group *before*
- // CURRENTLY NOT SUPPORTED!
- { V9::CALL, false, false, 0 },
- { V9::JMPLCALLr, false, false, 0 },
- { V9::JMPLCALLi, false, false, 0 },
- { V9::JMPLRETr, false, false, 0 },
- { V9::JMPLRETi, false, false, 0 },
-
- // Special cases for breaking the group *after*
- { V9::MULXr, true, true, (4+34)/2 },
- { V9::MULXi, true, true, (4+34)/2 },
- { V9::FDIVS, false, true, 0 },
- { V9::FDIVD, false, true, 0 },
- { V9::FDIVQ, false, true, 0 },
- { V9::FSQRTS, false, true, 0 },
- { V9::FSQRTD, false, true, 0 },
- { V9::FSQRTQ, false, true, 0 },
+ // Special cases for single-issue only
+ // Other single issue cases are below.
+//{ V9::LDDA, true, true, 0 },
+//{ V9::STDA, true, true, 0 },
+//{ V9::LDDF, true, true, 0 },
+//{ V9::LDDFA, true, true, 0 },
+ { V9::ADDCr, true, true, 0 },
+ { V9::ADDCi, true, true, 0 },
+ { V9::ADDCccr, true, true, 0 },
+ { V9::ADDCcci, true, true, 0 },
+ { V9::SUBCr, true, true, 0 },
+ { V9::SUBCi, true, true, 0 },
+ { V9::SUBCccr, true, true, 0 },
+ { V9::SUBCcci, true, true, 0 },
+//{ V9::LDSTUB, true, true, 0 },
+//{ V9::SWAP, true, true, 0 },
+//{ V9::SWAPA, true, true, 0 },
+//{ V9::CAS, true, true, 0 },
+//{ V9::CASA, true, true, 0 },
+//{ V9::CASX, true, true, 0 },
+//{ V9::CASXA, true, true, 0 },
+//{ V9::LDFSR, true, true, 0 },
+//{ V9::LDFSRA, true, true, 0 },
+//{ V9::LDXFSR, true, true, 0 },
+//{ V9::LDXFSRA, true, true, 0 },
+//{ V9::STFSR, true, true, 0 },
+//{ V9::STFSRA, true, true, 0 },
+//{ V9::STXFSR, true, true, 0 },
+//{ V9::STXFSRA, true, true, 0 },
+//{ V9::SAVED, true, true, 0 },
+//{ V9::RESTORED, true, true, 0 },
+//{ V9::FLUSH, true, true, 9 },
+//{ V9::FLUSHW, true, true, 9 },
+//{ V9::ALIGNADDR, true, true, 0 },
+//{ V9::DONE, true, true, 0 },
+//{ V9::RETRY, true, true, 0 },
+//{ V9::TCC, true, true, 0 },
+//{ V9::SHUTDOWN, true, true, 0 },
+
+ // Special cases for breaking group *before*
+ // CURRENTLY NOT SUPPORTED!
+ { V9::CALL, false, false, 0 },
+ { V9::JMPLCALLr, false, false, 0 },
+ { V9::JMPLCALLi, false, false, 0 },
+ { V9::JMPLRETr, false, false, 0 },
+ { V9::JMPLRETi, false, false, 0 },
+
+ // Special cases for breaking the group *after*
+ { V9::MULXr, true, true, (4+34)/2 },
+ { V9::MULXi, true, true, (4+34)/2 },
+ { V9::FDIVS, false, true, 0 },
+ { V9::FDIVD, false, true, 0 },
+ { V9::FDIVQ, false, true, 0 },
+ { V9::FSQRTS, false, true, 0 },
+ { V9::FSQRTD, false, true, 0 },
+ { V9::FSQRTQ, false, true, 0 },
//{ V9::FCMP{LE,GT,NE,EQ}, false, true, 0 },
-
- // Instructions that introduce bubbles
-//{ V9::MULScc, true, true, 2 },
-//{ V9::SMULcc, true, true, (4+18)/2 },
-//{ V9::UMULcc, true, true, (4+19)/2 },
- { V9::SDIVXr, true, true, 68 },
- { V9::SDIVXi, true, true, 68 },
- { V9::UDIVXr, true, true, 68 },
- { V9::UDIVXi, true, true, 68 },
-//{ V9::SDIVcc, true, true, 36 },
-//{ V9::UDIVcc, true, true, 37 },
- { V9::WRCCRr, true, true, 4 },
- { V9::WRCCRi, true, true, 4 },
-//{ V9::WRPR, true, true, 4 },
-//{ V9::RDCCR, true, true, 0 }, // no bubbles after, but see below
-//{ V9::RDPR, true, true, 0 },
+
+ // Instructions that introduce bubbles
+//{ V9::MULScc, true, true, 2 },
+//{ V9::SMULcc, true, true, (4+18)/2 },
+//{ V9::UMULcc, true, true, (4+19)/2 },
+ { V9::SDIVXr, true, true, 68 },
+ { V9::SDIVXi, true, true, 68 },
+ { V9::UDIVXr, true, true, 68 },
+ { V9::UDIVXi, true, true, 68 },
+//{ V9::SDIVcc, true, true, 36 },
+//{ V9::UDIVcc, true, true, 37 },
+ { V9::WRCCRr, true, true, 4 },
+ { V9::WRCCRi, true, true, 4 },
+//{ V9::WRPR, true, true, 4 },
+//{ V9::RDCCR, true, true, 0 }, // no bubbles after, but see below
+//{ V9::RDPR, true, true, 0 },
};
//---------------------------------------------------------------------------
// const InstrRUsageDelta SparcV9InstrUsageDeltas[]
-//
+//
// Purpose:
// Changes to resource usage information in InstrClassRUsage for
// instructions that differ from other instructions in their class.
// MachineOpCode, Resource, Start cycle, Num cycles
- //
+ //
// JMPL counts as a load/store instruction for issue!
//
{ V9::JMPLCALLr, LSIssueSlots.rid, 0, 1 },
{ V9::JMPLCALLi, LSIssueSlots.rid, 0, 1 },
{ V9::JMPLRETr, LSIssueSlots.rid, 0, 1 },
{ V9::JMPLRETi, LSIssueSlots.rid, 0, 1 },
-
- //
+
+ //
// Many instructions cannot issue for the next 2 cycles after an FCMP
// We model that with a fake resource FCMPDelayCycle.
- //
+ //
{ V9::FCMPS, FCMPDelayCycle.rid, 1, 3 },
{ V9::FCMPD, FCMPDelayCycle.rid, 1, 3 },
{ V9::FCMPQ, FCMPDelayCycle.rid, 1, 3 },
-
+
{ V9::MULXr, FCMPDelayCycle.rid, 1, 1 },
{ V9::MULXi, FCMPDelayCycle.rid, 1, 1 },
{ V9::SDIVXr, FCMPDelayCycle.rid, 1, 1 },
{ V9::FMOVRSNZ, FCMPDelayCycle.rid, 1, 1 },
{ V9::FMOVRSGZ, FCMPDelayCycle.rid, 1, 1 },
{ V9::FMOVRSGEZ,FCMPDelayCycle.rid, 1, 1 },
-
- //
+
+ //
// Some instructions are stalled in the GROUP stage if a CTI is in
// the E or C stage. We model that with a fake resource CTIDelayCycle.
- //
+ //
{ V9::LDDFr, CTIDelayCycle.rid, 1, 1 },
{ V9::LDDFi, CTIDelayCycle.rid, 1, 1 },
//{ V9::LDDA, CTIDelayCycle.rid, 1, 1 },
//{ V9::CASA, CTIDelayCycle.rid, 1, 1 },
//{ V9::CASX, CTIDelayCycle.rid, 1, 1 },
//{ V9::CASXA, CTIDelayCycle.rid, 1, 1 },
-
+
//
// Signed int loads of less than dword size return data in cycle N1 (not C)
// and put all loads in consecutive cycles into delayed load return mode.
{ V9::LDSBr, LdReturn.rid, 3, 1 },
{ V9::LDSBi, LdReturn.rid, 2, -1 },
{ V9::LDSBi, LdReturn.rid, 3, 1 },
-
+
{ V9::LDSHr, LdReturn.rid, 2, -1 },
{ V9::LDSHr, LdReturn.rid, 3, 1 },
{ V9::LDSHi, LdReturn.rid, 2, -1 },
{ V9::LDSHi, LdReturn.rid, 3, 1 },
-
+
{ V9::LDSWr, LdReturn.rid, 2, -1 },
{ V9::LDSWr, LdReturn.rid, 3, 1 },
{ V9::LDSWi, LdReturn.rid, 2, -1 },
// Together with their single-issue requirement, this means all four issue
// slots are effectively blocked for those cycles, plus the issue cycle.
// This does not increase the latency of the instruction itself.
- //
+ //
{ V9::RDCCR, AllIssueSlots.rid, 0, 5 },
{ V9::RDCCR, AllIssueSlots.rid, 0, 5 },
{ V9::RDCCR, AllIssueSlots.rid, 0, 5 },
#undef EXPLICIT_BUBBLES_NEEDED
#ifdef EXPLICIT_BUBBLES_NEEDED
- //
+ //
// MULScc inserts one bubble.
// This means it breaks the current group (captured in UltraSparcV9SchedInfo)
// *and occupies all issue slots for the next cycle
- //
+ //
//{ V9::MULScc, AllIssueSlots.rid, 2, 2-1 },
//{ V9::MULScc, AllIssueSlots.rid, 2, 2-1 },
//{ V9::MULScc, AllIssueSlots.rid, 2, 2-1 },
//{ V9::MULScc, AllIssueSlots.rid, 2, 2-1 },
-
- //
+
+ //
// SMULcc inserts between 4 and 18 bubbles, depending on #leading 0s in rs1.
// We just model this with a simple average.
- //
+ //
//{ V9::SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 },
//{ V9::SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 },
//{ V9::SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 },
//{ V9::SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 },
-
+
// SMULcc inserts between 4 and 19 bubbles, depending on #leading 0s in rs1.
//{ V9::UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 },
//{ V9::UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 },
//{ V9::UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 },
//{ V9::UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 },
-
- //
+
+ //
// MULX inserts between 4 and 34 bubbles, depending on #leading 0s in rs1.
- //
+ //
{ V9::MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 },
{ V9::MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 },
{ V9::MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 },
{ V9::MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 },
-
- //
+
+ //
// SDIVcc inserts 36 bubbles.
- //
+ //
//{ V9::SDIVcc, AllIssueSlots.rid, 2, 36-1 },
//{ V9::SDIVcc, AllIssueSlots.rid, 2, 36-1 },
//{ V9::SDIVcc, AllIssueSlots.rid, 2, 36-1 },
//{ V9::SDIVcc, AllIssueSlots.rid, 2, 36-1 },
-
+
// UDIVcc inserts 37 bubbles.
//{ V9::UDIVcc, AllIssueSlots.rid, 2, 37-1 },
//{ V9::UDIVcc, AllIssueSlots.rid, 2, 37-1 },
//{ V9::UDIVcc, AllIssueSlots.rid, 2, 37-1 },
//{ V9::UDIVcc, AllIssueSlots.rid, 2, 37-1 },
-
- //
+
+ //
// SDIVX inserts 68 bubbles.
- //
+ //
{ V9::SDIVX, AllIssueSlots.rid, 2, 68-1 },
{ V9::SDIVX, AllIssueSlots.rid, 2, 68-1 },
{ V9::SDIVX, AllIssueSlots.rid, 2, 68-1 },
{ V9::SDIVX, AllIssueSlots.rid, 2, 68-1 },
-
- //
+
+ //
// UDIVX inserts 68 bubbles.
- //
+ //
{ V9::UDIVX, AllIssueSlots.rid, 2, 68-1 },
{ V9::UDIVX, AllIssueSlots.rid, 2, 68-1 },
{ V9::UDIVX, AllIssueSlots.rid, 2, 68-1 },
{ V9::UDIVX, AllIssueSlots.rid, 2, 68-1 },
-
- //
+
+ //
// WR inserts 4 bubbles.
- //
+ //
//{ V9::WR, AllIssueSlots.rid, 2, 68-1 },
//{ V9::WR, AllIssueSlots.rid, 2, 68-1 },
//{ V9::WR, AllIssueSlots.rid, 2, 68-1 },
//{ V9::WR, AllIssueSlots.rid, 2, 68-1 },
-
- //
+
+ //
// WRPR inserts 4 bubbles.
- //
+ //
//{ V9::WRPR, AllIssueSlots.rid, 2, 68-1 },
//{ V9::WRPR, AllIssueSlots.rid, 2, 68-1 },
//{ V9::WRPR, AllIssueSlots.rid, 2, 68-1 },
//{ V9::WRPR, AllIssueSlots.rid, 2, 68-1 },
-
- //
+
+ //
// DONE inserts 9 bubbles.
- //
+ //
//{ V9::DONE, AllIssueSlots.rid, 2, 9-1 },
//{ V9::DONE, AllIssueSlots.rid, 2, 9-1 },
//{ V9::DONE, AllIssueSlots.rid, 2, 9-1 },
//{ V9::DONE, AllIssueSlots.rid, 2, 9-1 },
-
- //
+
+ //
// RETRY inserts 9 bubbles.
- //
+ //
//{ V9::RETRY, AllIssueSlots.rid, 2, 9-1 },
//{ V9::RETRY, AllIssueSlots.rid, 2, 9-1 },
//{ V9::RETRY, AllIssueSlots.rid, 2, 9-1 },
// branch. The group will stall until the load returns.
//11. Single-prec. FP loads lock 2 registers, for dependency checking.
//
-//
+//
// Additional delays we cannot or will not capture:
// 1. If DCTI is last word of cache line, it is delayed until next line can be
// fetched. Also, other DCTI alignment-related delays (pg 352)
//---------------------------------------------------------------------------
-// class SparcV9SchedInfo
-//
+// class SparcV9SchedInfo
+//
// Purpose:
// Scheduling information for the UltraSPARC.
// Primarily just initializes machine-dependent parameters in
SparcV9SchedInfo::SparcV9SchedInfo(const TargetMachine& tgt)
: TargetSchedInfo(tgt,
(unsigned int) SPARC_NUM_SCHED_CLASSES,
- SparcV9RUsageDesc,
- SparcV9InstrUsageDeltas,
- SparcV9InstrIssueDeltas,
- sizeof(SparcV9InstrUsageDeltas)/sizeof(InstrRUsageDelta),
- sizeof(SparcV9InstrIssueDeltas)/sizeof(InstrIssueDelta))
+ SparcV9RUsageDesc,
+ SparcV9InstrUsageDeltas,
+ SparcV9InstrIssueDeltas,
+ sizeof(SparcV9InstrUsageDeltas)/sizeof(InstrRUsageDelta),
+ sizeof(SparcV9InstrIssueDeltas)/sizeof(InstrIssueDelta))
{
maxNumIssueTotal = 4;
- longestIssueConflict = 0; // computed from issuesGaps[]
-
- branchMispredictPenalty = 4; // 4 for SPARC IIi
- branchTargetUnknownPenalty = 2; // 2 for SPARC IIi
- l1DCacheMissPenalty = 8; // 7 or 9 for SPARC IIi
- l1ICacheMissPenalty = 8; // ? for SPARC IIi
-
- inOrderLoads = true; // true for SPARC IIi
- inOrderIssue = true; // true for SPARC IIi
- inOrderExec = false; // false for most architectures
- inOrderRetire= true; // true for most architectures
-
+ longestIssueConflict = 0; // computed from issuesGaps[]
+
// must be called after above parameters are initialized.
initializeResources();
}
{
// Compute TargetSchedInfo::instrRUsages and TargetSchedInfo::issueGaps
TargetSchedInfo::initializeResources();
-
+
// Machine-dependent fixups go here. None for now.
}
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