PowerPCInstrInfo has gone away, PPC32 and PPC64 share opcodes.

[oota-llvm.git] / lib / Target / SparcV9 / SparcV9SchedInfo.cpp

diff --git a/lib/Target/SparcV9/SparcV9SchedInfo.cpp b/lib/Target/SparcV9/SparcV9SchedInfo.cpp
index fd03ad69d679379ed46b65961629085bfef9c69f..f9888f387f11a6460cbde57278f8ebabf9b4f274 100644 (file)
--- a/lib/Target/SparcV9/SparcV9SchedInfo.cpp
+++ b/lib/Target/SparcV9/SparcV9SchedInfo.cpp
@@ -1,4 +1,4 @@
-//===-- UltraSparcSchedInfo.cpp -------------------------------------------===//
+//===-- SparcV9SchedInfo.cpp ----------------------------------------------===//
 // 
 //                     The LLVM Compiler Infrastructure
 //
@@ -7,11 +7,13 @@
 // 
 //===----------------------------------------------------------------------===//
 //
-// Describe the scheduling characteristics of the UltraSparc
+// Describe the scheduling characteristics of the UltraSparc IIi.
 //
 //===----------------------------------------------------------------------===//
 
-#include "SparcInternals.h"
+#include "SparcV9Internals.h"
+
+using namespace llvm;
 
 /*---------------------------------------------------------------------------
 Scheduling guidelines for SPARC IIi:
@@ -127,7 +129,7 @@ static const CPUResource  FCMPDelayCycle("FCMP delay cycle", 1);
 
 
 //---------------------------------------------------------------------------
-// const InstrClassRUsage SparcRUsageDesc[]
+// const InstrClassRUsage SparcV9RUsageDesc[]
 // 
 // Purpose:
 //   Resource usage information for instruction in each scheduling class.
@@ -394,7 +396,7 @@ static const InstrClassRUsage SingleClassRUsage = {
 };
 
 
-static const InstrClassRUsage SparcRUsageDesc[] = {
+static const InstrClassRUsage SparcV9RUsageDesc[] = {
   NoneClassRUsage,
   IEUNClassRUsage,
   IEU0ClassRUsage,
@@ -410,14 +412,14 @@ static const InstrClassRUsage SparcRUsageDesc[] = {
 
 
 //---------------------------------------------------------------------------
-// const InstrIssueDelta  SparcInstrIssueDeltas[]
+// const InstrIssueDelta  SparcV9InstrIssueDeltas[]
 // 
 // Purpose:
 //   Changes to issue restrictions information in InstrClassRUsage for
 //   instructions that differ from other instructions in their class.
 //---------------------------------------------------------------------------
 
-static const InstrIssueDelta  SparcInstrIssueDeltas[] = {
+static const InstrIssueDelta  SparcV9InstrIssueDeltas[] = {
 
   // opCode,  isSingleIssue,  breaksGroup,  numBubbles
 
@@ -455,8 +457,6 @@ static const InstrIssueDelta  SparcInstrIssueDeltas[] = {
 //{ V9::FLUSH,         true,   true,   9 },
 //{ V9::FLUSHW,                true,   true,   9 },
 //{ V9::ALIGNADDR,     true,   true,   0 },
-  { V9::RETURNr,       true,   true,   0 },
-  { V9::RETURNi,       true,   true,   0 },
 //{ V9::DONE,          true,   true,   0 },
 //{ V9::RETRY,         true,   true,   0 },
 //{ V9::TCC,           true,   true,   0 },
@@ -502,14 +502,14 @@ static const InstrIssueDelta  SparcInstrIssueDeltas[] = {
 
 
 //---------------------------------------------------------------------------
-// const InstrRUsageDelta SparcInstrUsageDeltas[]
+// const InstrRUsageDelta SparcV9InstrUsageDeltas[]
 // 
 // Purpose:
 //   Changes to resource usage information in InstrClassRUsage for
 //   instructions that differ from other instructions in their class.
 //---------------------------------------------------------------------------
 
-static const InstrRUsageDelta SparcInstrUsageDeltas[] = {
+static const InstrRUsageDelta SparcV9InstrUsageDeltas[] = {
 
   // MachineOpCode, Resource, Start cycle, Num cycles
 
@@ -599,7 +599,7 @@ static const InstrRUsageDelta SparcInstrUsageDeltas[] = {
 #ifdef EXPLICIT_BUBBLES_NEEDED
   // 
   // MULScc inserts one bubble.
-  // This means it breaks the current group (captured in UltraSparcSchedInfo)
+  // This means it breaks the current group (captured in UltraSparcV9SchedInfo)
   // *and occupies all issue slots for the next cycle
   // 
 //{ V9::MULScc,  AllIssueSlots.rid, 2, 2-1 },
@@ -726,7 +726,7 @@ static const InstrRUsageDelta SparcInstrUsageDeltas[] = {
 
 
 //---------------------------------------------------------------------------
-// class UltraSparcSchedInfo 
+// class SparcV9SchedInfo 
 // 
 // Purpose:
 //   Scheduling information for the UltraSPARC.
@@ -735,34 +735,24 @@ static const InstrRUsageDelta SparcInstrUsageDeltas[] = {
 //---------------------------------------------------------------------------
 
 /*ctor*/
-UltraSparcSchedInfo::UltraSparcSchedInfo(const TargetMachine& tgt)
+SparcV9SchedInfo::SparcV9SchedInfo(const TargetMachine& tgt)
   : TargetSchedInfo(tgt,
                      (unsigned int) SPARC_NUM_SCHED_CLASSES,
-                    SparcRUsageDesc,
-                    SparcInstrUsageDeltas,
-                    SparcInstrIssueDeltas,
-                    sizeof(SparcInstrUsageDeltas)/sizeof(InstrRUsageDelta),
-                    sizeof(SparcInstrIssueDeltas)/sizeof(InstrIssueDelta))
+                    SparcV9RUsageDesc,
+                    SparcV9InstrUsageDeltas,
+                    SparcV9InstrIssueDeltas,
+                    sizeof(SparcV9InstrUsageDeltas)/sizeof(InstrRUsageDelta),
+                    sizeof(SparcV9InstrIssueDeltas)/sizeof(InstrIssueDelta))
 {
   maxNumIssueTotal = 4;
   longestIssueConflict = 0;            // computed from issuesGaps[]
   
-  branchMispredictPenalty = 4;         // 4 for SPARC IIi
-  branchTargetUnknownPenalty = 2;      // 2 for SPARC IIi
-  l1DCacheMissPenalty = 8;             // 7 or 9 for SPARC IIi
-  l1ICacheMissPenalty = 8;             // ? for SPARC IIi
-  
-  inOrderLoads = true;                 // true for SPARC IIi
-  inOrderIssue = true;                 // true for SPARC IIi
-  inOrderExec  = false;                        // false for most architectures
-  inOrderRetire= true;                 // true for most architectures
-  
   // must be called after above parameters are initialized.
   initializeResources();
 }
 
 void
-UltraSparcSchedInfo::initializeResources()
+SparcV9SchedInfo::initializeResources()
 {
   // Compute TargetSchedInfo::instrRUsages and TargetSchedInfo::issueGaps
   TargetSchedInfo::initializeResources();