-// $Id$
-//***************************************************************************
-// File:
-// Sparc.cpp
-//
-// Purpose:
-//
-// History:
-// 7/15/01 - Vikram Adve - Created
-//**************************************************************************/
+//===-- Sparc.cpp - General implementation file for the Sparc Target ------===//
+//
+// This file contains the code for the Sparc Target that does not fit in any of
+// the other files in this directory.
+//
+//===----------------------------------------------------------------------===//
-#include "llvm/Target/Sparc.h"
#include "SparcInternals.h"
-#include "llvm/Method.h"
-#include "llvm/CodeGen/InstrScheduling.h"
+#include "llvm/Target/TargetMachineImpls.h"
+#include "llvm/Function.h"
+#include "llvm/PassManager.h"
+#include "llvm/Transforms/Scalar.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/PreSelection.h"
+#include "llvm/CodeGen/StackSlots.h"
+#include "llvm/CodeGen/PeepholeOpts.h"
#include "llvm/CodeGen/InstrSelection.h"
+#include "llvm/CodeGen/InstrScheduling.h"
+#include "llvm/CodeGen/RegisterAllocation.h"
+#include "llvm/CodeGen/MachineCodeForInstruction.h"
+#include "llvm/Reoptimizer/Mapping/MappingInfo.h"
+#include "llvm/Reoptimizer/Mapping/FInfo.h"
+#include "Support/CommandLine.h"
+using std::cerr;
+
+// Build the MachineInstruction Description Array...
+const MachineInstrDescriptor SparcMachineInstrDesc[] = {
+#define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
+ NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
+ { OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
+ NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS, 0 },
+#include "SparcInstr.def"
+};
+
+//---------------------------------------------------------------------------
+// Command line options to control choice of code generation passes.
+//---------------------------------------------------------------------------
-#include "llvm/Analysis/LiveVar/MethodLiveVarInfo.h"
-#include "llvm/CodeGen/PhyRegAlloc.h"
+static cl::opt<bool> DisablePreSelect("nopreselect",
+ cl::desc("Disable preselection pass"));
+static cl::opt<bool> DisableSched("nosched",
+ cl::desc("Disable local scheduling pass"));
-//***************************** Internal Functions *************************/
+static cl::opt<bool> DisablePeephole("nopeephole",
+ cl::desc("Disable peephole optimization pass"));
//----------------------------------------------------------------------------
// allocateSparcTargetMachine - Allocate and return a subclass of TargetMachine
// that implements the Sparc backend. (the llvm/CodeGen/Sparc.h interface)
//----------------------------------------------------------------------------
-//
-TargetMachine *allocateSparcTargetMachine() { return new UltraSparc(); }
-
-
-//----------------------------------------------------------------------------
-// Entry point for register allocation for a module
-//----------------------------------------------------------------------------
-
-bool
-AllocateRegisters(Method *M, TargetMachine &TM)
-{
-
- if ( (M)->isExternal() ) // don't process prototypes
- return false;
-
- if( DEBUG_RA ) {
- cout << endl << "******************** Method "<< (M)->getName();
- cout << " ********************" <<endl;
- }
-
- MethodLiveVarInfo LVI(M ); // Analyze live varaibles
- LVI.analyze();
-
-
- PhyRegAlloc PRA(M, TM , &LVI); // allocate registers
- PRA.allocateRegisters();
-
-
- if( DEBUG_RA ) cout << endl << "Register allocation complete!" << endl;
- return false;
-}
+TargetMachine *allocateSparcTargetMachine() { return new UltraSparc(); }
-//***************************** External Classes **************************/
//---------------------------------------------------------------------------
-// class UltraSparcInstrInfo
+// class UltraSparcFrameInfo
//
// Purpose:
-// Information about individual instructions.
-// Most information is stored in the SparcMachineInstrDesc array above.
-// Other information is computed on demand, and most such functions
-// default to member functions in base class MachineInstrInfo.
+// Interface to stack frame layout info for the UltraSPARC.
+// Starting offsets for each area of the stack frame are aligned at
+// a multiple of getStackFrameSizeAlignment().
//---------------------------------------------------------------------------
-/*ctor*/
-UltraSparcInstrInfo::UltraSparcInstrInfo()
- : MachineInstrInfo(SparcMachineInstrDesc,
- /*descSize = */ NUM_TOTAL_OPCODES,
- /*numRealOpCodes = */ NUM_REAL_OPCODES)
+int
+UltraSparcFrameInfo::getFirstAutomaticVarOffset(MachineFunction& ,
+ bool& pos) const
{
+ pos = false; // static stack area grows downwards
+ return StaticAreaOffsetFromFP;
}
-
-//---------------------------------------------------------------------------
-// class UltraSparcSchedInfo
-//
-// Purpose:
-// Scheduling information for the UltraSPARC.
-// Primarily just initializes machine-dependent parameters in
-// class MachineSchedInfo.
-//---------------------------------------------------------------------------
-
-/*ctor*/
-UltraSparcSchedInfo::UltraSparcSchedInfo(const MachineInstrInfo* mii)
- : MachineSchedInfo((unsigned int) SPARC_NUM_SCHED_CLASSES,
- mii,
- SparcRUsageDesc,
- SparcInstrUsageDeltas,
- SparcInstrIssueDeltas,
- sizeof(SparcInstrUsageDeltas)/sizeof(InstrRUsageDelta),
- sizeof(SparcInstrIssueDeltas)/sizeof(InstrIssueDelta))
+int
+UltraSparcFrameInfo::getRegSpillAreaOffset(MachineFunction& mcInfo,
+ bool& pos) const
{
- maxNumIssueTotal = 4;
- longestIssueConflict = 0; // computed from issuesGaps[]
-
- branchMispredictPenalty = 4; // 4 for SPARC IIi
- branchTargetUnknownPenalty = 2; // 2 for SPARC IIi
- l1DCacheMissPenalty = 8; // 7 or 9 for SPARC IIi
- l1ICacheMissPenalty = 8; // ? for SPARC IIi
+ mcInfo.freezeAutomaticVarsArea(); // ensure no more auto vars are added
- inOrderLoads = true; // true for SPARC IIi
- inOrderIssue = true; // true for SPARC IIi
- inOrderExec = false; // false for most architectures
- inOrderRetire= true; // true for most architectures
-
- // must be called after above parameters are initialized.
- this->initializeResources();
+ pos = false; // static stack area grows downwards
+ unsigned int autoVarsSize = mcInfo.getAutomaticVarsSize();
+ return StaticAreaOffsetFromFP - autoVarsSize;
}
-void
-UltraSparcSchedInfo::initializeResources()
+int
+UltraSparcFrameInfo::getTmpAreaOffset(MachineFunction& mcInfo,
+ bool& pos) const
{
- // Compute MachineSchedInfo::instrRUsages and MachineSchedInfo::issueGaps
- MachineSchedInfo::initializeResources();
+ mcInfo.freezeAutomaticVarsArea(); // ensure no more auto vars are added
+ mcInfo.freezeSpillsArea(); // ensure no more spill slots are added
- // Machine-dependent fixups go here. None for now.
+ pos = false; // static stack area grows downwards
+ unsigned int autoVarsSize = mcInfo.getAutomaticVarsSize();
+ unsigned int spillAreaSize = mcInfo.getRegSpillsSize();
+ int offset = autoVarsSize + spillAreaSize;
+ return StaticAreaOffsetFromFP - offset;
}
-
-
-
-
-//---------------------------------------------------------------------------
-// UltraSparcRegInfo
-// Purpose:
-// This method will color incoming args to a method. If there are more
-// args than that can fit in regs, code will be inserted to pop them from
-// stack
-//---------------------------------------------------------------------------
-
-
-void UltraSparcRegInfo::colorArgs(const Method *const Meth,
- LiveRangeInfo& LRI) const
+int
+UltraSparcFrameInfo::getDynamicAreaOffset(MachineFunction& mcInfo,
+ bool& pos) const
{
-
- // get the argument list
- const Method::ArgumentListType& ArgList = Meth->getArgumentList();
- // get an iterator to arg list
- Method::ArgumentListType::const_iterator ArgIt = ArgList.begin();
- unsigned intArgNo=0;
-
- // to keep track of which float regs are allocated for argument passing
- bool FloatArgUsedArr[NumOfFloatArgRegs];
-
- // init float arg used array
- for(unsigned i=0; i < NumOfFloatArgRegs; ++i)
- FloatArgUsedArr[i] = false;
-
- // for each argument
- for( ; ArgIt != ArgList.end() ; ++ArgIt) {
-
- // get the LR of arg
- LiveRange *const LR = LRI.getLiveRangeForValue((const Value *) *ArgIt);
- unsigned RegClassID = (LR->getRegClass())->getID();
-
- // if the arg is in int class - allocate a reg for an int arg
- if( RegClassID == IntRegClassID ) {
-
- if( intArgNo < NumOfIntArgRegs) {
- LR->setColor( SparcIntRegOrder::i0 + intArgNo );
-
- if( DEBUG_RA) printReg( LR );
- }
-
- else {
- // TODO: Insert push code here
- assert( 0 && "Insert push code here!");
- }
- ++intArgNo;
- }
-
- // if the arg is float/double
- else if ( RegClassID == FloatRegClassID) {
-
- if( LR->getTypeID() == Type::DoubleTyID ) {
-
- // find the first reg # we can pass a double arg
- for(unsigned i=0; i < NumOfFloatArgRegs; i+= 2) {
- if ( !FloatArgUsedArr[i] && !FloatArgUsedArr[i+1] ) {
- LR->setColor( SparcFloatRegOrder::f0 + i );
- FloatArgUsedArr[i] = true;
- FloatArgUsedArr[i+1] = true;
- if( DEBUG_RA) printReg( LR );
- break;
- }
- }
- if( ! LR->hasColor() ) { // if LR was not colored above
-
- assert(0 && "insert push code here for a double");
-
- }
-
- }
- else if( LR->getTypeID() == Type::FloatTyID ) {
-
- // find the first reg # we can pass a float arg
- for(unsigned i=0; i < NumOfFloatArgRegs; ++i) {
- if ( !FloatArgUsedArr[i] ) {
- LR->setColor( SparcFloatRegOrder::f0 + i );
- FloatArgUsedArr[i] = true;
- if( DEBUG_RA) printReg( LR );
- break;
- }
- }
- if( ! LR->hasColor() ) { // if LR was not colored above
- assert(0 && "insert push code here for a float");
- }
-
- }
- else
- assert(0 && "unknown float type in method arg");
-
- } // float register class
-
- else
- assert(0 && "Unknown RegClassID");
- }
-
+ // Dynamic stack area grows downwards starting at top of opt-args area.
+ // The opt-args, required-args, and register-save areas are empty except
+ // during calls and traps, so they are shifted downwards on each
+ // dynamic-size alloca.
+ pos = false;
+ unsigned int optArgsSize = mcInfo.getMaxOptionalArgsSize();
+ if (int extra = optArgsSize % getStackFrameSizeAlignment())
+ optArgsSize += (getStackFrameSizeAlignment() - extra);
+ int offset = optArgsSize + FirstOptionalOutgoingArgOffsetFromSP;
+ assert((offset - OFFSET) % getStackFrameSizeAlignment() == 0);
+ return offset;
}
-
-
-
-
-
-void UltraSparcRegInfo::printReg(const LiveRange *const LR) {
-
- unsigned RegClassID = (LR->getRegClass())->getID();
-
- cout << " *Node " << (LR->getUserIGNode())->getIndex();
-
- if( ! LR->hasColor() ) {
- cout << " - could not find a color" << endl;
- return;
- }
-
- // if a color is found
-
- cout << " colored with color "<< LR->getColor();
-
- if( RegClassID == IntRegClassID ) {
-
- cout<< " [" << SparcIntRegOrder::getRegName(LR->getColor()) ;
- cout << "]" << endl;
- }
- else if ( RegClassID == FloatRegClassID) {
- cout << "[" << SparcFloatRegOrder::getRegName(LR->getColor());
- if( LR->getTypeID() == Type::DoubleTyID )
- cout << "+" << SparcFloatRegOrder::getRegName(LR->getColor()+1);
- cout << "]" << endl;
- }
-
-
-}
-
-
-void UltraSparcRegInfo::colorCallArgs(vector<const Instruction *> &
- CallInstrList, LiveRangeInfo& LRI,
- AddedInstrMapType &AddedInstrMap) const
-{
-
- vector<const Instruction *>::const_iterator InstIt = CallInstrList.begin();
-
- for( ; InstIt != CallInstrList.end(); ++InstIt) {
-
- // Inst = LLVM call instruction
- const Instruction *const CallI = *InstIt;
-
- MachineCodeForVMInstr & MInstVec = CallI->getMachineInstrVec();
- MachineCodeForVMInstr::const_iterator MIIt = MInstVec.begin();
-
- // find the CALL/JMMPL machine instruction
- for( ; MIIt != MInstVec.end() &&
- ! getUltraSparcInfo().getInstrInfo().isCall((*MIIt)->getOpCode());
- ++MIIt );
-
- assert( (MIIt != MInstVec.end()) && "CALL/JMPL not found");
-
- // CallMI = CALL/JMPL machine isntruction
- const MachineInstr *const CallMI = *MIIt;
-
- Instruction::op_const_iterator OpIt = CallI->op_begin();
-
- unsigned intArgNo=0;
- //unsigned NumOfCallInterfs = LR->getNumOfCallInterferences();
-
- // to keep track of which float regs are allocated for argument passing
- bool FloatArgUsedArr[NumOfFloatArgRegs];
-
- // init float arg used array
- for(unsigned i=0; i < NumOfFloatArgRegs; ++i)
- FloatArgUsedArr[i] = false;
-
- // go thru all the operands of LLVM instruction
- for( ; OpIt != CallI->op_end(); ++OpIt ) {
-
- // get the LR of call operand (parameter)
- LiveRange *const LR = LRI.getLiveRangeForValue((const Value *) *OpIt);
-
- if ( !LR ) {
- cout << " Warning: In call instr, no LR for arg: " ;
- printValue(*OpIt);
- cout << endl;
- continue;
- }
-
- unsigned RegClassID = (LR->getRegClass())->getID();
-
- // if the arg is in int class - allocate a reg for an int arg
- if( RegClassID == IntRegClassID ) {
-
- if( intArgNo < NumOfIntArgRegs) {
- setCallArgColor( LR, SparcIntRegOrder::o0 + intArgNo );
- }
-
- else {
- // TODO: Insert push code here
- assert( 0 && "Insert push code here!");
-
- AddedInstrns * AI = AddedInstrMap[ CallMI ];
- if( ! AI ) AI = new AddedInstrns();
-
- // AI->InstrnsBefore.push_back( getStackPushInstr(LR) );
- AddedInstrMap[ CallMI ] = AI;
-
- }
- ++intArgNo;
- }
-
- // if the arg is float/double
- else if ( RegClassID == FloatRegClassID) {
-
- if( LR->getTypeID() == Type::DoubleTyID ) {
-
- // find the first reg # we can pass a double arg
- for(unsigned i=0; i < NumOfFloatArgRegs; i+= 2) {
- if ( !FloatArgUsedArr[i] && !FloatArgUsedArr[i+1] ) {
- setCallArgColor(LR, SparcFloatRegOrder::f0 + i );
- FloatArgUsedArr[i] = true;
- FloatArgUsedArr[i+1] = true;
- //if( DEBUG_RA) printReg( LR );
- break;
- }
- }
- if( ! LR->hasColor() ) { // if LR was not colored above
-
- assert(0 && "insert push code here for a double");
-
- }
-
- }
- else if( LR->getTypeID() == Type::FloatTyID ) {
-
- // find the first reg # we can pass a float arg
- for(unsigned i=0; i < NumOfFloatArgRegs; ++i) {
- if ( !FloatArgUsedArr[i] ) {
- setCallArgColor(LR, SparcFloatRegOrder::f0 + i );
- FloatArgUsedArr[i] = true;
- // LR->setColor( SparcFloatRegOrder::f0 + i );
- // if( DEBUG_RA) printReg( LR );
- break;
- }
- }
- if( ! LR->hasColor() ) { // if LR was not colored above
- assert(0 && "insert push code here for a float");
- }
-
- }
- else
- assert(0 && "unknown float type in method arg");
-
- } // float register class
-
- else
- assert(0 && "Unknown RegClassID");
-
-
- } // for each operand in a call instruction
-
-
-
-
- } // for all call instrctions in CallInstrList
-
-}
-
-
-void UltraSparcRegInfo::setCallArgColor(LiveRange *const LR,
- const unsigned RegNo) const {
-
- // if no call interference and LR is NOT previously colored (e.g., as an
- // incoming arg)
- if( ! LR->getNumOfCallInterferences() && ! LR->hasColor() ) {
- // we can directly allocate a %o register
- LR->setColor( RegNo);
- if( DEBUG_RA) printReg( LR );
- }
- else { // there are call interferences
-
- /*
- // insert a copy machine instr to copy from LR to %o(reg)
- PreMInstrMap[ CallMI ] =
- getNewCopyMInstr( LR->, SparcIntRegOrder::o0 + intArgNo );
- */
- cout << " $$$ TODO: Insert a copy for call argument!: " << endl;
-
- // We don't color LR here. It's colored as any other normal LR
- }
-
-}
-
-
-
-
-
//---------------------------------------------------------------------------
// class UltraSparcMachine
//
//---------------------------------------------------------------------------
UltraSparc::UltraSparc()
- : TargetMachine("UltraSparc-Native"),
- instrInfo(),
- schedInfo(&instrInfo),
- regInfo( this )
-{
- optSizeForSubWordData = 4;
- minMemOpWordSize = 8;
- maxAtomicMemOpWordSize = 8;
+ : TargetMachine("UltraSparc-Native", 4),
+ schedInfo(*this),
+ regInfo(*this),
+ frameInfo(*this),
+ cacheInfo(*this),
+ optInfo(*this) {
}
-bool
-UltraSparc::compileMethod(Method *M)
+// addPassesToEmitAssembly - This method controls the entire code generation
+// process for the ultra sparc.
+//
+bool UltraSparc::addPassesToEmitAssembly(PassManager &PM, std::ostream &Out)
{
- if (SelectInstructionsForMethod(M, *this))
- {
- cerr << "Instruction selection failed for method " << M->getName()
- << "\n\n";
- return true;
- }
-
- if (ScheduleInstructionsWithSSA(M, *this))
+ // Construct and initialize the MachineFunction object for this fn.
+ PM.add(createMachineCodeConstructionPass(*this));
+
+ //Insert empty stackslots in the stack frame of each function
+ //so %fp+offset-8 and %fp+offset-16 are empty slots now!
+ PM.add(createStackSlotsPass(*this));
+
+ // Specialize LLVM code for this target machine and then
+ // run basic dataflow optimizations on LLVM code.
+ if (!DisablePreSelect)
{
- cerr << "Instruction scheduling before allocation failed for method "
- << M->getName() << "\n\n";
- return true;
+ PM.add(createPreSelectionPass(*this));
+ /* PM.add(createReassociatePass()); */
+ PM.add(createLICMPass());
+ PM.add(createGCSEPass());
}
-
- // if (AllocateRegisters(M, *this)) // allocate registers
- // {
- // cerr << "Register allocation failed for method "
- // << M->getName() << "\n\n";
- // return true;
- // }
-
+
+ PM.add(createInstructionSelectionPass(*this));
+
+ if (!DisableSched)
+ PM.add(createInstructionSchedulingWithSSAPass(*this));
+
+ PM.add(getRegisterAllocator(*this));
+
+ PM.add(getPrologEpilogInsertionPass());
+
+ if (!DisablePeephole)
+ PM.add(createPeepholeOptsPass(*this));
+
+ PM.add(MappingInfoForFunction(Out));
+
+ // Output assembly language to the .s file. Assembly emission is split into
+ // two parts: Function output and Global value output. This is because
+ // function output is pipelined with all of the rest of code generation stuff,
+ // allowing machine code representations for functions to be free'd after the
+ // function has been emitted.
+ //
+ PM.add(getFunctionAsmPrinterPass(Out));
+ PM.add(createMachineCodeDestructionPass()); // Free stuff no longer needed
+
+ // Emit Module level assembly after all of the functions have been processed.
+ PM.add(getModuleAsmPrinterPass(Out));
+
+ // Emit bytecode to the assembly file into its special section next
+ PM.add(getEmitBytecodeToAsmPass(Out));
+ PM.add(getFunctionInfo(Out));
return false;
}
-
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