Add completely untested support for mtcrf/mfcrf encoding

[oota-llvm.git] / lib / Target / SparcV9 / SparcV9_F2.td

diff --git a/lib/Target/SparcV9/SparcV9_F2.td b/lib/Target/SparcV9/SparcV9_F2.td
index 69e4cac76c922c75f56d5b4af11eeb3bb471c5bf..3c9ae1e98a2b23bc610653fa325615e17079ea59 100644 (file)
--- a/lib/Target/SparcV9/SparcV9_F2.td
+++ b/lib/Target/SparcV9/SparcV9_F2.td
@@ -1,5 +1,10 @@
-//===- Sparc.td - Target Description for Sparc V9 Target --------*- C++ -*-===//
-// vim:ft=cpp
+//===- SparcV9_F2.td - SparcV9 Format 2 instructions -------*- tablegen -*-===//
+// 
+//                     The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// 
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
@@ -7,57 +12,60 @@
 //
 class F2 : InstV9 {                   // Format 2 instructions
   bits<3> op2;
-  set op = 0;    // Op = 0
-  set Inst{24-22} = op2;
+  let op          = 0;    // Op = 0
+  let Inst{24-22} = op2;
 }
 
 // Format 2.1 instructions
 class F2_1<string name> : F2 {
   bits<22> imm;
-  bits<5> rd;
+  bits<5>  rd;
 
-  set Name = name;
-  set Inst{29-25} = rd;
-  set Inst{21-0}  = imm;
+  let Name        = name;
+  let Inst{29-25} = rd;
+  let Inst{21-0}  = imm;
 }
 
 class F2_br : F2 {                    // Format 2 Branch instruction
-  bit annul;  // All branches have an annul bit
-  set Inst{29} = annul;
-  set isBranch    = 1;      // All instances are branch instructions
+  let isBranch    = 1;      // All instances are branch instructions
 }
 
 class F2_2<bits<4> cond, string name> : F2_br { // Format 2.2 instructions
   bits<22> disp;
+  bit      annul = 0; // currently unused by SparcV9 backend
 
-  set Name        = name;
-  set Inst{28-25} = cond;
-  set Inst{21-0}  = disp;
+  let Name        = name;
+  let Inst{29}    = annul;
+  let Inst{28-25} = cond;
+  let Inst{21-0}  = disp;
 }
 
 class F2_3<bits<4> cond, string name> : F2_br { // Format 2.3 instructions
-  bits<2> cc;
+  bits<2>  cc;
   bits<19> disp;
-  bit predict;
+  bit      predict = 1;
+  bit      annul = 0; // currently unused by SparcV9 backend
 
-  set Name        = name;
-  set Inst{28-25} = cond;
-  set Inst{21-20} = cc;
-  set Inst{19}    = predict;
-  set Inst{18-0}  = disp;
+  let Name        = name;
+  let Inst{29}    = annul;
+  let Inst{28-25} = cond;
+  let Inst{21-20} = cc;
+  let Inst{19}    = predict;
+  let Inst{18-0}  = disp;
 }
 
 class F2_4<bits<3> rcond, string name> : F2_br { // Format 2.4 instructions
-  bit        predict;
-  bits<5>    rs1;
-  bits<16>   disp;
-
-  set Name = name;
-  set Inst{28}    = 0;
-  set Inst{27-25} = rcond;
-  //  Inst{24-22} = op2 field
-  set Inst{21-20} = disp{15-14};
-  set Inst{19}    = predict;
-  set Inst{18-14} = rs1;
-  set Inst{13-0 } = disp{13-0};
+  bits<5>  rs1;
+  bits<16> disp;
+  bit      predict = 1;
+  bit      annul = 0; // currently unused by SparcV9 backend
+
+  let Name        = name;
+  let Inst{29}    = annul;
+  let Inst{28}    = 0;
+  let Inst{27-25} = rcond;
+  let Inst{21-20} = disp{15-14};
+  let Inst{19}    = predict;
+  let Inst{18-14} = rs1;
+  let Inst{13-0 } = disp{13-0};
 }