SHUFP* are two address code.

[oota-llvm.git] / lib / Target / SparcV9 / SparcV9_F4.td

diff --git a/lib/Target/SparcV9/SparcV9_F4.td b/lib/Target/SparcV9/SparcV9_F4.td
index 2a2e467c575e595f3144858d573657b34d4bbc5f..86cd30a37aef90d27318ab17ac7ceefe71570aba 100644 (file)
--- a/lib/Target/SparcV9/SparcV9_F4.td
+++ b/lib/Target/SparcV9/SparcV9_F4.td
@@ -1,5 +1,10 @@
-//===- Sparc.td - Target Description for Sparc V9 Target --------*- C++ -*-===//
-// vim:ft=cpp
+//===- SparcV9_F4.td - SparcV9 Format 4 instructions -------*- tablegen -*-===//
+// 
+//                     The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// 
 //===----------------------------------------------------------------------===//
 
 //----------------------- F4 classes -----------------------------------------
@@ -8,27 +13,25 @@
 // field.
 class F4 : InstV9 {
   bits<6> op3;
-  set Inst{24-19} = op3;
+  let Inst{24-19} = op3;
 }
 
 // F4_rs1 - Common class of instructions that use an rs1 field
 class F4_rs1 : F4 {
   bits<5> rs1;
-  //set Inst{29-25} = dontcare;
-  set Inst{18-14} = rs1;
+  let Inst{18-14} = rs1;
 }
 
 // F4_rs1rs2 - Common class of instructions that have rs1 and rs2 fields
 class F4_rs1rs2 : F4_rs1 {
   bits<5> rs2;
-  //set Inst{12-5} = dontcare;
-  set Inst{4-0} = rs2;
+  let Inst{4-0} = rs2;
 }
 
 // F4_rs1rs2rd - Common class of instructions that have 3 register operands
 class F4_rs1rs2rd : F4_rs1rs2 {
   bits<5> rd;
-  set Inst{29-25} = rd;
+  let Inst{29-25} = rd;
 }
 
 // F4_rs1rs2rd - Common class of instructions that have 2 reg and 1 imm operand
@@ -36,22 +39,22 @@ class F4_rs1simm11rd : F4_rs1 {
   bits<11> simm11;
   bits<5>  rd;
 
-  set Inst{10-0}  = simm11;
-  set Inst{29-25} = rd;
+  let Inst{10-0}  = simm11;
+  let Inst{29-25} = rd;
 }
 
 // F4_cc - Common class of instructions that have a cond field
 class F4_cond : F4 {
   bits<4> cond;
-  set Inst{17-14} = cond;
+  let Inst{17-14} = cond;
 }
 
 // F4_cc - Common class of instructions that have cc register as first operand
 class F4_condcc : F4_cond {
   bits<3> cc;
-  set Inst{18} = cc{2};
-  set Inst{12} = cc{1};
-  set Inst{11} = cc{0};
+  let Inst{18} = cc{2};
+  let Inst{12} = cc{1};
+  let Inst{11} = cc{0};
 }
 
 // Actual F4 instruction classes
@@ -59,60 +62,63 @@ class F4_condcc : F4_cond {
 class F4_1<bits<2> opVal, bits<6> op3Val, string name> : F4_rs1rs2rd {
   bits<2> cc;
 
-  set op = opVal;
-  set op3 = op3Val;
-  set Name = name;
-  set Inst{13} = 0; // i bit
-  set Inst{12-11} = cc;
-  //set Inst{10-5} = dontcare;
+  let op = opVal;
+  let op3 = op3Val;
+  let Name = name;
+  let Inst{13} = 0; // i bit
+  let Inst{12-11} = cc;
+  let Inst{10-5} = 0; // don't care
 }
 
 class F4_2<bits<2> opVal, bits<6> op3Val, string name> : F4_rs1simm11rd {
   bits<2> cc;
 
-  set op = opVal;
-  set op3 = op3Val;
-  set Name = name;
-  set Inst{13} = 1; // i bit
-  set Inst{12-11} = cc;
+  let op = opVal;
+  let op3 = op3Val;
+  let Name = name;
+  let Inst{13} = 1; // i bit
+  let Inst{12-11} = cc;
 }
 
 class F4_3<bits<2> opVal, bits<6> op3Val, bits<4> condVal,
            string name> : F4_condcc {
   bits<5> rs2;
+  bits<5> rd;
 
-  set op = opVal;
-  set op3 = op3Val;
-  set cond = condVal;
-  set Name = name;
-  set Inst{13} = 0; // i bit
-  //set Inst{10-5} = dontcare;
-  set Inst{4-0} = rs2;
+  let op = opVal;
+  let op3 = op3Val;
+  let cond = condVal;
+  let Name = name;
+  let Inst{29-25} = rd;
+  let Inst{13} = 0; // i bit
+  let Inst{10-5} = 0; // don't care
+  let Inst{4-0} = rs2;
 }
 
 class F4_4<bits<2> opVal, bits<6> op3Val, bits<4> condVal,
            string name> : F4_condcc {
-  bits<11> sim11;
+  bits<11> simm11;
   bits<5>  rd;
 
-  set op   = opVal;
-  set op3  = op3Val;
-  set cond = condVal;
-  set Name = name;
-  set Inst{13} = 1; // i bit
-  set Inst{10-0} = sim11;
+  let op   = opVal;
+  let op3  = op3Val;
+  let cond = condVal;
+  let Name = name;
+  let Inst{29-25} = rd;
+  let Inst{13} = 1; // i bit
+  let Inst{10-0} = simm11;
 }  
   
 // FIXME: class F4_5
 
 class F4_6<bits<2> opVal, bits<6> op3Val, bits<3> rcondVal,
            bits<5> opf_lowVal, string name> : F4_rs1rs2rd {
-  set op  = opVal;
-  set op3 = op3Val;
-  set Name = name;
-  set Inst{13} = 0;
-  set Inst{12-10} = rcondVal;
-  set Inst{9-5} = opf_lowVal;
+  let op  = opVal;
+  let op3 = op3Val;
+  let Name = name;
+  let Inst{13} = 0;
+  let Inst{12-10} = rcondVal;
+  let Inst{9-5} = opf_lowVal;
 }
 
 class F4_7<bits<2> opVal, bits<6> op3Val, bits<4> condVal,
@@ -121,15 +127,15 @@ class F4_7<bits<2> opVal, bits<6> op3Val, bits<4> condVal,
   bits<5> rs2;
   bits<5> rd;
 
-  set op   = opVal;
-  set op3  = op3Val;
-  set cond = condVal;
-  set Name = name;
-  set Inst{29-25} = rd;
-  set Inst{18}    = 0;
-  set Inst{13-11} = cc;
-  set Inst{10-5}  = opf_lowVal;
-  set Inst{4-0}   = rs2;
+  let op   = opVal;
+  let op3  = op3Val;
+  let cond = condVal;
+  let Name = name;
+  let Inst{29-25} = rd;
+  let Inst{18}    = 0;
+  let Inst{13-11} = cc;
+  let Inst{10-5}  = opf_lowVal;
+  let Inst{4-0}   = rs2;
 }
 
 // FIXME: F4 classes 8-9