ARM64: override all the things.

[oota-llvm.git] / lib / Target / SystemZ / README.txt

diff --git a/lib/Target/SystemZ/README.txt b/lib/Target/SystemZ/README.txt
index d5361fb658c0cc1cd956a4521150848ffc45b80c..e089047d013e8b7788ea1443abb9f1a8e4518117 100644 (file)
--- a/lib/Target/SystemZ/README.txt
+++ b/lib/Target/SystemZ/README.txt
@@ -58,14 +58,11 @@ condition codes.  For example, we could use LCDFR instead of LCDBR.
 
 --
 
-We don't optimize block memory operations, except using single MVCs
-for memcpy and single CLCs for memcmp.
+We only use MVC, XC and CLC for constant-length block operations.
+We could extend them to variable-length operations too,
+using EXECUTE RELATIVE LONG.
 
-It's definitely worth using things like NC, XC and OC with
-constant lengths.  MVCIN may be worthwhile too.
-
-We should probably implement general memcpy using MVC with EXECUTE.
-Likewise memcmp and CLC.  MVCLE and CLCLE could be useful too.
+MVCIN, MVCLE and CLCLE may be worthwhile too.
 
 --
 
@@ -93,8 +90,7 @@ We don't use the halfword forms of LOAD REVERSED and STORE REVERSED
 
 --
 
-We could take advantage of the various ... UNDER MASK instructions,
-such as ICM and STCM.
+We don't use ICM or STCM.
 
 --
 
@@ -170,13 +166,6 @@ See CodeGen/SystemZ/alloca-01.ll for an example.
 
 --
 
-Atomic loads and stores use the default compare-and-swap based implementation.
-This is much too conservative in practice, since the architecture guarantees
-that 1-, 2-, 4- and 8-byte loads and stores to aligned addresses are
-inherently atomic.
-
---
-
 If needed, we can support 16-byte atomics using LPQ, STPQ and CSDG.
 
 --