Replace the tablegen RegisterClass field SubRegClassList with an alist-like data

[oota-llvm.git] / lib / Target / SystemZ / SystemZCallingConv.td

diff --git a/lib/Target/SystemZ/SystemZCallingConv.td b/lib/Target/SystemZ/SystemZCallingConv.td
index 34670467f1cdbd4f808773075b2a68c12f511218..c799a9e501aa285f08f397bc0f60ed5d81151e9e 100644 (file)
--- a/lib/Target/SystemZ/SystemZCallingConv.td
+++ b/lib/Target/SystemZ/SystemZCallingConv.td
@@ -17,7 +17,11 @@ def RetCC_SystemZ : CallingConv<[
   CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
 
   // i64 is returned in register R2
-  CCIfType<[i64], CCAssignToReg<[R2D]>>
+  CCIfType<[i64], CCAssignToReg<[R2D, R3D, R4D, R5D]>>,
+
+  // f32 / f64 are returned in F0
+  CCIfType<[f32], CCAssignToReg<[F0S, F2S, F4S, F6S]>>,
+  CCIfType<[f64], CCAssignToReg<[F0L, F2L, F4L, F6L]>>
 ]>;
 
 //===----------------------------------------------------------------------===//
@@ -29,11 +33,14 @@ def CC_SystemZ : CallingConv<[
 
   // The first 5 integer arguments of non-varargs functions are passed in
   // integer registers.
-  // FIXME: Check stuff for varagrs
-  CCIfNotVarArg<CCIfType<[i64],
-                CCAssignToReg<[R2D, R3D, R4D, R5D, R6D]>>>,
+  CCIfType<[i64], CCAssignToReg<[R2D, R3D, R4D, R5D, R6D]>>,
+
+  // The first 4 floating point arguments of non-varargs functions are passed
+  // in FP registers.
+  CCIfType<[f32], CCAssignToReg<[F0S, F2S, F4S, F6S]>>,
+  CCIfType<[f64], CCAssignToReg<[F0L, F2L, F4L, F6L]>>,
 
   // Integer values get stored in stack slots that are 8 bytes in
   // size and 8-byte aligned.
-  CCIfType<[i64], CCAssignToStack<8, 8>>
+  CCIfType<[i64, f32, f64], CCAssignToStack<8, 8>>
 ]>;