//===----------------------------------------------------------------------===//
#include "SystemZ.h"
-#include "SystemZISelLowering.h"
#include "SystemZTargetMachine.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Function.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
using namespace llvm;
-static const unsigned subreg_even32 = 1;
-static const unsigned subreg_odd32 = 2;
-static const unsigned subreg_even = 3;
-static const unsigned subreg_odd = 4;
-
namespace {
/// SystemZRRIAddressMode - This corresponds to rriaddr, but uses SDValue's
/// instead of register numbers for the leaves of the matched tree.
}
void dump() {
- cerr << "SystemZRRIAddressMode " << this << '\n';
+ errs() << "SystemZRRIAddressMode " << this << '\n';
if (BaseType == RegBase) {
- cerr << "Base.Reg ";
- if (Base.Reg.getNode() != 0) Base.Reg.getNode()->dump();
- else cerr << "nul";
- cerr << '\n';
+ errs() << "Base.Reg ";
+ if (Base.Reg.getNode() != 0)
+ Base.Reg.getNode()->dump();
+ else
+ errs() << "nul";
+ errs() << '\n';
} else {
- cerr << " Base.FrameIndex " << Base.FrameIndex << '\n';
+ errs() << " Base.FrameIndex " << Base.FrameIndex << '\n';
}
if (!isRI) {
- cerr << "IndexReg ";
+ errs() << "IndexReg ";
if (IndexReg.getNode() != 0) IndexReg.getNode()->dump();
- else cerr << "nul";
+ else errs() << "nul";
}
- cerr << " Disp " << Disp << '\n';
+ errs() << " Disp " << Disp << '\n';
}
};
}
///
namespace {
class SystemZDAGToDAGISel : public SelectionDAGISel {
- SystemZTargetLowering &Lowering;
+ const SystemZTargetLowering &Lowering;
const SystemZSubtarget &Subtarget;
void getAddressOperandsRI(const SystemZRRIAddressMode &AM,
Lowering(*TM.getTargetLowering()),
Subtarget(*TM.getSubtargetImpl()) { }
- virtual void InstructionSelect();
-
virtual const char *getPassName() const {
return "SystemZ DAG->DAG Pattern Instruction Selection";
}
#include "SystemZGenDAGISel.inc"
private:
- bool SelectAddrRI12Only(SDValue Op, SDValue& Addr,
+ bool SelectAddrRI12Only(SDValue& Addr,
SDValue &Base, SDValue &Disp);
- bool SelectAddrRI12(SDValue Op, SDValue& Addr,
+ bool SelectAddrRI12(SDValue& Addr,
SDValue &Base, SDValue &Disp,
bool is12BitOnly = false);
- bool SelectAddrRI(SDValue Op, SDValue& Addr,
- SDValue &Base, SDValue &Disp);
- bool SelectAddrRRI12(SDValue Op, SDValue Addr,
+ bool SelectAddrRI(SDValue& Addr, SDValue &Base, SDValue &Disp);
+ bool SelectAddrRRI12(SDValue Addr,
SDValue &Base, SDValue &Disp, SDValue &Index);
- bool SelectAddrRRI20(SDValue Op, SDValue Addr,
+ bool SelectAddrRRI20(SDValue Addr,
SDValue &Base, SDValue &Disp, SDValue &Index);
- bool SelectLAAddr(SDValue Op, SDValue Addr,
+ bool SelectLAAddr(SDValue Addr,
SDValue &Base, SDValue &Disp, SDValue &Index);
- SDNode *Select(SDValue Op);
+ SDNode *Select(SDNode *Node);
- bool TryFoldLoad(SDValue P, SDValue N,
+ bool TryFoldLoad(SDNode *P, SDValue N,
SDValue &Base, SDValue &Disp, SDValue &Index);
bool MatchAddress(SDValue N, SystemZRRIAddressMode &AM,
bool is12Bit, unsigned Depth = 0);
bool MatchAddressBase(SDValue N, SystemZRRIAddressMode &AM);
- bool MatchAddressRI(SDValue N, SystemZRRIAddressMode &AM,
- bool is12Bit);
-
- #ifndef NDEBUG
- unsigned Indent;
- #endif
};
} // end anonymous namespace
bool SystemZDAGToDAGISel::MatchAddress(SDValue N, SystemZRRIAddressMode &AM,
bool is12Bit, unsigned Depth) {
DebugLoc dl = N.getDebugLoc();
- DOUT << "MatchAddress: "; DEBUG(AM.dump());
+ DEBUG(errs() << "MatchAddress: "; AM.dump());
// Limit recursion.
if (Depth > 5)
return MatchAddressBase(N, AM);
default: break;
case ISD::Constant: {
int64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
- int64_t Imm;
+ int64_t Imm = 0;
bool Match = (is12Bit ?
isImmZExt12(AM.Disp + Val, Imm) :
isImmSExt20(AM.Disp + Val, Imm));
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
SystemZRRIAddressMode Backup = AM;
int64_t Offset = CN->getSExtValue();
- int64_t Imm;
+ int64_t Imm = 0;
bool MatchOffset = (is12Bit ?
isImmZExt12(AM.Disp + Offset, Imm) :
isImmSExt20(AM.Disp + Offset, Imm));
/// Returns true if the address can be represented by a base register plus
/// an unsigned 12-bit displacement [r+imm].
-bool SystemZDAGToDAGISel::SelectAddrRI12Only(SDValue Op, SDValue& Addr,
+bool SystemZDAGToDAGISel::SelectAddrRI12Only(SDValue &Addr,
SDValue &Base, SDValue &Disp) {
- return SelectAddrRI12(Op, Addr, Base, Disp, /*is12BitOnly*/true);
+ return SelectAddrRI12(Addr, Base, Disp, /*is12BitOnly*/true);
}
-bool SystemZDAGToDAGISel::SelectAddrRI12(SDValue Op, SDValue& Addr,
+bool SystemZDAGToDAGISel::SelectAddrRI12(SDValue &Addr,
SDValue &Base, SDValue &Disp,
bool is12BitOnly) {
SystemZRRIAddressMode AM20(/*isRI*/true), AM12(/*isRI*/true);
if (AM12.Disp == 0 && AM20.Disp != 0)
return false;
- DOUT << "MatchAddress (final): "; DEBUG(AM12.dump());
+ DEBUG(errs() << "MatchAddress (final): "; AM12.dump());
- MVT VT = Addr.getValueType();
+ EVT VT = Addr.getValueType();
if (AM12.BaseType == SystemZRRIAddressMode::RegBase) {
if (!AM12.Base.Reg.getNode())
AM12.Base.Reg = CurDAG->getRegister(0, VT);
/// Returns true if the address can be represented by a base register plus
/// a signed 20-bit displacement [r+imm].
-bool SystemZDAGToDAGISel::SelectAddrRI(SDValue Op, SDValue& Addr,
+bool SystemZDAGToDAGISel::SelectAddrRI(SDValue& Addr,
SDValue &Base, SDValue &Disp) {
SystemZRRIAddressMode AM(/*isRI*/true);
bool Done = false;
if (!Done && MatchAddress(Addr, AM, /* is12Bit */ false))
return false;
- DOUT << "MatchAddress (final): "; DEBUG(AM.dump());
+ DEBUG(errs() << "MatchAddress (final): "; AM.dump());
- MVT VT = Addr.getValueType();
+ EVT VT = Addr.getValueType();
if (AM.BaseType == SystemZRRIAddressMode::RegBase) {
if (!AM.Base.Reg.getNode())
AM.Base.Reg = CurDAG->getRegister(0, VT);
/// Returns true if the address can be represented by a base register plus
/// index register plus an unsigned 12-bit displacement [base + idx + imm].
-bool SystemZDAGToDAGISel::SelectAddrRRI12(SDValue Op, SDValue Addr,
+bool SystemZDAGToDAGISel::SelectAddrRRI12(SDValue Addr,
SDValue &Base, SDValue &Disp, SDValue &Index) {
SystemZRRIAddressMode AM20, AM12;
bool Done = false;
if (AM12.Disp == 0 && AM20.Disp != 0)
return false;
- DOUT << "MatchAddress (final): "; DEBUG(AM12.dump());
+ DEBUG(errs() << "MatchAddress (final): "; AM12.dump());
- MVT VT = Addr.getValueType();
+ EVT VT = Addr.getValueType();
if (AM12.BaseType == SystemZRRIAddressMode::RegBase) {
if (!AM12.Base.Reg.getNode())
AM12.Base.Reg = CurDAG->getRegister(0, VT);
/// Returns true if the address can be represented by a base register plus
/// index register plus a signed 20-bit displacement [base + idx + imm].
-bool SystemZDAGToDAGISel::SelectAddrRRI20(SDValue Op, SDValue Addr,
+bool SystemZDAGToDAGISel::SelectAddrRRI20(SDValue Addr,
SDValue &Base, SDValue &Disp, SDValue &Index) {
SystemZRRIAddressMode AM;
bool Done = false;
if (!Done && MatchAddress(Addr, AM, /* is12Bit */ false))
return false;
- DOUT << "MatchAddress (final): "; DEBUG(AM.dump());
+ DEBUG(errs() << "MatchAddress (final): "; AM.dump());
- MVT VT = Addr.getValueType();
+ EVT VT = Addr.getValueType();
if (AM.BaseType == SystemZRRIAddressMode::RegBase) {
if (!AM.Base.Reg.getNode())
AM.Base.Reg = CurDAG->getRegister(0, VT);
/// SelectLAAddr - it calls SelectAddr and determines if the maximal addressing
/// mode it matches can be cost effectively emitted as an LA/LAY instruction.
-bool SystemZDAGToDAGISel::SelectLAAddr(SDValue Op, SDValue Addr,
+bool SystemZDAGToDAGISel::SelectLAAddr(SDValue Addr,
SDValue &Base, SDValue &Disp, SDValue &Index) {
SystemZRRIAddressMode AM;
if (MatchAddress(Addr, AM, false))
return false;
- MVT VT = Addr.getValueType();
+ EVT VT = Addr.getValueType();
unsigned Complexity = 0;
if (AM.BaseType == SystemZRRIAddressMode::RegBase)
if (AM.Base.Reg.getNode())
return false;
}
-bool SystemZDAGToDAGISel::TryFoldLoad(SDValue P, SDValue N,
+bool SystemZDAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N,
SDValue &Base, SDValue &Disp, SDValue &Index) {
if (ISD::isNON_EXTLoad(N.getNode()) &&
- N.hasOneUse() &&
- IsLegalAndProfitableToFold(N.getNode(), P.getNode(), P.getNode()))
- return SelectAddrRRI20(P, N.getOperand(1), Base, Disp, Index);
+ IsLegalToFold(N, P, P, OptLevel))
+ return SelectAddrRRI20(N.getOperand(1), Base, Disp, Index);
return false;
}
-/// InstructionSelect - This callback is invoked by
-/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
-void SystemZDAGToDAGISel::InstructionSelect() {
- DEBUG(BB->dump());
-
- // Codegen the basic block.
-#ifndef NDEBUG
- DOUT << "===== Instruction selection begins:\n";
- Indent = 0;
-#endif
- SelectRoot(*CurDAG);
-#ifndef NDEBUG
- DOUT << "===== Instruction selection ends:\n";
-#endif
-
- CurDAG->RemoveDeadNodes();
-}
-
-SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
- SDNode *Node = Op.getNode();
- MVT NVT = Node->getValueType(0);
- DebugLoc dl = Op.getDebugLoc();
+SDNode *SystemZDAGToDAGISel::Select(SDNode *Node) {
+ EVT NVT = Node->getValueType(0);
+ DebugLoc dl = Node->getDebugLoc();
unsigned Opcode = Node->getOpcode();
// Dump information about the Node being selected
- #ifndef NDEBUG
- DOUT << std::string(Indent, ' ') << "Selecting: ";
- DEBUG(Node->dump(CurDAG));
- DOUT << "\n";
- Indent += 2;
- #endif
+ DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
// If we have a custom node, we already have selected!
if (Node->isMachineOpcode()) {
- #ifndef NDEBUG
- DOUT << std::string(Indent-2, ' ') << "== ";
- DEBUG(Node->dump(CurDAG));
- DOUT << "\n";
- Indent -= 2;
- #endif
+ DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
return NULL; // Already selected.
}
SDValue N0 = Node->getOperand(0);
SDValue N1 = Node->getOperand(1);
- MVT ResVT;
+ EVT ResVT;
bool is32Bit = false;
- switch (NVT.getSimpleVT()) {
- default: assert(0 && "Unsupported VT!");
- case MVT::i32:
- Opc = SystemZ::SDIVREM32r; MOpc = SystemZ::SDIVREM32m;
- ResVT = MVT::v2i64;
- is32Bit = true;
- break;
- case MVT::i64:
- Opc = SystemZ::SDIVREM64r; MOpc = SystemZ::SDIVREM64m;
- ResVT = MVT::v2i64;
- break;
+ switch (NVT.getSimpleVT().SimpleTy) {
+ default: assert(0 && "Unsupported VT!");
+ case MVT::i32:
+ Opc = SystemZ::SDIVREM32r; MOpc = SystemZ::SDIVREM32m;
+ ResVT = MVT::v2i64;
+ is32Bit = true;
+ break;
+ case MVT::i64:
+ Opc = SystemZ::SDIVREM64r; MOpc = SystemZ::SDIVREM64m;
+ ResVT = MVT::v2i64;
+ break;
}
SDValue Tmp0, Tmp1, Tmp2;
- bool foldedLoad = TryFoldLoad(Op, N1, Tmp0, Tmp1, Tmp2);
+ bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2);
// Prepare the dividend
SDNode *Dividend;
if (is32Bit)
- Dividend = CurDAG->getTargetNode(SystemZ::MOVSX64rr32, dl, MVT::i64, N0);
+ Dividend = CurDAG->getMachineNode(SystemZ::MOVSX64rr32, dl, MVT::i64, N0);
else
Dividend = N0.getNode();
// Insert prepared dividend into suitable 'subreg'
- SDNode *Tmp = CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF,
- dl, ResVT);
+ SDNode *Tmp = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
+ dl, ResVT);
Dividend =
- CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT,
- SDValue(Tmp, 0), SDValue(Dividend, 0),
- CurDAG->getTargetConstant(subreg_odd, MVT::i32));
+ CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl, ResVT,
+ SDValue(Tmp, 0), SDValue(Dividend, 0),
+ CurDAG->getTargetConstant(SystemZ::subreg_odd, MVT::i32));
SDNode *Result;
SDValue DivVal = SDValue(Dividend, 0);
if (foldedLoad) {
SDValue Ops[] = { DivVal, Tmp0, Tmp1, Tmp2, N1.getOperand(0) };
- Result = CurDAG->getTargetNode(MOpc, dl, ResVT, Ops, array_lengthof(Ops));
+ Result = CurDAG->getMachineNode(MOpc, dl, ResVT, MVT::Other,
+ Ops, array_lengthof(Ops));
// Update the chain.
- ReplaceUses(N1.getValue(1), SDValue(Result, 0));
+ ReplaceUses(N1.getValue(1), SDValue(Result, 1));
} else {
- Result = CurDAG->getTargetNode(Opc, dl, ResVT, SDValue(Dividend, 0), N1);
+ Result = CurDAG->getMachineNode(Opc, dl, ResVT, SDValue(Dividend, 0), N1);
}
// Copy the division (odd subreg) result, if it is needed.
- if (!Op.getValue(0).use_empty()) {
- unsigned SubRegIdx = (is32Bit ? subreg_odd32 : subreg_odd);
- SDNode *Div = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
- dl, NVT,
- SDValue(Result, 0),
- CurDAG->getTargetConstant(SubRegIdx,
- MVT::i32));
-
- ReplaceUses(Op.getValue(0), SDValue(Div, 0));
- #ifndef NDEBUG
- DOUT << std::string(Indent-2, ' ') << "=> ";
- DEBUG(Result->dump(CurDAG));
- DOUT << "\n";
- #endif
+ if (!SDValue(Node, 0).use_empty()) {
+ unsigned SubRegIdx = (is32Bit ?
+ SystemZ::subreg_odd32 : SystemZ::subreg_odd);
+ SDNode *Div = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
+ dl, NVT,
+ SDValue(Result, 0),
+ CurDAG->getTargetConstant(SubRegIdx,
+ MVT::i32));
+
+ ReplaceUses(SDValue(Node, 0), SDValue(Div, 0));
+ DEBUG(errs() << "=> "; Result->dump(CurDAG); errs() << "\n");
}
// Copy the remainder (even subreg) result, if it is needed.
- if (!Op.getValue(1).use_empty()) {
- unsigned SubRegIdx = (is32Bit ? subreg_even32 : subreg_even);
- SDNode *Rem = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
- dl, NVT,
- SDValue(Result, 0),
- CurDAG->getTargetConstant(SubRegIdx,
- MVT::i32));
-
- ReplaceUses(Op.getValue(1), SDValue(Rem, 0));
- #ifndef NDEBUG
- DOUT << std::string(Indent-2, ' ') << "=> ";
- DEBUG(Result->dump(CurDAG));
- DOUT << "\n";
- #endif
+ if (!SDValue(Node, 1).use_empty()) {
+ unsigned SubRegIdx = (is32Bit ?
+ SystemZ::subreg_32bit : SystemZ::subreg_even);
+ SDNode *Rem = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
+ dl, NVT,
+ SDValue(Result, 0),
+ CurDAG->getTargetConstant(SubRegIdx,
+ MVT::i32));
+
+ ReplaceUses(SDValue(Node, 1), SDValue(Rem, 0));
+ DEBUG(errs() << "=> "; Result->dump(CurDAG); errs() << "\n");
}
-#ifndef NDEBUG
- Indent -= 2;
-#endif
-
return NULL;
}
case ISD::UDIVREM: {
unsigned Opc, MOpc, ClrOpc;
SDValue N0 = Node->getOperand(0);
SDValue N1 = Node->getOperand(1);
- MVT ResVT;
+ EVT ResVT;
bool is32Bit = false;
- switch (NVT.getSimpleVT()) {
- default: assert(0 && "Unsupported VT!");
- case MVT::i32:
- Opc = SystemZ::UDIVREM32r; MOpc = SystemZ::UDIVREM32m;
- ClrOpc = SystemZ::MOV64Pr0_even;
- ResVT = MVT::v2i32;
- is32Bit = true;
- break;
- case MVT::i64:
- Opc = SystemZ::UDIVREM64r; MOpc = SystemZ::UDIVREM64m;
- ClrOpc = SystemZ::MOV128r0_even;
- ResVT = MVT::v2i64;
- break;
+ switch (NVT.getSimpleVT().SimpleTy) {
+ default: assert(0 && "Unsupported VT!");
+ case MVT::i32:
+ Opc = SystemZ::UDIVREM32r; MOpc = SystemZ::UDIVREM32m;
+ ClrOpc = SystemZ::MOV64Pr0_even;
+ ResVT = MVT::v2i32;
+ is32Bit = true;
+ break;
+ case MVT::i64:
+ Opc = SystemZ::UDIVREM64r; MOpc = SystemZ::UDIVREM64m;
+ ClrOpc = SystemZ::MOV128r0_even;
+ ResVT = MVT::v2i64;
+ break;
}
SDValue Tmp0, Tmp1, Tmp2;
- bool foldedLoad = TryFoldLoad(Op, N1, Tmp0, Tmp1, Tmp2);
+ bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2);
// Prepare the dividend
SDNode *Dividend = N0.getNode();
// Insert prepared dividend into suitable 'subreg'
- SDNode *Tmp = CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF,
- dl, ResVT);
+ SDNode *Tmp = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
+ dl, ResVT);
{
- unsigned SubRegIdx = (is32Bit ? subreg_odd32 : subreg_odd);
+ unsigned SubRegIdx = (is32Bit ?
+ SystemZ::subreg_odd32 : SystemZ::subreg_odd);
Dividend =
- CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT,
- SDValue(Tmp, 0), SDValue(Dividend, 0),
- CurDAG->getTargetConstant(SubRegIdx, MVT::i32));
+ CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl, ResVT,
+ SDValue(Tmp, 0), SDValue(Dividend, 0),
+ CurDAG->getTargetConstant(SubRegIdx, MVT::i32));
}
// Zero out even subreg
- Dividend = CurDAG->getTargetNode(ClrOpc, dl, ResVT, SDValue(Dividend, 0));
+ Dividend = CurDAG->getMachineNode(ClrOpc, dl, ResVT, SDValue(Dividend, 0));
SDValue DivVal = SDValue(Dividend, 0);
SDNode *Result;
if (foldedLoad) {
SDValue Ops[] = { DivVal, Tmp0, Tmp1, Tmp2, N1.getOperand(0) };
- Result = CurDAG->getTargetNode(MOpc, dl,ResVT,
- Ops, array_lengthof(Ops));
+ Result = CurDAG->getMachineNode(MOpc, dl, ResVT, MVT::Other,
+ Ops, array_lengthof(Ops));
// Update the chain.
- ReplaceUses(N1.getValue(1), SDValue(Result, 0));
+ ReplaceUses(N1.getValue(1), SDValue(Result, 1));
} else {
- Result = CurDAG->getTargetNode(Opc, dl, ResVT, DivVal, N1);
+ Result = CurDAG->getMachineNode(Opc, dl, ResVT, DivVal, N1);
}
// Copy the division (odd subreg) result, if it is needed.
- if (!Op.getValue(0).use_empty()) {
- unsigned SubRegIdx = (is32Bit ? subreg_odd32 : subreg_odd);
- SDNode *Div = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
- dl, NVT,
- SDValue(Result, 0),
- CurDAG->getTargetConstant(SubRegIdx,
- MVT::i32));
- ReplaceUses(Op.getValue(0), SDValue(Div, 0));
- #ifndef NDEBUG
- DOUT << std::string(Indent-2, ' ') << "=> ";
- DEBUG(Result->dump(CurDAG));
- DOUT << "\n";
- #endif
+ if (!SDValue(Node, 0).use_empty()) {
+ unsigned SubRegIdx = (is32Bit ?
+ SystemZ::subreg_odd32 : SystemZ::subreg_odd);
+ SDNode *Div = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
+ dl, NVT,
+ SDValue(Result, 0),
+ CurDAG->getTargetConstant(SubRegIdx,
+ MVT::i32));
+ ReplaceUses(SDValue(Node, 0), SDValue(Div, 0));
+ DEBUG(errs() << "=> "; Result->dump(CurDAG); errs() << "\n");
}
// Copy the remainder (even subreg) result, if it is needed.
- if (!Op.getValue(1).use_empty()) {
- unsigned SubRegIdx = (is32Bit ? subreg_even32 : subreg_even);
- SDNode *Rem = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
- dl, NVT,
- SDValue(Result, 0),
- CurDAG->getTargetConstant(SubRegIdx,
- MVT::i32));
- ReplaceUses(Op.getValue(1), SDValue(Rem, 0));
- #ifndef NDEBUG
- DOUT << std::string(Indent-2, ' ') << "=> ";
- DEBUG(Result->dump(CurDAG));
- DOUT << "\n";
- #endif
+ if (!SDValue(Node, 1).use_empty()) {
+ unsigned SubRegIdx = (is32Bit ?
+ SystemZ::subreg_32bit : SystemZ::subreg_even);
+ SDNode *Rem = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
+ dl, NVT,
+ SDValue(Result, 0),
+ CurDAG->getTargetConstant(SubRegIdx,
+ MVT::i32));
+ ReplaceUses(SDValue(Node, 1), SDValue(Rem, 0));
+ DEBUG(errs() << "=> "; Result->dump(CurDAG); errs() << "\n");
}
-#ifndef NDEBUG
- Indent -= 2;
-#endif
-
return NULL;
}
}
// Select the default instruction
- SDNode *ResNode = SelectCode(Op);
-
- #ifndef NDEBUG
- DOUT << std::string(Indent-2, ' ') << "=> ";
- if (ResNode == NULL || ResNode == Op.getNode())
- DEBUG(Op.getNode()->dump(CurDAG));
- else
- DEBUG(ResNode->dump(CurDAG));
- DOUT << "\n";
- Indent -= 2;
- #endif
-
+ SDNode *ResNode = SelectCode(Node);
+
+ DEBUG(errs() << "=> ";
+ if (ResNode == NULL || ResNode == Node)
+ Node->dump(CurDAG);
+ else
+ ResNode->dump(CurDAG);
+ errs() << "\n";
+ );
return ResNode;
}
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