#include "llvm/Target/TargetLowering.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
using namespace llvm;
+static const unsigned subreg_even32 = 1;
+static const unsigned subreg_odd32 = 2;
+static const unsigned subreg_even = 3;
+static const unsigned subreg_odd = 4;
+
namespace {
/// SystemZRRIAddressMode - This corresponds to rriaddr, but uses SDValue's
/// instead of register numbers for the leaves of the matched tree.
return "SystemZ DAG->DAG Pattern Instruction Selection";
}
+ /// getI8Imm - Return a target constant with the specified value, of type
+ /// i8.
+ inline SDValue getI8Imm(uint64_t Imm) {
+ return CurDAG->getTargetConstant(Imm, MVT::i8);
+ }
+
/// getI16Imm - Return a target constant with the specified value, of type
/// i16.
inline SDValue getI16Imm(uint64_t Imm) {
#include "SystemZGenDAGISel.inc"
private:
+ bool SelectAddrRI12Only(SDValue Op, SDValue& Addr,
+ SDValue &Base, SDValue &Disp);
bool SelectAddrRI12(SDValue Op, SDValue& Addr,
- SDValue &Base, SDValue &Disp);
+ SDValue &Base, SDValue &Disp,
+ bool is12BitOnly = false);
bool SelectAddrRI(SDValue Op, SDValue& Addr,
SDValue &Base, SDValue &Disp);
bool SelectAddrRRI12(SDValue Op, SDValue Addr,
SDValue &Base, SDValue &Disp, SDValue &Index);
SDNode *Select(SDValue Op);
+
+ bool TryFoldLoad(SDValue P, SDValue N,
+ SDValue &Base, SDValue &Disp, SDValue &Index);
+
bool MatchAddress(SDValue N, SystemZRRIAddressMode &AM,
bool is12Bit, unsigned Depth = 0);
bool MatchAddressBase(SDValue N, SystemZRRIAddressMode &AM);
default: break;
case ISD::Constant: {
int64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
- int64_t Imm;
+ int64_t Imm = 0;
bool Match = (is12Bit ?
isImmZExt12(AM.Disp + Val, Imm) :
isImmSExt20(AM.Disp + Val, Imm));
break;
}
// Test if the index field is free for use.
- if (AM.IndexReg.getNode() && !AM.isRI) {
+ if (AM.IndexReg.getNode() || AM.isRI) {
AM = Backup;
break;
}
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
SystemZRRIAddressMode Backup = AM;
int64_t Offset = CN->getSExtValue();
- int64_t Imm;
+ int64_t Imm = 0;
bool MatchOffset = (is12Bit ?
isImmZExt12(AM.Disp + Offset, Imm) :
isImmSExt20(AM.Disp + Offset, Imm));
SystemZRRIAddressMode &AM) {
// Is the base register already occupied?
if (AM.BaseType != SystemZRRIAddressMode::RegBase || AM.Base.Reg.getNode()) {
- // If so, check to see if the scale register is set.
+ // If so, check to see if the index register is set.
if (AM.IndexReg.getNode() == 0 && !AM.isRI) {
AM.IndexReg = N;
return false;
/// Returns true if the address can be represented by a base register plus
/// an unsigned 12-bit displacement [r+imm].
+bool SystemZDAGToDAGISel::SelectAddrRI12Only(SDValue Op, SDValue& Addr,
+ SDValue &Base, SDValue &Disp) {
+ return SelectAddrRI12(Op, Addr, Base, Disp, /*is12BitOnly*/true);
+}
+
bool SystemZDAGToDAGISel::SelectAddrRI12(SDValue Op, SDValue& Addr,
- SDValue &Base, SDValue &Disp) {
+ SDValue &Base, SDValue &Disp,
+ bool is12BitOnly) {
SystemZRRIAddressMode AM20(/*isRI*/true), AM12(/*isRI*/true);
bool Done = false;
return false;
// Check, whether we can match stuff using 20-bit displacements
- if (!Done && !MatchAddress(Addr, AM20, /* is12Bit */ false))
+ if (!Done && !is12BitOnly &&
+ !MatchAddress(Addr, AM20, /* is12Bit */ false))
if (AM12.Disp == 0 && AM20.Disp != 0)
return false;
/// index register plus an unsigned 12-bit displacement [base + idx + imm].
bool SystemZDAGToDAGISel::SelectAddrRRI12(SDValue Op, SDValue Addr,
SDValue &Base, SDValue &Disp, SDValue &Index) {
- SystemZRRIAddressMode AM20(/*isRI*/true), AM12(/*isRI*/true);
+ SystemZRRIAddressMode AM20, AM12;
bool Done = false;
if (!Addr.hasOneUse()) {
return false;
}
+bool SystemZDAGToDAGISel::TryFoldLoad(SDValue P, SDValue N,
+ SDValue &Base, SDValue &Disp, SDValue &Index) {
+ if (ISD::isNON_EXTLoad(N.getNode()) &&
+ N.hasOneUse() &&
+ IsLegalAndProfitableToFold(N.getNode(), P.getNode(), P.getNode()))
+ return SelectAddrRRI20(P, N.getOperand(1), Base, Disp, Index);
+ return false;
+}
+
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
void SystemZDAGToDAGISel::InstructionSelect() {
SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
SDNode *Node = Op.getNode();
+ MVT NVT = Node->getValueType(0);
DebugLoc dl = Op.getDebugLoc();
+ unsigned Opcode = Node->getOpcode();
// Dump information about the Node being selected
#ifndef NDEBUG
DOUT << "\n";
Indent -= 2;
#endif
+ return NULL; // Already selected.
+ }
+
+ switch (Opcode) {
+ default: break;
+ case ISD::SDIVREM: {
+ unsigned Opc, MOpc;
+ SDValue N0 = Node->getOperand(0);
+ SDValue N1 = Node->getOperand(1);
+
+ MVT ResVT;
+ bool is32Bit = false;
+ switch (NVT.getSimpleVT()) {
+ default: assert(0 && "Unsupported VT!");
+ case MVT::i32:
+ Opc = SystemZ::SDIVREM32r; MOpc = SystemZ::SDIVREM32m;
+ ResVT = MVT::v2i64;
+ is32Bit = true;
+ break;
+ case MVT::i64:
+ Opc = SystemZ::SDIVREM64r; MOpc = SystemZ::SDIVREM64m;
+ ResVT = MVT::v2i64;
+ break;
+ }
+
+ SDValue Tmp0, Tmp1, Tmp2;
+ bool foldedLoad = TryFoldLoad(Op, N1, Tmp0, Tmp1, Tmp2);
+
+ // Prepare the dividend
+ SDNode *Dividend;
+ if (is32Bit)
+ Dividend = CurDAG->getTargetNode(SystemZ::MOVSX64rr32, dl, MVT::i64, N0);
+ else
+ Dividend = N0.getNode();
+
+ // Insert prepared dividend into suitable 'subreg'
+ SDNode *Tmp = CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF,
+ dl, ResVT);
+ Dividend =
+ CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT,
+ SDValue(Tmp, 0), SDValue(Dividend, 0),
+ CurDAG->getTargetConstant(subreg_odd, MVT::i32));
+
+ SDNode *Result;
+ SDValue DivVal = SDValue(Dividend, 0);
+ if (foldedLoad) {
+ SDValue Ops[] = { DivVal, Tmp0, Tmp1, Tmp2, N1.getOperand(0) };
+ Result = CurDAG->getTargetNode(MOpc, dl, ResVT, Ops, array_lengthof(Ops));
+ // Update the chain.
+ ReplaceUses(N1.getValue(1), SDValue(Result, 0));
+ } else {
+ Result = CurDAG->getTargetNode(Opc, dl, ResVT, SDValue(Dividend, 0), N1);
+ }
+
+ // Copy the division (odd subreg) result, if it is needed.
+ if (!Op.getValue(0).use_empty()) {
+ unsigned SubRegIdx = (is32Bit ? subreg_odd32 : subreg_odd);
+ SDNode *Div = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
+ dl, NVT,
+ SDValue(Result, 0),
+ CurDAG->getTargetConstant(SubRegIdx,
+ MVT::i32));
+
+ ReplaceUses(Op.getValue(0), SDValue(Div, 0));
+ #ifndef NDEBUG
+ DOUT << std::string(Indent-2, ' ') << "=> ";
+ DEBUG(Result->dump(CurDAG));
+ DOUT << "\n";
+ #endif
+ }
+
+ // Copy the remainder (even subreg) result, if it is needed.
+ if (!Op.getValue(1).use_empty()) {
+ unsigned SubRegIdx = (is32Bit ? subreg_even32 : subreg_even);
+ SDNode *Rem = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
+ dl, NVT,
+ SDValue(Result, 0),
+ CurDAG->getTargetConstant(SubRegIdx,
+ MVT::i32));
+
+ ReplaceUses(Op.getValue(1), SDValue(Rem, 0));
+ #ifndef NDEBUG
+ DOUT << std::string(Indent-2, ' ') << "=> ";
+ DEBUG(Result->dump(CurDAG));
+ DOUT << "\n";
+ #endif
+ }
+
+#ifndef NDEBUG
+ Indent -= 2;
+#endif
+
return NULL;
}
+ case ISD::UDIVREM: {
+ unsigned Opc, MOpc, ClrOpc;
+ SDValue N0 = Node->getOperand(0);
+ SDValue N1 = Node->getOperand(1);
+ MVT ResVT;
+
+ bool is32Bit = false;
+ switch (NVT.getSimpleVT()) {
+ default: assert(0 && "Unsupported VT!");
+ case MVT::i32:
+ Opc = SystemZ::UDIVREM32r; MOpc = SystemZ::UDIVREM32m;
+ ClrOpc = SystemZ::MOV64Pr0_even;
+ ResVT = MVT::v2i32;
+ is32Bit = true;
+ break;
+ case MVT::i64:
+ Opc = SystemZ::UDIVREM64r; MOpc = SystemZ::UDIVREM64m;
+ ClrOpc = SystemZ::MOV128r0_even;
+ ResVT = MVT::v2i64;
+ break;
+ }
+
+ SDValue Tmp0, Tmp1, Tmp2;
+ bool foldedLoad = TryFoldLoad(Op, N1, Tmp0, Tmp1, Tmp2);
+
+ // Prepare the dividend
+ SDNode *Dividend = N0.getNode();
+
+ // Insert prepared dividend into suitable 'subreg'
+ SDNode *Tmp = CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF,
+ dl, ResVT);
+ {
+ unsigned SubRegIdx = (is32Bit ? subreg_odd32 : subreg_odd);
+ Dividend =
+ CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT,
+ SDValue(Tmp, 0), SDValue(Dividend, 0),
+ CurDAG->getTargetConstant(SubRegIdx, MVT::i32));
+ }
+
+ // Zero out even subreg
+ Dividend = CurDAG->getTargetNode(ClrOpc, dl, ResVT, SDValue(Dividend, 0));
+
+ SDValue DivVal = SDValue(Dividend, 0);
+ SDNode *Result;
+ if (foldedLoad) {
+ SDValue Ops[] = { DivVal, Tmp0, Tmp1, Tmp2, N1.getOperand(0) };
+ Result = CurDAG->getTargetNode(MOpc, dl,ResVT,
+ Ops, array_lengthof(Ops));
+ // Update the chain.
+ ReplaceUses(N1.getValue(1), SDValue(Result, 0));
+ } else {
+ Result = CurDAG->getTargetNode(Opc, dl, ResVT, DivVal, N1);
+ }
+
+ // Copy the division (odd subreg) result, if it is needed.
+ if (!Op.getValue(0).use_empty()) {
+ unsigned SubRegIdx = (is32Bit ? subreg_odd32 : subreg_odd);
+ SDNode *Div = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
+ dl, NVT,
+ SDValue(Result, 0),
+ CurDAG->getTargetConstant(SubRegIdx,
+ MVT::i32));
+ ReplaceUses(Op.getValue(0), SDValue(Div, 0));
+ #ifndef NDEBUG
+ DOUT << std::string(Indent-2, ' ') << "=> ";
+ DEBUG(Result->dump(CurDAG));
+ DOUT << "\n";
+ #endif
+ }
+
+ // Copy the remainder (even subreg) result, if it is needed.
+ if (!Op.getValue(1).use_empty()) {
+ unsigned SubRegIdx = (is32Bit ? subreg_even32 : subreg_even);
+ SDNode *Rem = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
+ dl, NVT,
+ SDValue(Result, 0),
+ CurDAG->getTargetConstant(SubRegIdx,
+ MVT::i32));
+ ReplaceUses(Op.getValue(1), SDValue(Rem, 0));
+ #ifndef NDEBUG
+ DOUT << std::string(Indent-2, ' ') << "=> ";
+ DEBUG(Result->dump(CurDAG));
+ DOUT << "\n";
+ #endif
+ }
+
+#ifndef NDEBUG
+ Indent -= 2;
+#endif
+
+ return NULL;
+ }
+ }
// Select the default instruction
SDNode *ResNode = SelectCode(Op);
projects / oota-llvm.git / blobdiff