// Unconditional branches. R1 is the condition-code mask (all 1s).
let isBranch = 1, isTerminator = 1, isBarrier = 1, R1 = 15 in {
let isIndirectBranch = 1 in
- def BR : InstRR<0x07, (outs), (ins ADDR64:$dst),
- "br\t$dst", [(brind ADDR64:$dst)]>;
+ def BR : InstRR<0x07, (outs), (ins ADDR64:$R2),
+ "br\t$R2", [(brind ADDR64:$R2)]>;
- // An assembler extended mnemonic for BRC. Use a separate instruction for
- // the asm parser, so that we don't relax Js to external symbols into JGs.
- let isCodeGenOnly = 1 in
- def J : InstRI<0xA74, (outs), (ins brtarget16:$dst), "j\t$dst", []>;
- let isAsmParserOnly = 1 in
- def AsmJ : InstRI<0xA74, (outs), (ins brtarget16:$dst), "j\t$dst", []>;
+ // An assembler extended mnemonic for BRC.
+ def J : InstRI<0xA74, (outs), (ins brtarget16:$I2), "j\t$I2",
+ [(br bb:$I2)]>;
// An assembler extended mnemonic for BRCL. (The extension is "G"
// rather than "L" because "JL" is "Jump if Less".)
- def JG : InstRIL<0xC04, (outs), (ins brtarget32:$dst),
- "jg\t$dst", [(br bb:$dst)]>;
+ def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2), "jg\t$I2", []>;
}
// Conditional branches. It's easier for LLVM to handle these branches
// in their raw BRC/BRCL form, with the 4-bit condition-code mask being
// the first operand. It seems friendlier to use mnemonic forms like
// JE and JLH when writing out the assembly though.
-multiclass CondBranches<Operand imm, string short, string long> {
- let isBranch = 1, isTerminator = 1, Uses = [PSW] in {
- def "" : InstRI<0xA74, (outs), (ins imm:$cond, brtarget16:$dst), short, []>;
- def L : InstRIL<0xC04, (outs), (ins imm:$cond, brtarget32:$dst), long, []>;
+let isBranch = 1, isTerminator = 1, Uses = [CC] in {
+ let isCodeGenOnly = 1, CCMaskFirst = 1 in {
+ def BRC : InstRI<0xA74, (outs), (ins cond4:$valid, cond4:$R1,
+ brtarget16:$I2), "j$R1\t$I2",
+ [(z_br_ccmask cond4:$valid, cond4:$R1, bb:$I2)]>;
+ def BRCL : InstRIL<0xC04, (outs), (ins cond4:$valid, cond4:$R1,
+ brtarget32:$I2), "jg$R1\t$I2", []>;
+ }
+ def AsmBRC : InstRI<0xA74, (outs), (ins uimm8zx4:$R1, brtarget16:$I2),
+ "brc\t$R1, $I2", []>;
+ def AsmBRCL : InstRIL<0xC04, (outs), (ins uimm8zx4:$R1, brtarget32:$I2),
+ "brcl\t$R1, $I2", []>;
+}
+
+// Fused compare-and-branch instructions. As for normal branches,
+// we handle these instructions internally in their raw CRJ-like form,
+// but use assembly macros like CRJE when writing them out.
+//
+// These instructions do not use or clobber the condition codes.
+// We nevertheless pretend that they clobber CC, so that we can lower
+// them to separate comparisons and BRCLs if the branch ends up being
+// out of range.
+multiclass CompareBranches<Operand ccmask, string pos1, string pos2> {
+ let isBranch = 1, isTerminator = 1, Defs = [CC] in {
+ def RJ : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
+ brtarget16:$RI4),
+ "crj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
+ def GRJ : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
+ brtarget16:$RI4),
+ "cgrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
+ def IJ : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2, ccmask:$M3,
+ brtarget16:$RI4),
+ "cij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
+ def GIJ : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2, ccmask:$M3,
+ brtarget16:$RI4),
+ "cgij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
}
}
let isCodeGenOnly = 1 in
- defm BRC : CondBranches<cond4, "j$cond\t$dst", "jg$cond\t$dst">;
-let isAsmParserOnly = 1 in
- defm AsmBRC : CondBranches<uimm8zx4, "brc\t$cond, $dst", "brcl\t$cond, $dst">;
-
-def : Pat<(z_br_ccmask cond4:$cond, bb:$dst), (BRCL cond4:$cond, bb:$dst)>;
-
-// Define AsmParser mnemonics for each condition code.
-multiclass CondExtendedMnemonic<bits<4> Cond, string name> {
- let R1 = Cond in {
- def "" : InstRI<0xA74, (outs), (ins brtarget16:$dst),
- "j"##name##"\t$dst", []>;
- def L : InstRIL<0xC04, (outs), (ins brtarget32:$dst),
- "jg"##name##"\t$dst", []>;
+ defm C : CompareBranches<cond4, "$M3", "">;
+defm AsmC : CompareBranches<uimm8zx4, "", "$M3, ">;
+
+// Define AsmParser mnemonics for each general condition-code mask
+// (integer or floating-point)
+multiclass CondExtendedMnemonic<bits<4> ccmask, string name> {
+ let R1 = ccmask in {
+ def J : InstRI<0xA74, (outs), (ins brtarget16:$I2),
+ "j"##name##"\t$I2", []>;
+ def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2),
+ "jg"##name##"\t$I2", []>;
}
+ def LOCR : FixedCondUnaryRRF<"locr"##name, 0xB9F2, GR32, GR32, ccmask>;
+ def LOCGR : FixedCondUnaryRRF<"locgr"##name, 0xB9E2, GR64, GR64, ccmask>;
+ def LOC : FixedCondUnaryRSY<"loc"##name, 0xEBF2, GR32, ccmask, 4>;
+ def LOCG : FixedCondUnaryRSY<"locg"##name, 0xEBE2, GR64, ccmask, 8>;
+ def STOC : FixedCondStoreRSY<"stoc"##name, 0xEBF3, GR32, ccmask, 4>;
+ def STOCG : FixedCondStoreRSY<"stocg"##name, 0xEBE3, GR64, ccmask, 8>;
}
-let isAsmParserOnly = 1 in {
- defm AsmJO : CondExtendedMnemonic<1, "o">;
- defm AsmJH : CondExtendedMnemonic<2, "h">;
- defm AsmJNLE : CondExtendedMnemonic<3, "nle">;
- defm AsmJL : CondExtendedMnemonic<4, "l">;
- defm AsmJNHE : CondExtendedMnemonic<5, "nhe">;
- defm AsmJLH : CondExtendedMnemonic<6, "lh">;
- defm AsmJNE : CondExtendedMnemonic<7, "ne">;
- defm AsmJE : CondExtendedMnemonic<8, "e">;
- defm AsmJNLH : CondExtendedMnemonic<9, "nlh">;
- defm AsmJHE : CondExtendedMnemonic<10, "he">;
- defm AsmJNL : CondExtendedMnemonic<11, "nl">;
- defm AsmJLE : CondExtendedMnemonic<12, "le">;
- defm AsmJNH : CondExtendedMnemonic<13, "nh">;
- defm AsmJNO : CondExtendedMnemonic<14, "no">;
+defm AsmO : CondExtendedMnemonic<1, "o">;
+defm AsmH : CondExtendedMnemonic<2, "h">;
+defm AsmNLE : CondExtendedMnemonic<3, "nle">;
+defm AsmL : CondExtendedMnemonic<4, "l">;
+defm AsmNHE : CondExtendedMnemonic<5, "nhe">;
+defm AsmLH : CondExtendedMnemonic<6, "lh">;
+defm AsmNE : CondExtendedMnemonic<7, "ne">;
+defm AsmE : CondExtendedMnemonic<8, "e">;
+defm AsmNLH : CondExtendedMnemonic<9, "nlh">;
+defm AsmHE : CondExtendedMnemonic<10, "he">;
+defm AsmNL : CondExtendedMnemonic<11, "nl">;
+defm AsmLE : CondExtendedMnemonic<12, "le">;
+defm AsmNH : CondExtendedMnemonic<13, "nh">;
+defm AsmNO : CondExtendedMnemonic<14, "no">;
+
+// Define AsmParser mnemonics for each integer condition-code mask.
+// This is like the list above, except that condition 3 is not possible
+// and that the low bit of the mask is therefore always 0. This means
+// that each condition has two names. Conditions "o" and "no" are not used.
+//
+// We don't make one of the two names an alias of the other because
+// we need the custom parsing routines to select the correct register class.
+multiclass IntCondExtendedMnemonicA<bits<4> ccmask, string name> {
+ let M3 = ccmask in {
+ def CR : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2,
+ brtarget16:$RI4),
+ "crj"##name##"\t$R1, $R2, $RI4", []>;
+ def CGR : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2,
+ brtarget16:$RI4),
+ "cgrj"##name##"\t$R1, $R2, $RI4", []>;
+ def CI : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2,
+ brtarget16:$RI4),
+ "cij"##name##"\t$R1, $I2, $RI4", []>;
+ def CGI : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2,
+ brtarget16:$RI4),
+ "cgij"##name##"\t$R1, $I2, $RI4", []>;
+ }
}
+multiclass IntCondExtendedMnemonic<bits<4> ccmask, string name1, string name2>
+ : IntCondExtendedMnemonicA<ccmask, name1> {
+ let isAsmParserOnly = 1 in
+ defm Alt : IntCondExtendedMnemonicA<ccmask, name2>;
+}
+defm AsmJH : IntCondExtendedMnemonic<2, "h", "nle">;
+defm AsmJL : IntCondExtendedMnemonic<4, "l", "nhe">;
+defm AsmJLH : IntCondExtendedMnemonic<6, "lh", "ne">;
+defm AsmJE : IntCondExtendedMnemonic<8, "e", "nlh">;
+defm AsmJHE : IntCondExtendedMnemonic<10, "he", "nl">;
+defm AsmJLE : IntCondExtendedMnemonic<12, "le", "nh">;
+
+// Decrement a register and branch if it is nonzero. These don't clobber CC,
+// but we might need to split long branches into sequences that do.
+let Defs = [CC] in {
+ def BRCT : BranchUnaryRI<"brct", 0xA76, GR32>;
+ def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>;
+}
+
+//===----------------------------------------------------------------------===//
+// Select instructions
+//===----------------------------------------------------------------------===//
def Select32 : SelectWrapper<GR32>;
def Select64 : SelectWrapper<GR64>;
+defm CondStore8_32 : CondStores<GR32, nonvolatile_truncstorei8,
+ nonvolatile_anyextloadi8, bdxaddr20only>;
+defm CondStore16_32 : CondStores<GR32, nonvolatile_truncstorei16,
+ nonvolatile_anyextloadi16, bdxaddr20only>;
+defm CondStore32_32 : CondStores<GR32, nonvolatile_store,
+ nonvolatile_load, bdxaddr20only>;
+
+defm CondStore8 : CondStores<GR64, nonvolatile_truncstorei8,
+ nonvolatile_anyextloadi8, bdxaddr20only>;
+defm CondStore16 : CondStores<GR64, nonvolatile_truncstorei16,
+ nonvolatile_anyextloadi16, bdxaddr20only>;
+defm CondStore32 : CondStores<GR64, nonvolatile_truncstorei32,
+ nonvolatile_anyextloadi32, bdxaddr20only>;
+defm CondStore64 : CondStores<GR64, nonvolatile_store,
+ nonvolatile_load, bdxaddr20only>;
+
//===----------------------------------------------------------------------===//
// Call instructions
//===----------------------------------------------------------------------===//
// The definitions here are for the call-clobbered registers.
let isCall = 1, Defs = [R0D, R1D, R2D, R3D, R4D, R5D, R14D,
- F0D, F1D, F2D, F3D, F4D, F5D, F6D, F7D],
+ F0D, F1D, F2D, F3D, F4D, F5D, F6D, F7D, CC],
R1 = 14, isCodeGenOnly = 1 in {
- def BRAS : InstRI<0xA75, (outs), (ins pcrel16call:$dst, variable_ops),
- "bras\t%r14, $dst", []>;
- def BRASL : InstRIL<0xC05, (outs), (ins pcrel32call:$dst, variable_ops),
- "brasl\t%r14, $dst", [(z_call pcrel32call:$dst)]>;
- def BASR : InstRR<0x0D, (outs), (ins ADDR64:$dst, variable_ops),
- "basr\t%r14, $dst", [(z_call ADDR64:$dst)]>;
+ def BRAS : InstRI<0xA75, (outs), (ins pcrel16call:$I2, variable_ops),
+ "bras\t%r14, $I2", []>;
+ def BRASL : InstRIL<0xC05, (outs), (ins pcrel32call:$I2, variable_ops),
+ "brasl\t%r14, $I2", [(z_call pcrel32call:$I2)]>;
+ def BASR : InstRR<0x0D, (outs), (ins ADDR64:$R2, variable_ops),
+ "basr\t%r14, $R2", [(z_call ADDR64:$R2)]>;
}
// Define the general form of the call instructions for the asm parser.
// These instructions don't hard-code %r14 as the return address register.
-let isAsmParserOnly = 1 in {
- def AsmBRAS : InstRI<0xA75, (outs), (ins GR64:$save, brtarget16:$dst),
- "bras\t$save, $dst", []>;
- def AsmBRASL : InstRIL<0xC05, (outs), (ins GR64:$save, brtarget32:$dst),
- "brasl\t$save, $dst", []>;
- def AsmBASR : InstRR<0x0D, (outs), (ins GR64:$save, ADDR64:$dst),
- "basr\t$save, $dst", []>;
-}
+def AsmBRAS : InstRI<0xA75, (outs), (ins GR64:$R1, brtarget16:$I2),
+ "bras\t$R1, $I2", []>;
+def AsmBRASL : InstRIL<0xC05, (outs), (ins GR64:$R1, brtarget32:$I2),
+ "brasl\t$R1, $I2", []>;
+def AsmBASR : InstRR<0x0D, (outs), (ins GR64:$R1, ADDR64:$R2),
+ "basr\t$R1, $R2", []>;
//===----------------------------------------------------------------------===//
// Move instructions
// Register moves.
let neverHasSideEffects = 1 in {
- def LR : UnaryRR <"lr", 0x18, null_frag, GR32, GR32>;
- def LGR : UnaryRRE<"lgr", 0xB904, null_frag, GR64, GR64>;
+ def LR : UnaryRR <"l", 0x18, null_frag, GR32, GR32>;
+ def LGR : UnaryRRE<"lg", 0xB904, null_frag, GR64, GR64>;
+}
+let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
+ def LTR : UnaryRR <"lt", 0x12, null_frag, GR32, GR32>;
+ def LTGR : UnaryRRE<"ltg", 0xB902, null_frag, GR64, GR64>;
+}
+
+// Move on condition.
+let isCodeGenOnly = 1, Uses = [CC] in {
+ def LOCR : CondUnaryRRF<"loc", 0xB9F2, GR32, GR32>;
+ def LOCGR : CondUnaryRRF<"locg", 0xB9E2, GR64, GR64>;
+}
+let Uses = [CC] in {
+ def AsmLOCR : AsmCondUnaryRRF<"loc", 0xB9F2, GR32, GR32>;
+ def AsmLOCGR : AsmCondUnaryRRF<"locg", 0xB9E2, GR64, GR64>;
}
// Immediate moves.
-let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
+let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
+ isReMaterializable = 1 in {
// 16-bit sign-extended immediates.
def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>;
def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>;
// Register loads.
let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
- defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32>;
- def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>;
-
- def LG : UnaryRXY<"lg", 0xE304, load, GR64>;
- def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>;
+ defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>;
+ def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>;
// These instructions are split after register allocation, so we don't
// want a custom inserter.
[(set GR128:$dst, (load bdxaddr20only128:$src))]>;
}
}
+let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
+ def LT : UnaryRXY<"lt", 0xE312, load, GR32, 4>;
+ def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>;
+}
+
+let canFoldAsLoad = 1 in {
+ def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>;
+ def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>;
+}
+
+// Load on condition.
+let isCodeGenOnly = 1, Uses = [CC] in {
+ def LOC : CondUnaryRSY<"loc", 0xEBF2, nonvolatile_load, GR32, 4>;
+ def LOCG : CondUnaryRSY<"locg", 0xEBE2, nonvolatile_load, GR64, 8>;
+}
+let Uses = [CC] in {
+ def AsmLOC : AsmCondUnaryRSY<"loc", 0xEBF2, GR32, 4>;
+ def AsmLOCG : AsmCondUnaryRSY<"locg", 0xEBE2, GR64, 8>;
+}
// Register stores.
let SimpleBDXStore = 1 in {
- let isCodeGenOnly = 1 in {
- defm ST32 : StoreRXPair<"st", 0x50, 0xE350, store, GR32>;
- def STRL32 : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>;
- }
-
- def STG : StoreRXY<"stg", 0xE324, store, GR64>;
- def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>;
+ let isCodeGenOnly = 1 in
+ defm ST32 : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>;
+ def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>;
// These instructions are split after register allocation, so we don't
// want a custom inserter.
[(store GR128:$src, bdxaddr20only128:$dst)]>;
}
}
+let isCodeGenOnly = 1 in
+ def STRL32 : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>;
+def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>;
+
+// Store on condition.
+let isCodeGenOnly = 1, Uses = [CC] in {
+ def STOC32 : CondStoreRSY<"stoc", 0xEBF3, GR32, 4>;
+ def STOC : CondStoreRSY<"stoc", 0xEBF3, GR64, 4>;
+ def STOCG : CondStoreRSY<"stocg", 0xEBE3, GR64, 8>;
+}
+let Uses = [CC] in {
+ def AsmSTOC : AsmCondStoreRSY<"stoc", 0xEBF3, GR32, 4>;
+ def AsmSTOCG : AsmCondStoreRSY<"stocg", 0xEBE3, GR64, 8>;
+}
// 8-bit immediate stores to 8-bit fields.
defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>;
def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>;
def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>;
+// Memory-to-memory moves.
+let mayLoad = 1, mayStore = 1 in
+ defm MVC : MemorySS<"mvc", 0xD2, z_mvc>;
+
+// String moves.
+let mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0W] in
+ defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>;
+
+defm LoadStore8_32 : MVCLoadStore<anyextloadi8, truncstorei8, i32,
+ MVCWrapper, 1>;
+defm LoadStore16_32 : MVCLoadStore<anyextloadi16, truncstorei16, i32,
+ MVCWrapper, 2>;
+defm LoadStore32_32 : MVCLoadStore<load, store, i32, MVCWrapper, 4>;
+
+defm LoadStore8 : MVCLoadStore<anyextloadi8, truncstorei8, i64,
+ MVCWrapper, 1>;
+defm LoadStore16 : MVCLoadStore<anyextloadi16, truncstorei16, i64,
+ MVCWrapper, 2>;
+defm LoadStore32 : MVCLoadStore<anyextloadi32, truncstorei32, i64,
+ MVCWrapper, 4>;
+defm LoadStore64 : MVCLoadStore<load, store, i64, MVCWrapper, 8>;
+
//===----------------------------------------------------------------------===//
// Sign extensions
//===----------------------------------------------------------------------===//
// 32-bit extensions from registers.
let neverHasSideEffects = 1 in {
- def LBR : UnaryRRE<"lbr", 0xB926, sext8, GR32, GR32>;
- def LHR : UnaryRRE<"lhr", 0xB927, sext16, GR32, GR32>;
+ def LBR : UnaryRRE<"lb", 0xB926, sext8, GR32, GR32>;
+ def LHR : UnaryRRE<"lh", 0xB927, sext16, GR32, GR32>;
}
// 64-bit extensions from registers.
let neverHasSideEffects = 1 in {
- def LGBR : UnaryRRE<"lgbr", 0xB906, sext8, GR64, GR64>;
- def LGHR : UnaryRRE<"lghr", 0xB907, sext16, GR64, GR64>;
- def LGFR : UnaryRRE<"lgfr", 0xB914, sext32, GR64, GR32>;
+ def LGBR : UnaryRRE<"lgb", 0xB906, sext8, GR64, GR64>;
+ def LGHR : UnaryRRE<"lgh", 0xB907, sext16, GR64, GR64>;
+ def LGFR : UnaryRRE<"lgf", 0xB914, sext32, GR64, GR32>;
}
+let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in
+ def LTGFR : UnaryRRE<"ltgf", 0xB912, null_frag, GR64, GR64>;
// Match 32-to-64-bit sign extensions in which the source is already
// in a 64-bit register.
(LGFR (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
// 32-bit extensions from memory.
-def LB : UnaryRXY<"lb", 0xE376, sextloadi8, GR32>;
-defm LH : UnaryRXPair<"lh", 0x48, 0xE378, sextloadi16, GR32>;
+def LB : UnaryRXY<"lb", 0xE376, sextloadi8, GR32, 1>;
+defm LH : UnaryRXPair<"lh", 0x48, 0xE378, sextloadi16, GR32, 2>;
def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_sextloadi16, GR32>;
// 64-bit extensions from memory.
-def LGB : UnaryRXY<"lgb", 0xE377, sextloadi8, GR64>;
-def LGH : UnaryRXY<"lgh", 0xE315, sextloadi16, GR64>;
-def LGF : UnaryRXY<"lgf", 0xE314, sextloadi32, GR64>;
+def LGB : UnaryRXY<"lgb", 0xE377, sextloadi8, GR64, 1>;
+def LGH : UnaryRXY<"lgh", 0xE315, sextloadi16, GR64, 2>;
+def LGF : UnaryRXY<"lgf", 0xE314, sextloadi32, GR64, 4>;
def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_sextloadi16, GR64>;
def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_sextloadi32, GR64>;
+let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in
+ def LTGF : UnaryRXY<"ltgf", 0xE332, sextloadi32, GR64, 4>;
// If the sign of a load-extend operation doesn't matter, use the signed ones.
// There's not really much to choose between the sign and zero extensions,
def : Pat<(i64 (extloadi16 bdxaddr20only:$src)), (LGH bdxaddr20only:$src)>;
def : Pat<(i64 (extloadi32 bdxaddr20only:$src)), (LGF bdxaddr20only:$src)>;
+// We want PC-relative addresses to be tried ahead of BD and BDX addresses.
+// However, BDXs have two extra operands and are therefore 6 units more
+// complex.
+let AddedComplexity = 7 in {
+ def : Pat<(i32 (extloadi16 pcrel32:$src)), (LHRL pcrel32:$src)>;
+ def : Pat<(i64 (extloadi16 pcrel32:$src)), (LGHRL pcrel32:$src)>;
+}
+
//===----------------------------------------------------------------------===//
// Zero extensions
//===----------------------------------------------------------------------===//
// 32-bit extensions from registers.
let neverHasSideEffects = 1 in {
- def LLCR : UnaryRRE<"llcr", 0xB994, zext8, GR32, GR32>;
- def LLHR : UnaryRRE<"llhr", 0xB995, zext16, GR32, GR32>;
+ def LLCR : UnaryRRE<"llc", 0xB994, zext8, GR32, GR32>;
+ def LLHR : UnaryRRE<"llh", 0xB995, zext16, GR32, GR32>;
}
// 64-bit extensions from registers.
let neverHasSideEffects = 1 in {
- def LLGCR : UnaryRRE<"llgcr", 0xB984, zext8, GR64, GR64>;
- def LLGHR : UnaryRRE<"llghr", 0xB985, zext16, GR64, GR64>;
- def LLGFR : UnaryRRE<"llgfr", 0xB916, zext32, GR64, GR32>;
+ def LLGCR : UnaryRRE<"llgc", 0xB984, zext8, GR64, GR64>;
+ def LLGHR : UnaryRRE<"llgh", 0xB985, zext16, GR64, GR64>;
+ def LLGFR : UnaryRRE<"llgf", 0xB916, zext32, GR64, GR32>;
}
// Match 32-to-64-bit zero extensions in which the source is already
(LLGFR (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
// 32-bit extensions from memory.
-def LLC : UnaryRXY<"llc", 0xE394, zextloadi8, GR32>;
-def LLH : UnaryRXY<"llh", 0xE395, zextloadi16, GR32>;
+def LLC : UnaryRXY<"llc", 0xE394, zextloadi8, GR32, 1>;
+def LLH : UnaryRXY<"llh", 0xE395, zextloadi16, GR32, 2>;
def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_zextloadi16, GR32>;
// 64-bit extensions from memory.
-def LLGC : UnaryRXY<"llgc", 0xE390, zextloadi8, GR64>;
-def LLGH : UnaryRXY<"llgh", 0xE391, zextloadi16, GR64>;
-def LLGF : UnaryRXY<"llgf", 0xE316, zextloadi32, GR64>;
+def LLGC : UnaryRXY<"llgc", 0xE390, zextloadi8, GR64, 1>;
+def LLGH : UnaryRXY<"llgh", 0xE391, zextloadi16, GR64, 2>;
+def LLGF : UnaryRXY<"llgf", 0xE316, zextloadi32, GR64, 4>;
def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_zextloadi16, GR64>;
def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_zextloadi32, GR64>;
// Truncations of 32-bit registers to memory.
let isCodeGenOnly = 1 in {
- defm STC32 : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32>;
- defm STH32 : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32>;
+ defm STC32 : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>;
+ defm STH32 : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>;
def STHRL32 : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>;
}
// Truncations of 64-bit registers to memory.
-defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR64>;
-defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR64>;
+defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR64, 1>;
+defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR64, 2>;
def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR64>;
-defm ST : StoreRXPair<"st", 0x50, 0xE350, truncstorei32, GR64>;
+defm ST : StoreRXPair<"st", 0x50, 0xE350, truncstorei32, GR64, 4>;
def STRL : StoreRILPC<"strl", 0xC4F, aligned_truncstorei32, GR64>;
//===----------------------------------------------------------------------===//
// Byte-swapping register moves.
let neverHasSideEffects = 1 in {
- def LRVR : UnaryRRE<"lrvr", 0xB91F, bswap, GR32, GR32>;
- def LRVGR : UnaryRRE<"lrvgr", 0xB90F, bswap, GR64, GR64>;
+ def LRVR : UnaryRRE<"lrv", 0xB91F, bswap, GR32, GR32>;
+ def LRVGR : UnaryRRE<"lrvg", 0xB90F, bswap, GR64, GR64>;
}
-// Byte-swapping loads.
-def LRV : UnaryRXY<"lrv", 0xE31E, loadu<bswap>, GR32>;
-def LRVG : UnaryRXY<"lrvg", 0xE30F, loadu<bswap>, GR64>;
+// Byte-swapping loads. Unlike normal loads, these instructions are
+// allowed to access storage more than once.
+def LRV : UnaryRXY<"lrv", 0xE31E, loadu<bswap, nonvolatile_load>, GR32, 4>;
+def LRVG : UnaryRXY<"lrvg", 0xE30F, loadu<bswap, nonvolatile_load>, GR64, 8>;
-// Byte-swapping stores.
-def STRV : StoreRXY<"strv", 0xE33E, storeu<bswap>, GR32>;
-def STRVG : StoreRXY<"strvg", 0xE32F, storeu<bswap>, GR64>;
+// Likewise byte-swapping stores.
+def STRV : StoreRXY<"strv", 0xE33E, storeu<bswap, nonvolatile_store>, GR32, 4>;
+def STRVG : StoreRXY<"strvg", 0xE32F, storeu<bswap, nonvolatile_store>,
+ GR64, 8>;
//===----------------------------------------------------------------------===//
// Load address instructions
//===----------------------------------------------------------------------===//
// Load BDX-style addresses.
-let neverHasSideEffects = 1, Function = "la" in {
- let PairType = "12" in
- def LA : InstRX<0x41, (outs GR64:$dst), (ins laaddr12pair:$src),
- "la\t$dst, $src",
- [(set GR64:$dst, laaddr12pair:$src)]>;
- let PairType = "20" in
- def LAY : InstRXY<0xE371, (outs GR64:$dst), (ins laaddr20pair:$src),
- "lay\t$dst, $src",
- [(set GR64:$dst, laaddr20pair:$src)]>;
+let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isReMaterializable = 1,
+ DispKey = "la" in {
+ let DispSize = "12" in
+ def LA : InstRX<0x41, (outs GR64:$R1), (ins laaddr12pair:$XBD2),
+ "la\t$R1, $XBD2",
+ [(set GR64:$R1, laaddr12pair:$XBD2)]>;
+ let DispSize = "20" in
+ def LAY : InstRXY<0xE371, (outs GR64:$R1), (ins laaddr20pair:$XBD2),
+ "lay\t$R1, $XBD2",
+ [(set GR64:$R1, laaddr20pair:$XBD2)]>;
}
// Load a PC-relative address. There's no version of this instruction
// with a 16-bit offset, so there's no relaxation.
-let neverHasSideEffects = 1 in {
- def LARL : InstRIL<0xC00, (outs GR64:$dst), (ins pcrel32:$src),
- "larl\t$dst, $src",
- [(set GR64:$dst, pcrel32:$src)]>;
+let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
+ isReMaterializable = 1 in {
+ def LARL : InstRIL<0xC00, (outs GR64:$R1), (ins pcrel32:$I2),
+ "larl\t$R1, $I2",
+ [(set GR64:$R1, pcrel32:$I2)]>;
}
//===----------------------------------------------------------------------===//
// Negation
//===----------------------------------------------------------------------===//
-let Defs = [PSW] in {
- def LCR : UnaryRR <"lcr", 0x13, ineg, GR32, GR32>;
- def LCGR : UnaryRRE<"lcgr", 0xB903, ineg, GR64, GR64>;
- def LCGFR : UnaryRRE<"lcgfr", 0xB913, null_frag, GR64, GR32>;
+let Defs = [CC] in {
+ let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
+ def LCR : UnaryRR <"lc", 0x13, ineg, GR32, GR32>;
+ def LCGR : UnaryRRE<"lcg", 0xB903, ineg, GR64, GR64>;
+ }
+ let CCValues = 0xE, CompareZeroCCMask = 0xE in
+ def LCGFR : UnaryRRE<"lcgf", 0xB913, null_frag, GR64, GR32>;
}
defm : SXU<ineg, LCGFR>;
//===----------------------------------------------------------------------===//
let isCodeGenOnly = 1 in
- defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, zextloadi8>;
-defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, zextloadi8>;
+ defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, zextloadi8, 1>;
+defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, zextloadi8, 1>;
defm : InsertMem<"inserti8", IC32, GR32, zextloadi8, bdxaddr12pair>;
defm : InsertMem<"inserti8", IC32Y, GR32, zextloadi8, bdxaddr20pair>;
// full-width move. (We use IILF rather than something like LLILF
// for 32-bit moves because IILF leaves the upper 32 bits of the
// GR64 unchanged.)
-let isCodeGenOnly = 1 in {
+let isCodeGenOnly = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
+ isReMaterializable = 1 in {
def IILF32 : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>;
}
def IILF : BinaryRIL<"iilf", 0xC09, insertlf, GR64, imm64lf32>;
//===----------------------------------------------------------------------===//
// Plain addition.
-let Defs = [PSW] in {
+let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in {
// Addition of a register.
let isCommutable = 1 in {
- def AR : BinaryRR <"ar", 0x1A, add, GR32, GR32>;
- def AGR : BinaryRRE<"agr", 0xB908, add, GR64, GR64>;
+ defm AR : BinaryRRAndK<"a", 0x1A, 0xB9F8, add, GR32, GR32>;
+ defm AGR : BinaryRREAndK<"ag", 0xB908, 0xB9E8, add, GR64, GR64>;
}
- def AGFR : BinaryRRE<"agfr", 0xB918, null_frag, GR64, GR32>;
+ def AGFR : BinaryRRE<"agf", 0xB918, null_frag, GR64, GR32>;
// Addition of signed 16-bit immediates.
- def AHI : BinaryRI<"ahi", 0xA7A, add, GR32, imm32sx16>;
- def AGHI : BinaryRI<"aghi", 0xA7B, add, GR64, imm64sx16>;
+ defm AHI : BinaryRIAndK<"ahi", 0xA7A, 0xECD8, add, GR32, imm32sx16>;
+ defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, add, GR64, imm64sx16>;
// Addition of signed 32-bit immediates.
def AFI : BinaryRIL<"afi", 0xC29, add, GR32, simm32>;
def AGFI : BinaryRIL<"agfi", 0xC28, add, GR64, imm64sx32>;
// Addition of memory.
- defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, add, GR32, sextloadi16>;
- defm A : BinaryRXPair<"a", 0x5A, 0xE35A, add, GR32, load>;
- def AGF : BinaryRXY<"agf", 0xE318, add, GR64, sextloadi32>;
- def AG : BinaryRXY<"ag", 0xE308, add, GR64, load>;
+ defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, add, GR32, sextloadi16, 2>;
+ defm A : BinaryRXPair<"a", 0x5A, 0xE35A, add, GR32, load, 4>;
+ def AGF : BinaryRXY<"agf", 0xE318, add, GR64, sextloadi32, 4>;
+ def AG : BinaryRXY<"ag", 0xE308, add, GR64, load, 8>;
// Addition to memory.
def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>;
defm : SXB<add, GR64, AGFR>;
// Addition producing a carry.
-let Defs = [PSW] in {
+let Defs = [CC] in {
// Addition of a register.
let isCommutable = 1 in {
- def ALR : BinaryRR <"alr", 0x1E, addc, GR32, GR32>;
- def ALGR : BinaryRRE<"algr", 0xB90A, addc, GR64, GR64>;
+ defm ALR : BinaryRRAndK<"al", 0x1E, 0xB9FA, addc, GR32, GR32>;
+ defm ALGR : BinaryRREAndK<"alg", 0xB90A, 0xB9EA, addc, GR64, GR64>;
}
- def ALGFR : BinaryRRE<"algfr", 0xB91A, null_frag, GR64, GR32>;
+ def ALGFR : BinaryRRE<"algf", 0xB91A, null_frag, GR64, GR32>;
+
+ // Addition of signed 16-bit immediates.
+ def ALHSIK : BinaryRIE<"alhsik", 0xECDA, addc, GR32, imm32sx16>,
+ Requires<[FeatureDistinctOps]>;
+ def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, addc, GR64, imm64sx16>,
+ Requires<[FeatureDistinctOps]>;
// Addition of unsigned 32-bit immediates.
def ALFI : BinaryRIL<"alfi", 0xC2B, addc, GR32, uimm32>;
def ALGFI : BinaryRIL<"algfi", 0xC2A, addc, GR64, imm64zx32>;
// Addition of memory.
- defm AL : BinaryRXPair<"al", 0x5E, 0xE35E, addc, GR32, load>;
- def ALGF : BinaryRXY<"algf", 0xE31A, addc, GR64, zextloadi32>;
- def ALG : BinaryRXY<"alg", 0xE30A, addc, GR64, load>;
+ defm AL : BinaryRXPair<"al", 0x5E, 0xE35E, addc, GR32, load, 4>;
+ def ALGF : BinaryRXY<"algf", 0xE31A, addc, GR64, zextloadi32, 4>;
+ def ALG : BinaryRXY<"alg", 0xE30A, addc, GR64, load, 8>;
}
defm : ZXB<addc, GR64, ALGFR>;
// Addition producing and using a carry.
-let Defs = [PSW], Uses = [PSW] in {
+let Defs = [CC], Uses = [CC] in {
// Addition of a register.
- def ALCR : BinaryRRE<"alcr", 0xB998, adde, GR32, GR32>;
- def ALCGR : BinaryRRE<"alcgr", 0xB988, adde, GR64, GR64>;
+ def ALCR : BinaryRRE<"alc", 0xB998, adde, GR32, GR32>;
+ def ALCGR : BinaryRRE<"alcg", 0xB988, adde, GR64, GR64>;
// Addition of memory.
- def ALC : BinaryRXY<"alc", 0xE398, adde, GR32, load>;
- def ALCG : BinaryRXY<"alcg", 0xE388, adde, GR64, load>;
+ def ALC : BinaryRXY<"alc", 0xE398, adde, GR32, load, 4>;
+ def ALCG : BinaryRXY<"alcg", 0xE388, adde, GR64, load, 8>;
}
//===----------------------------------------------------------------------===//
// Plain substraction. Although immediate forms exist, we use the
// add-immediate instruction instead.
-let Defs = [PSW] in {
+let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in {
// Subtraction of a register.
- def SR : BinaryRR <"sr", 0x1B, sub, GR32, GR32>;
- def SGFR : BinaryRRE<"sgfr", 0xB919, null_frag, GR64, GR32>;
- def SGR : BinaryRRE<"sgr", 0xB909, sub, GR64, GR64>;
+ defm SR : BinaryRRAndK<"s", 0x1B, 0xB9F9, sub, GR32, GR32>;
+ def SGFR : BinaryRRE<"sgf", 0xB919, null_frag, GR64, GR32>;
+ defm SGR : BinaryRREAndK<"sg", 0xB909, 0xB9E9, sub, GR64, GR64>;
// Subtraction of memory.
- defm S : BinaryRXPair<"s", 0x5B, 0xE35B, sub, GR32, load>;
- def SGF : BinaryRXY<"sgf", 0xE319, sub, GR64, sextloadi32>;
- def SG : BinaryRXY<"sg", 0xE309, sub, GR64, load>;
+ defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, sub, GR32, sextloadi16, 2>;
+ defm S : BinaryRXPair<"s", 0x5B, 0xE35B, sub, GR32, load, 4>;
+ def SGF : BinaryRXY<"sgf", 0xE319, sub, GR64, sextloadi32, 4>;
+ def SG : BinaryRXY<"sg", 0xE309, sub, GR64, load, 8>;
}
defm : SXB<sub, GR64, SGFR>;
// Subtraction producing a carry.
-let Defs = [PSW] in {
+let Defs = [CC] in {
// Subtraction of a register.
- def SLR : BinaryRR <"slr", 0x1F, subc, GR32, GR32>;
- def SLGFR : BinaryRRE<"slgfr", 0xB91B, null_frag, GR64, GR32>;
- def SLGR : BinaryRRE<"slgr", 0xB90B, subc, GR64, GR64>;
+ defm SLR : BinaryRRAndK<"sl", 0x1F, 0xB9FB, subc, GR32, GR32>;
+ def SLGFR : BinaryRRE<"slgf", 0xB91B, null_frag, GR64, GR32>;
+ defm SLGR : BinaryRREAndK<"slg", 0xB90B, 0xB9EB, subc, GR64, GR64>;
// Subtraction of unsigned 32-bit immediates. These don't match
// subc because we prefer addc for constants.
def SLGFI : BinaryRIL<"slgfi", 0xC24, null_frag, GR64, imm64zx32>;
// Subtraction of memory.
- defm SL : BinaryRXPair<"sl", 0x5F, 0xE35F, subc, GR32, load>;
- def SLGF : BinaryRXY<"slgf", 0xE31B, subc, GR64, zextloadi32>;
- def SLG : BinaryRXY<"slg", 0xE30B, subc, GR64, load>;
+ defm SL : BinaryRXPair<"sl", 0x5F, 0xE35F, subc, GR32, load, 4>;
+ def SLGF : BinaryRXY<"slgf", 0xE31B, subc, GR64, zextloadi32, 4>;
+ def SLG : BinaryRXY<"slg", 0xE30B, subc, GR64, load, 8>;
}
defm : ZXB<subc, GR64, SLGFR>;
// Subtraction producing and using a carry.
-let Defs = [PSW], Uses = [PSW] in {
+let Defs = [CC], Uses = [CC] in {
// Subtraction of a register.
- def SLBR : BinaryRRE<"slbr", 0xB999, sube, GR32, GR32>;
- def SLGBR : BinaryRRE<"slbgr", 0xB989, sube, GR64, GR64>;
+ def SLBR : BinaryRRE<"slb", 0xB999, sube, GR32, GR32>;
+ def SLGBR : BinaryRRE<"slbg", 0xB989, sube, GR64, GR64>;
// Subtraction of memory.
- def SLB : BinaryRXY<"slb", 0xE399, sube, GR32, load>;
- def SLBG : BinaryRXY<"slbg", 0xE389, sube, GR64, load>;
+ def SLB : BinaryRXY<"slb", 0xE399, sube, GR32, load, 4>;
+ def SLBG : BinaryRXY<"slbg", 0xE389, sube, GR64, load, 8>;
}
//===----------------------------------------------------------------------===//
// AND
//===----------------------------------------------------------------------===//
-let Defs = [PSW] in {
+let Defs = [CC] in {
// ANDs of a register.
- let isCommutable = 1 in {
- def NR : BinaryRR <"nr", 0x14, and, GR32, GR32>;
- def NGR : BinaryRRE<"ngr", 0xB980, and, GR64, GR64>;
+ let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
+ defm NR : BinaryRRAndK<"n", 0x14, 0xB9F4, and, GR32, GR32>;
+ defm NGR : BinaryRREAndK<"ng", 0xB980, 0xB9E4, and, GR64, GR64>;
}
- // ANDs of a 16-bit immediate, leaving other bits unaffected.
- let isCodeGenOnly = 1 in {
- def NILL32 : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>;
- def NILH32 : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>;
+ let isConvertibleToThreeAddress = 1 in {
+ // ANDs of a 16-bit immediate, leaving other bits unaffected.
+ // The CC result only reflects the 16-bit field, not the full register.
+ let isCodeGenOnly = 1 in {
+ def NILL32 : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>;
+ def NILH32 : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>;
+ }
+ def NILL : BinaryRI<"nill", 0xA57, and, GR64, imm64ll16c>;
+ def NILH : BinaryRI<"nilh", 0xA56, and, GR64, imm64lh16c>;
+ def NIHL : BinaryRI<"nihl", 0xA55, and, GR64, imm64hl16c>;
+ def NIHH : BinaryRI<"nihh", 0xA54, and, GR64, imm64hh16c>;
+
+ // ANDs of a 32-bit immediate, leaving other bits unaffected.
+ // The CC result only reflects the 32-bit field, which means we can
+ // use it as a zero indicator for i32 operations but not otherwise.
+ let isCodeGenOnly = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in
+ def NILF32 : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>;
+ def NILF : BinaryRIL<"nilf", 0xC0B, and, GR64, imm64lf32c>;
+ def NIHF : BinaryRIL<"nihf", 0xC0A, and, GR64, imm64hf32c>;
}
- def NILL : BinaryRI<"nill", 0xA57, and, GR64, imm64ll16c>;
- def NILH : BinaryRI<"nilh", 0xA56, and, GR64, imm64lh16c>;
- def NIHL : BinaryRI<"nihl", 0xA55, and, GR64, imm64hl16c>;
- def NIHH : BinaryRI<"nihh", 0xA54, and, GR64, imm64hh16c>;
-
- // ANDs of a 32-bit immediate, leaving other bits unaffected.
- let isCodeGenOnly = 1 in
- def NILF32 : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>;
- def NILF : BinaryRIL<"nilf", 0xC0B, and, GR64, imm64lf32c>;
- def NIHF : BinaryRIL<"nihf", 0xC0A, and, GR64, imm64hf32c>;
// ANDs of memory.
- defm N : BinaryRXPair<"n", 0x54, 0xE354, and, GR32, load>;
- def NG : BinaryRXY<"ng", 0xE380, and, GR64, load>;
+ let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
+ defm N : BinaryRXPair<"n", 0x54, 0xE354, and, GR32, load, 4>;
+ def NG : BinaryRXY<"ng", 0xE380, and, GR64, load, 8>;
+ }
// AND to memory
defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, uimm8>;
// OR
//===----------------------------------------------------------------------===//
-let Defs = [PSW] in {
+let Defs = [CC] in {
// ORs of a register.
- let isCommutable = 1 in {
- def OR : BinaryRR <"or", 0x16, or, GR32, GR32>;
- def OGR : BinaryRRE<"ogr", 0xB981, or, GR64, GR64>;
+ let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
+ defm OR : BinaryRRAndK<"o", 0x16, 0xB9F6, or, GR32, GR32>;
+ defm OGR : BinaryRREAndK<"og", 0xB981, 0xB9E6, or, GR64, GR64>;
}
// ORs of a 16-bit immediate, leaving other bits unaffected.
+ // The CC result only reflects the 16-bit field, not the full register.
let isCodeGenOnly = 1 in {
def OILL32 : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>;
def OILH32 : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>;
def OIHH : BinaryRI<"oihh", 0xA58, or, GR64, imm64hh16>;
// ORs of a 32-bit immediate, leaving other bits unaffected.
- let isCodeGenOnly = 1 in
+ // The CC result only reflects the 32-bit field, which means we can
+ // use it as a zero indicator for i32 operations but not otherwise.
+ let isCodeGenOnly = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in
def OILF32 : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>;
def OILF : BinaryRIL<"oilf", 0xC0D, or, GR64, imm64lf32>;
def OIHF : BinaryRIL<"oihf", 0xC0C, or, GR64, imm64hf32>;
// ORs of memory.
- defm O : BinaryRXPair<"o", 0x56, 0xE356, or, GR32, load>;
- def OG : BinaryRXY<"og", 0xE381, or, GR64, load>;
+ let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
+ defm O : BinaryRXPair<"o", 0x56, 0xE356, or, GR32, load, 4>;
+ def OG : BinaryRXY<"og", 0xE381, or, GR64, load, 8>;
+ }
// OR to memory
defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, uimm8>;
// XOR
//===----------------------------------------------------------------------===//
-let Defs = [PSW] in {
+let Defs = [CC] in {
// XORs of a register.
- let isCommutable = 1 in {
- def XR : BinaryRR <"xr", 0x17, xor, GR32, GR32>;
- def XGR : BinaryRRE<"xgr", 0xB982, xor, GR64, GR64>;
+ let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
+ defm XR : BinaryRRAndK<"x", 0x17, 0xB9F7, xor, GR32, GR32>;
+ defm XGR : BinaryRREAndK<"xg", 0xB982, 0xB9E7, xor, GR64, GR64>;
}
// XORs of a 32-bit immediate, leaving other bits unaffected.
- let isCodeGenOnly = 1 in
+ // The CC result only reflects the 32-bit field, which means we can
+ // use it as a zero indicator for i32 operations but not otherwise.
+ let isCodeGenOnly = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in
def XILF32 : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>;
def XILF : BinaryRIL<"xilf", 0xC07, xor, GR64, imm64lf32>;
def XIHF : BinaryRIL<"xihf", 0xC06, xor, GR64, imm64hf32>;
// XORs of memory.
- defm X : BinaryRXPair<"x",0x57, 0xE357, xor, GR32, load>;
- def XG : BinaryRXY<"xg", 0xE382, xor, GR64, load>;
+ let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
+ defm X : BinaryRXPair<"x",0x57, 0xE357, xor, GR32, load, 4>;
+ def XG : BinaryRXY<"xg", 0xE382, xor, GR64, load, 8>;
+ }
// XOR to memory
defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, uimm8>;
// Multiplication of a register.
let isCommutable = 1 in {
- def MSR : BinaryRRE<"msr", 0xB252, mul, GR32, GR32>;
- def MSGR : BinaryRRE<"msgr", 0xB90C, mul, GR64, GR64>;
+ def MSR : BinaryRRE<"ms", 0xB252, mul, GR32, GR32>;
+ def MSGR : BinaryRRE<"msg", 0xB90C, mul, GR64, GR64>;
}
-def MSGFR : BinaryRRE<"msgfr", 0xB91C, null_frag, GR64, GR32>;
+def MSGFR : BinaryRRE<"msgf", 0xB91C, null_frag, GR64, GR32>;
defm : SXB<mul, GR64, MSGFR>;
// Multiplication of a signed 16-bit immediate.
def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>;
// Multiplication of memory.
-defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, sextloadi16>;
-defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load>;
-def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, sextloadi32>;
-def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load>;
+defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, sextloadi16, 2>;
+defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>;
+def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, sextloadi32, 4>;
+def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load, 8>;
// Multiplication of a register, producing two results.
-def MLGR : BinaryRRE<"mlgr", 0xB986, z_umul_lohi64, GR128, GR64>;
+def MLGR : BinaryRRE<"mlg", 0xB986, z_umul_lohi64, GR128, GR64>;
// Multiplication of memory, producing two results.
-def MLG : BinaryRXY<"mlg", 0xE386, z_umul_lohi64, GR128, load>;
+def MLG : BinaryRXY<"mlg", 0xE386, z_umul_lohi64, GR128, load, 8>;
//===----------------------------------------------------------------------===//
// Division and remainder
//===----------------------------------------------------------------------===//
// Division and remainder, from registers.
-def DSGFR : BinaryRRE<"dsgfr", 0xB91D, null_frag, GR128, GR32>;
-def DSGR : BinaryRRE<"dsgr", 0xB90D, z_sdivrem64, GR128, GR64>;
-def DLR : BinaryRRE<"dlr", 0xB997, z_udivrem32, GR128, GR32>;
-def DLGR : BinaryRRE<"dlgr", 0xB987, z_udivrem64, GR128, GR64>;
-defm : SXB<z_sdivrem64, GR128, DSGFR>;
+def DSGFR : BinaryRRE<"dsgf", 0xB91D, z_sdivrem32, GR128, GR32>;
+def DSGR : BinaryRRE<"dsg", 0xB90D, z_sdivrem64, GR128, GR64>;
+def DLR : BinaryRRE<"dl", 0xB997, z_udivrem32, GR128, GR32>;
+def DLGR : BinaryRRE<"dlg", 0xB987, z_udivrem64, GR128, GR64>;
// Division and remainder, from memory.
-def DSGF : BinaryRXY<"dsgf", 0xE31D, z_sdivrem64, GR128, sextloadi32>;
-def DSG : BinaryRXY<"dsg", 0xE30D, z_sdivrem64, GR128, load>;
-def DL : BinaryRXY<"dl", 0xE397, z_udivrem32, GR128, load>;
-def DLG : BinaryRXY<"dlg", 0xE387, z_udivrem64, GR128, load>;
+def DSGF : BinaryRXY<"dsgf", 0xE31D, z_sdivrem32, GR128, load, 4>;
+def DSG : BinaryRXY<"dsg", 0xE30D, z_sdivrem64, GR128, load, 8>;
+def DL : BinaryRXY<"dl", 0xE397, z_udivrem32, GR128, load, 4>;
+def DLG : BinaryRXY<"dlg", 0xE387, z_udivrem64, GR128, load, 8>;
//===----------------------------------------------------------------------===//
// Shifts
// Shift left.
let neverHasSideEffects = 1 in {
- def SLL : ShiftRS <"sll", 0x89, shl, GR32, shift12only>;
- def SLLG : ShiftRSY<"sllg", 0xEB0D, shl, GR64, shift20only>;
+ defm SLL : ShiftRSAndK<"sll", 0x89, 0xEBDF, shl, GR32>;
+ def SLLG : ShiftRSY<"sllg", 0xEB0D, shl, GR64>;
}
// Logical shift right.
let neverHasSideEffects = 1 in {
- def SRL : ShiftRS <"srl", 0x88, srl, GR32, shift12only>;
- def SRLG : ShiftRSY<"srlg", 0xEB0C, srl, GR64, shift20only>;
+ defm SRL : ShiftRSAndK<"srl", 0x88, 0xEBDE, srl, GR32>;
+ def SRLG : ShiftRSY<"srlg", 0xEB0C, srl, GR64>;
}
// Arithmetic shift right.
-let Defs = [PSW] in {
- def SRA : ShiftRS <"sra", 0x8A, sra, GR32, shift12only>;
- def SRAG : ShiftRSY<"srag", 0xEB0A, sra, GR64, shift20only>;
+let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
+ defm SRA : ShiftRSAndK<"sra", 0x8A, 0xEBDC, sra, GR32>;
+ def SRAG : ShiftRSY<"srag", 0xEB0A, sra, GR64>;
}
// Rotate left.
let neverHasSideEffects = 1 in {
- def RLL : ShiftRSY<"rll", 0xEB1D, rotl, GR32, shift20only>;
- def RLLG : ShiftRSY<"rllg", 0xEB1C, rotl, GR64, shift20only>;
+ def RLL : ShiftRSY<"rll", 0xEB1D, rotl, GR32>;
+ def RLLG : ShiftRSY<"rllg", 0xEB1C, rotl, GR64>;
}
// Rotate second operand left and inserted selected bits into first operand.
// These can act like 32-bit operands provided that the constant start and
-// end bits (operands 2 and 3) are in the range [32, 64)
-let Defs = [PSW] in {
+// end bits (operands 2 and 3) are in the range [32, 64).
+let Defs = [CC] in {
let isCodeGenOnly = 1 in
- def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>;
- def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>;
+ def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>;
+ let CCValues = 0xE, CompareZeroCCMask = 0xE in
+ def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>;
+}
+
+// Forms of RISBG that only affect one word of the destination register.
+// They do not set CC.
+let isCodeGenOnly = 1 in
+ def RISBLG32 : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR32>,
+ Requires<[FeatureHighWord]>;
+def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GR64, GR64>,
+ Requires<[FeatureHighWord]>;
+def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR64, GR64>,
+ Requires<[FeatureHighWord]>;
+
+// Rotate second operand left and perform a logical operation with selected
+// bits of the first operand. The CC result only describes the selected bits,
+// so isn't useful for a full comparison against zero.
+let Defs = [CC] in {
+ def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>;
+ def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>;
+ def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>;
}
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Signed comparisons.
-let Defs = [PSW] in {
+let Defs = [CC], CCValues = 0xE in {
// Comparison with a register.
- def CR : CompareRR <"cr", 0x19, z_cmp, GR32, GR32>;
- def CGFR : CompareRRE<"cgfr", 0xB930, null_frag, GR64, GR32>;
- def CGR : CompareRRE<"cgr", 0xB920, z_cmp, GR64, GR64>;
+ def CR : CompareRR <"c", 0x19, z_cmp, GR32, GR32>;
+ def CGFR : CompareRRE<"cgf", 0xB930, null_frag, GR64, GR32>;
+ def CGR : CompareRRE<"cg", 0xB920, z_cmp, GR64, GR64>;
// Comparison with a signed 16-bit immediate.
def CHI : CompareRI<"chi", 0xA7E, z_cmp, GR32, imm32sx16>;
def CGFI : CompareRIL<"cgfi", 0xC2C, z_cmp, GR64, imm64sx32>;
// Comparison with memory.
- defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_cmp, GR32, sextloadi16>;
- defm C : CompareRXPair<"c", 0x59, 0xE359, z_cmp, GR32, load>;
- def CGH : CompareRXY<"cgh", 0xE334, z_cmp, GR64, sextloadi16>;
- def CGF : CompareRXY<"cgf", 0xE330, z_cmp, GR64, sextloadi32>;
- def CG : CompareRXY<"cg", 0xE320, z_cmp, GR64, load>;
+ defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_cmp, GR32, sextloadi16, 2>;
+ defm C : CompareRXPair<"c", 0x59, 0xE359, z_cmp, GR32, load, 4>;
+ def CGH : CompareRXY<"cgh", 0xE334, z_cmp, GR64, sextloadi16, 2>;
+ def CGF : CompareRXY<"cgf", 0xE330, z_cmp, GR64, sextloadi32, 4>;
+ def CG : CompareRXY<"cg", 0xE320, z_cmp, GR64, load, 8>;
def CHRL : CompareRILPC<"chrl", 0xC65, z_cmp, GR32, aligned_sextloadi16>;
def CRL : CompareRILPC<"crl", 0xC6D, z_cmp, GR32, aligned_load>;
def CGHRL : CompareRILPC<"cghrl", 0xC64, z_cmp, GR64, aligned_sextloadi16>;
defm : SXB<z_cmp, GR64, CGFR>;
// Unsigned comparisons.
-let Defs = [PSW] in {
+let Defs = [CC], CCValues = 0xE, IsLogical = 1 in {
// Comparison with a register.
- def CLR : CompareRR <"clr", 0x15, z_ucmp, GR32, GR32>;
- def CLGFR : CompareRRE<"clgfr", 0xB931, null_frag, GR64, GR32>;
- def CLGR : CompareRRE<"clgr", 0xB921, z_ucmp, GR64, GR64>;
+ def CLR : CompareRR <"cl", 0x15, z_ucmp, GR32, GR32>;
+ def CLGFR : CompareRRE<"clgf", 0xB931, null_frag, GR64, GR32>;
+ def CLGR : CompareRRE<"clg", 0xB921, z_ucmp, GR64, GR64>;
// Comparison with a signed 32-bit immediate.
def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>;
def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>;
// Comparison with memory.
- defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load>;
- def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, zextloadi32>;
- def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load>;
+ defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>;
+ def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, zextloadi32, 4>;
+ def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load, 8>;
def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32,
aligned_zextloadi16>;
def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32,
}
defm : ZXB<z_ucmp, GR64, CLGFR>;
+// Memory-to-memory comparison.
+let mayLoad = 1, Defs = [CC] in
+ defm CLC : MemorySS<"clc", 0xD5, z_clc>;
+
+// String comparison.
+let mayLoad = 1, Defs = [CC], Uses = [R0W] in
+ defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>;
+
//===----------------------------------------------------------------------===//
// Atomic operations
//===----------------------------------------------------------------------===//
(z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap,
ADDR32:$bitshift, ADDR32:$negbitshift,
uimm32:$bitsize))]> {
- let Defs = [PSW];
+ let Defs = [CC];
let mayLoad = 1;
let mayStore = 1;
let usesCustomInserter = 1;
}
-let Defs = [PSW] in {
+let Defs = [CC] in {
defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, atomic_cmp_swap_32, GR32>;
def CSG : CmpSwapRSY<"csg", 0xEB30, atomic_cmp_swap_64, GR64>;
}
// Miscellaneous Instructions.
//===----------------------------------------------------------------------===//
+// Extract CC into bits 29 and 28 of a register.
+let Uses = [CC] in
+ def IPM : InherentRRE<"ipm", 0xB222, GR32, (z_ipm)>;
+
// Read a 32-bit access register into a GR32. As with all GR32 operations,
// the upper 32 bits of the enclosing GR64 remain unchanged, which is useful
// when a 64-bit address is stored in a pair of access registers.
-def EAR : InstRRE<0xB24F, (outs GR32:$dst), (ins access_reg:$src),
- "ear\t$dst, $src",
- [(set GR32:$dst, (z_extract_access access_reg:$src))]>;
+def EAR : InstRRE<0xB24F, (outs GR32:$R1), (ins access_reg:$R2),
+ "ear\t$R1, $R2",
+ [(set GR32:$R1, (z_extract_access access_reg:$R2))]>;
// Find leftmost one, AKA count leading zeros. The instruction actually
// returns a pair of GR64s, the first giving the number of leading zeros
// and the second giving a copy of the source with the leftmost one bit
// cleared. We only use the first result here.
-let Defs = [PSW] in {
- def FLOGR : UnaryRRE<"flogr", 0xB983, null_frag, GR128, GR64>;
+let Defs = [CC] in {
+ def FLOGR : UnaryRRE<"flog", 0xB983, null_frag, GR128, GR64>;
}
def : Pat<(ctlz GR64:$src),
(EXTRACT_SUBREG (FLOGR GR64:$src), subreg_high)>;
def ZEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
}
+// Search a block of memory for a character.
+let mayLoad = 1, Defs = [CC], Uses = [R0W] in
+ defm SRST : StringRRE<"srst", 0xb25e, z_search_string>;
+
//===----------------------------------------------------------------------===//
// Peepholes.
//===----------------------------------------------------------------------===//
(SLGFI GR64:$src1, imm64zx32n:$src2)>;
def : Pat<(sub GR64:$src1, (zextloadi32 bdxaddr20only:$addr)),
(SLGF GR64:$src1, bdxaddr20only:$addr)>;
+
+// Optimize sign-extended 1/0 selects to -1/0 selects. This is important
+// for vector legalization.
+def : Pat<(sra (shl (i32 (z_select_ccmask 1, 0, uimm8zx4:$valid, uimm8zx4:$cc)),
+ (i32 31)),
+ (i32 31)),
+ (Select32 (LHI -1), (LHI 0), uimm8zx4:$valid, uimm8zx4:$cc)>;
+def : Pat<(sra (shl (i64 (anyext (i32 (z_select_ccmask 1, 0, uimm8zx4:$valid,
+ uimm8zx4:$cc)))),
+ (i32 63)),
+ (i32 63)),
+ (Select64 (LGHI -1), (LGHI 0), uimm8zx4:$valid, uimm8zx4:$cc)>;
projects / oota-llvm.git / blobdiff