Specify S registers as D registers' sub-registers.

[oota-llvm.git] / lib / Target / Target.td

diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index 75d3d7b4f8266d99681e8b5336fcefa3402a6d81..094a4adf3ba38196aec44ec585df0300f11b0c15 100644 (file)
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -39,11 +39,16 @@ class Register<string n> {
   int SpillAlignment = 0;
 
   // Aliases - A list of registers that this register overlaps with.  A read or
-  // modification of this register can potentially read or modifie the aliased
+  // modification of this register can potentially read or modify the aliased
   // registers.
-  //
   list<Register> Aliases = [];
   
+  // SubRegs - A list of registers that are parts of this register. Note these
+  // are "immediate" sub-registers and the registers within the list do not
+  // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
+  // not [AX, AH, AL].
+  list<Register> SubRegs = [];
+
   // DwarfNumber - Number used internally by gcc/gdb to identify the register.
   // These values can be determined by locating the <target>.h file in the
   // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES.  The
@@ -52,6 +57,16 @@ class Register<string n> {
   int DwarfNumber = -1;
 }
 
+// RegisterWithSubRegs - This can be used to define instances of Register which
+// need to specify sub-registers.
+// List "subregs" specifies which registers are sub-registers to this one. This
+// is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
+// This allows the code generator to be careful not to put two values with 
+// overlapping live ranges into registers which alias.
+class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
+  let SubRegs = subregs;
+}
+
 // RegisterGroup - This can be used to define instances of Register which
 // need to specify aliases.
 // List "aliases" specifies which registers are aliased to this one.  This
@@ -165,12 +180,26 @@ class Instruction {
   bit isConvertibleToThreeAddress = 0;  // Can this 2-addr instruction promote?
   bit isCommutable = 0;     // Is this 3 operand instruction commutable?
   bit isTerminator = 0;     // Is this part of the terminator for a basic block?
+  bit isReMaterializable = 0; // Is this instruction re-materializable?
   bit hasDelaySlot = 0;     // Does this instruction have an delay slot?
   bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
   bit hasCtrlDep   = 0;     // Does this instruction r/w ctrl-flow chains?
   bit noResults    = 0;     // Does this instruction produce no results?
   
   InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
+
+  string Constraints = "";  // OperandConstraint, e.g. $src = $dst.
+  
+  /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
+  /// be encoded into the output machineinstr.
+  string DisableEncoding = "";
+}
+
+/// Imp - Helper class for specifying the implicit uses/defs set for an
+/// instruction.
+class Imp<list<Register> uses, list<Register> defs> {
+  list<Register> Uses = uses;
+  list<Register> Defs = defs;
 }
 
 /// Predicates - These are extra conditionals which are turned into instruction
@@ -204,7 +233,6 @@ def ptr_rc;
 class Operand<ValueType ty> {
   ValueType Type = ty;
   string PrintMethod = "printOperand";
-  int NumMIOperands = 1;
   dag MIOperandInfo = (ops);
 }
 
@@ -214,6 +242,17 @@ def i16imm : Operand<i16>;
 def i32imm : Operand<i32>;
 def i64imm : Operand<i64>;
 
+
+/// PredicateOperand - This can be used to define a predicate operand for an
+/// instruction.  OpTypes specifies the MIOperandInfo for the operand, and
+/// AlwaysVal specifies the value of this predicate when set to "always
+/// execute".
+class PredicateOperand<dag OpTypes, dag AlwaysVal> : Operand<OtherVT> {
+  let MIOperandInfo = OpTypes;
+  dag ExecuteAlways = AlwaysVal;
+}
+
+
 // InstrInfo - This class should only be instantiated once to provide parameters
 // which are global to the the target machine.
 //
@@ -243,6 +282,12 @@ def INLINEASM : Instruction {
   let AsmString = "";
   let Namespace = "TargetInstrInfo";
 }
+def LABEL : Instruction {
+  let OperandList = (ops i32imm:$id);
+  let AsmString = "";
+  let Namespace = "TargetInstrInfo";
+  let hasCtrlDep = 1;
+}
 
 //===----------------------------------------------------------------------===//
 // AsmWriter - This class can be implemented by targets that need to customize
@@ -326,6 +371,11 @@ class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
 }
 
 //===----------------------------------------------------------------------===//
-// Pull in the common support for DAG isel generation
+// Pull in the common support for calling conventions.
+//
+include "TargetCallingConv.td"
+
+//===----------------------------------------------------------------------===//
+// Pull in the common support for DAG isel generation.
 //
 include "TargetSelectionDAG.td"