initial implementation of addressing mode 2

[oota-llvm.git] / lib / Target / Target.td

diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index 663dfce91e49ba5cfd37fb15e88e2eb9271b6b7f..0f2b0348bef52d40749e9161dd3ace81a0bd8b03 100644 (file)
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -70,8 +70,11 @@ class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
                     list<Register> regList> {
   string Namespace = namespace;
 
-  // RegType - Specify the ValueType of the registers in this register class.
-  // Note that all registers in a register class must have the same ValueType.
+  // RegType - Specify the list ValueType of the registers in this register
+  // class.  Note that all registers in a register class must have the same
+  // ValueTypes.  This is a list because some targets permit storing different 
+  // types in same register, for example vector values with 128-bit total size,
+  // but different count/size of items, like SSE on x86.
   //
   list<ValueType> RegTypes = regTypes;
 
@@ -115,7 +118,7 @@ class DwarfRegNum<int N> {
 //===----------------------------------------------------------------------===//
 // Pull in the common support for scheduling
 //
-include "../TargetSchedule.td"
+include "TargetSchedule.td"
 
 class Predicate; // Forward def
 
@@ -144,6 +147,9 @@ class Instruction {
   // code.
   list<Predicate> Predicates = [];
 
+  // Code size.
+  int CodeSize = 0;
+
   // Added complexity passed onto matching pattern.
   int AddedComplexity  = 0;
 
@@ -165,6 +171,15 @@ class Instruction {
   bit noResults    = 0;     // Does this instruction produce no results?
   
   InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
+
+  string Constraints = "";
+}
+
+/// Imp - Helper class for specifying the implicit uses/defs set for an
+/// instruction.
+class Imp<list<Register> uses, list<Register> defs> {
+  list<Register> Uses = uses;
+  list<Register> Defs = defs;
 }
 
 /// Predicates - These are extra conditionals which are turned into instruction
@@ -186,13 +201,18 @@ def ops;
 /// of operands.
 def variable_ops;
 
+/// ptr_rc definition - Mark this operand as being a pointer value whose
+/// register class is resolved dynamically via a callback to TargetInstrInfo.
+/// FIXME: We should probably change this to a class which contain a list of
+/// flags. But currently we have but one flag.
+def ptr_rc;
+
 /// Operand Types - These provide the built-in operand types that may be used
 /// by a target.  Targets can optionally provide their own operand types as
 /// needed, though this should not be needed for RISC targets.
 class Operand<ValueType ty> {
   ValueType Type = ty;
   string PrintMethod = "printOperand";
-  int NumMIOperands = 1;
   dag MIOperandInfo = (ops);
 }
 
@@ -202,6 +222,17 @@ def i16imm : Operand<i16>;
 def i32imm : Operand<i32>;
 def i64imm : Operand<i64>;
 
+
+/// PredicateOperand - This can be used to define a predicate operand for an
+/// instruction.  OpTypes specifies the MIOperandInfo for the operand, and
+/// AlwaysVal specifies the value of this predicate when set to "always
+/// execute".
+class PredicateOperand<dag OpTypes, dag AlwaysVal> : Operand<OtherVT> {
+  let MIOperandInfo = OpTypes;
+  dag ExecuteAlways = AlwaysVal;
+}
+
+
 // InstrInfo - This class should only be instantiated once to provide parameters
 // which are global to the the target machine.
 //
@@ -224,10 +255,12 @@ class InstrInfo {
 def PHI : Instruction {
   let OperandList = (ops variable_ops);
   let AsmString = "PHINODE";
+  let Namespace = "TargetInstrInfo";
 }
 def INLINEASM : Instruction {
   let OperandList = (ops variable_ops);
   let AsmString = "";
+  let Namespace = "TargetInstrInfo";
 }
 
 //===----------------------------------------------------------------------===//
@@ -262,14 +295,6 @@ def DefaultAsmWriter : AsmWriter;
 // Target - This class contains the "global" target information
 //
 class Target {
-  // CalleeSavedRegisters - As you might guess, this is a list of the callee
-  // saved registers for a target.
-  list<Register> CalleeSavedRegisters = [];
-  
-  // PointerType - Specify the value type to be used to represent pointers in
-  // this target.  Typically this is an i32 or i64 type.
-  ValueType PointerType;
-
   // InstructionSet - Instruction set description for this target.
   InstrInfo InstructionSet;
 
@@ -322,4 +347,4 @@ class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
 //===----------------------------------------------------------------------===//
 // Pull in the common support for DAG isel generation
 //
-include "../TargetSelectionDAG.td"
+include "TargetSelectionDAG.td"