def i16 : ValueType<16 , 3>; // 16-bit integer value
def i32 : ValueType<32 , 4>; // 32-bit integer value
def i64 : ValueType<64 , 5>; // 64-bit integer value
-def i128 : ValueType<128, 5>; // 128-bit integer value
+def i128 : ValueType<128, 6>; // 128-bit integer value
def f32 : ValueType<32 , 7>; // 32-bit floating point value
def f64 : ValueType<64 , 8>; // 64-bit floating point value
def f80 : ValueType<80 , 9>; // 80-bit floating point value
-def f128 : ValueType<128, 9>; // 128-bit floating point value
-def isVoid : ValueType<0 , 11>; // Produces no value
+def f128 : ValueType<128, 10>; // 128-bit floating point value
+def FlagVT : ValueType<0 , 11>; // Condition code or machine flag
+def isVoid : ValueType<0 , 12>; // Produces no value
+def Vector : ValueType<0 , 13>; // Abstract vector value
+def v16i8 : ValueType<128, 14>; // 16 x i8 vector value
+def v8i16 : ValueType<128, 15>; // 8 x i16 vector value
+def v4i32 : ValueType<128, 16>; // 4 x i32 vector value
+def v2i64 : ValueType<128, 17>; // 2 x i64 vector value
+def v4f32 : ValueType<128, 18>; // 4 x f32 vector value
+def v2f64 : ValueType<128, 19>; // 2 x f64 vector value
//===----------------------------------------------------------------------===//
// Register file description - These classes are used to fill in the target
-// description classes in llvm/Target/MRegisterInfo.h
+// description classes.
+class RegisterClass; // Forward def
-// Register - You should define one instance of this class for each register in
-// the target machine.
-//
-class Register {
+// Register - You should define one instance of this class for each register
+// in the target machine. String n will become the "name" of the register.
+class Register<string n> {
string Namespace = "";
- string Name = "";
-}
-
-// NamedReg - If the name for the 'def' of the register should not become the
-// "name" of the register, you can use this to specify a custom name instead.
-//
-class NamedReg<string n> : Register {
- let Name = n;
+ string Name = n;
+
+ // SpillSize - If this value is set to a non-zero value, it is the size in
+ // bits of the spill slot required to hold this register. If this value is
+ // set to zero, the information is inferred from any register classes the
+ // register belongs to.
+ int SpillSize = 0;
+
+ // SpillAlignment - This value is used to specify the alignment required for
+ // spilling the register. Like SpillSize, this should only be explicitly
+ // specified if the register is not in a register class.
+ int SpillAlignment = 0;
+
+ // Aliases - A list of registers that this register overlaps with. A read or
+ // modification of this register can potentially read or modifie the aliased
+ // registers.
+ //
+ list<Register> Aliases = [];
}
-// RegisterAliases - You should define instances of this class to indicate which
-// registers in the register file are aliased together. This allows the code
-// generator to be careful not to put two values with overlapping live ranges
-// into registers which alias.
-//
-class RegisterAliases<Register reg, list<Register> aliases> {
- Register Reg = reg;
- list<Register> Aliases = aliases;
+// RegisterGroup - This can be used to define instances of Register which
+// need to specify aliases.
+// List "aliases" specifies which registers are aliased to this one. This
+// allows the code generator to be careful not to put two values with
+// overlapping live ranges into registers which alias.
+class RegisterGroup<string n, list<Register> aliases> : Register<n> {
+ let Aliases = aliases;
}
// RegisterClass - Now that all of the registers are defined, and aliases
// register classes. This also defines the default allocation order of
// registers by register allocators.
//
-class RegisterClass<ValueType regType, int alignment, list<Register> regList> {
+class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
+ list<Register> regList> {
+ string Namespace = namespace;
+
// RegType - Specify the ValueType of the registers in this register class.
// Note that all registers in a register class must have the same ValueType.
//
- ValueType RegType = regType;
+ list<ValueType> RegTypes = regTypes;
+
+ // Size - Specify the spill size in bits of the registers. A default value of
+ // zero lets tablgen pick an appropriate size.
+ int Size = 0;
// Alignment - Specify the alignment required of the registers when they are
// stored or loaded to memory.
//
- int Size = RegType.Size;
int Alignment = alignment;
// MemberList - Specify which registers are in this class. If the
//
list<Register> MemberList = regList;
- // Methods - This member can be used to insert arbitrary code into a generated
- // register class. The normal usage of this is to overload virtual methods.
- code Methods = [{}];
-
- // isDummyClass - If this is set to true, this register class is not really
- // part of the target, it is just used for other purposes.
- bit isDummyClass = 0;
+ // MethodProtos/MethodBodies - These members can be used to insert arbitrary
+ // code into a generated register class. The normal usage of this is to
+ // overload virtual methods.
+ code MethodProtos = [{}];
+ code MethodBodies = [{}];
}
+//===----------------------------------------------------------------------===//
+// Pull in the common support for scheduling
+//
+include "../TargetSchedule.td"
+
+
//===----------------------------------------------------------------------===//
// Instruction set description - These classes correspond to the C++ classes in
// the Target/TargetInstrInfo.h file.
bit isBranch = 0; // Is this instruction a branch instruction?
bit isBarrier = 0; // Can control flow fall through this instruction?
bit isCall = 0; // Is this instruction a call instruction?
+ bit isLoad = 0; // Is this instruction a load instruction?
+ bit isStore = 0; // Is this instruction a store instruction?
bit isTwoAddress = 0; // Is this a two address instruction?
+ bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
+ bit isCommutable = 0; // Is this 3 operand instruction commutable?
bit isTerminator = 0; // Is this part of the terminator for a basic block?
+ bit hasDelaySlot = 0; // Does this instruction have an delay slot?
+ bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
+
+ InstrItinClass Itinerary; // Execution steps used for scheduling.
}
/// (ops R32:$dst, R32:$src) or something similar.
def ops;
+/// variable_ops definition - Mark this instruction as taking a variable number
+/// of operands.
+def variable_ops;
+
/// Operand Types - These provide the built-in operand types that may be used
/// by a target. Targets can optionally provide their own operand types as
/// needed, though this should not be needed for RISC targets.
class Operand<ValueType ty> {
- int NumMIOperands = 1;
ValueType Type = ty;
string PrintMethod = "printOperand";
+ int NumMIOperands = 1;
+ dag MIOperandInfo = (ops);
}
def i1imm : Operand<i1>;
//
list<string> TSFlagsFields = [];
list<int> TSFlagsShifts = [];
+
+ // Target can specify its instructions in either big or little-endian formats.
+ // For instance, while both Sparc and PowerPC are big-endian platforms, the
+ // Sparc manual specifies its instructions in the format [31..0] (big), while
+ // PowerPC specifies them using the format [0..31] (little).
+ bit isLittleEndianEncoding = 0;
}
//===----------------------------------------------------------------------===//
// InstFormatName - AsmWriters can specify the name of the format string to
// print instructions with.
string InstFormatName = "AsmString";
+
+ // Variant - AsmWriters can be of multiple different variants. Variants are
+ // used to support targets that need to emit assembly code in ways that are
+ // mostly the same for different targets, but have minor differences in
+ // syntax. If the asmstring contains {|} characters in them, this integer
+ // will specify which alternative to use. For example "{x|y|z}" with Variant
+ // == 1, will expand to "y".
+ int Variant = 0;
}
def DefaultAsmWriter : AsmWriter;
// InstructionSet - Instruction set description for this target.
InstrInfo InstructionSet;
- // AssemblyWriter - The AsmWriter instance to use for this target.
- AsmWriter AssemblyWriter = DefaultAsmWriter;
+ // AssemblyWriters - The AsmWriter instances available for this target.
+ list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
}
-
//===----------------------------------------------------------------------===//
-// DAG node definitions used by the instruction selector.
+// SubtargetFeature - A characteristic of the chip set.
//
-// NOTE: all of this is a work-in-progress and should be ignored for now.
-//
-/*
-class Expander<dag pattern, list<dag> result> {
- dag Pattern = pattern;
- list<dag> Result = result;
-}
-
-class DagNodeValType;
-def DNVT_any : DagNodeValType; // No constraint on tree node
-def DNVT_void : DagNodeValType; // Tree node always returns void
-def DNVT_val : DagNodeValType; // A non-void type
-def DNVT_arg0 : DagNodeValType; // Tree node returns same type as Arg0
-def DNVT_arg1 : DagNodeValType; // Tree node returns same type as Arg1
-def DNVT_ptr : DagNodeValType; // The target pointer type
-def DNVT_i8 : DagNodeValType; // Always have an i8 value
-
-class DagNode<DagNodeValType ret, list<DagNodeValType> args> {
- DagNodeValType RetType = ret;
- list<DagNodeValType> ArgTypes = args;
- string EnumName = ?;
-}
-
-// BuiltinDagNodes are built into the instruction selector and correspond to
-// enum values.
-class BuiltinDagNode<DagNodeValType Ret, list<DagNodeValType> Args,
- string Ename> : DagNode<Ret, Args> {
- let EnumName = Ename;
+class SubtargetFeature<string n, string t, string a, string d> {
+ // Name - Feature name. Used by command line (-mattr=) to determine the
+ // appropriate target chip.
+ //
+ string Name = n;
+
+ // Type - Type of attribute to be set by feature.
+ //
+ string Type = t;
+
+ // Attribute - Attribute to be set by feature.
+ //
+ string Attribute = a;
+
+ // Desc - Feature description. Used by command line (-mattr=) to display help
+ // information.
+ //
+ string Desc = d;
}
-// Magic nodes...
-def Void : RegisterClass<isVoid,0,[]> { let isDummyClass = 1; }
-def set : DagNode<DNVT_void, [DNVT_val, DNVT_arg0]>;
-def chain : BuiltinDagNode<DNVT_void, [DNVT_void, DNVT_void], "ChainNode">;
-def blockchain : BuiltinDagNode<DNVT_void, [DNVT_void, DNVT_void],
- "BlockChainNode">;
-def ChainExpander : Expander<(chain Void, Void), []>;
-def BlockChainExpander : Expander<(blockchain Void, Void), []>;
-
-
-// Terminals...
-def imm : BuiltinDagNode<DNVT_val, [], "Constant">;
-def frameidx : BuiltinDagNode<DNVT_ptr, [], "FrameIndex">;
-def basicblock : BuiltinDagNode<DNVT_ptr, [], "BasicBlock">;
-
-// Arithmetic...
-def plus : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Plus">;
-def minus : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Minus">;
-def times : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Times">;
-def sdiv : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "SDiv">;
-def udiv : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "UDiv">;
-def srem : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "SRem">;
-def urem : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "URem">;
-def and : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "And">;
-def or : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Or">;
-def xor : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Xor">;
-
-// Comparisons...
-def seteq : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetEQ">;
-def setne : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetNE">;
-def setlt : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetLT">;
-def setle : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetLE">;
-def setgt : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetGT">;
-def setge : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetGE">;
-
-def load : BuiltinDagNode<DNVT_val, [DNVT_ptr], "Load">;
-//def store : BuiltinDagNode<DNVT_Void, [DNVT_ptr, DNVT_val]>;
-
-// Other...
-def ret : BuiltinDagNode<DNVT_void, [DNVT_val], "Ret">;
-def retvoid : BuiltinDagNode<DNVT_void, [], "RetVoid">;
-def br : BuiltinDagNode<DNVT_void, [DNVT_ptr], "Br">;
-def brcond : BuiltinDagNode<DNVT_void, [DNVT_i8, DNVT_ptr, DNVT_ptr],
- "BrCond">;
-
-def unspec1 : BuiltinDagNode<DNVT_any , [DNVT_val], "Unspec1">;
-def unspec2 : BuiltinDagNode<DNVT_any , [DNVT_val, DNVT_val], "Unspec2">;
-
//===----------------------------------------------------------------------===//
-// DAG nonterminals definitions used by the instruction selector...
+// Processor chip sets - These values represent each of the chip sets supported
+// by the scheduler. Each Processor definition requires corresponding
+// instruction itineraries.
//
-class Nonterminal<dag pattern> {
- dag Pattern = pattern;
- bit BuiltIn = 0;
+class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
+ // Name - Chip set name. Used by command line (-mcpu=) to determine the
+ // appropriate target chip.
+ //
+ string Name = n;
+
+ // ProcItin - The scheduling information for the target processor.
+ //
+ ProcessorItineraries ProcItin = pi;
+
+ // Features - list of
+ list<SubtargetFeature> Features = f;
}
-*/
+//===----------------------------------------------------------------------===//
+// Pull in the common support for DAG isel generation
+//
+include "../TargetSelectionDAG.td"
projects / oota-llvm.git / blobdiff