Add the new InstrSched directory.

[oota-llvm.git] / lib / Target / Target.td

diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index 725d3bd47a249c6b9bad4b50f98dadb850bdcbae..522a46cbc2164211cf9eb5f62ddd78744ee8382e 100644 (file)
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -43,12 +43,11 @@ def isVoid : ValueType<0  , 11>;   // Produces no value
 // description classes in llvm/Target/MRegisterInfo.h
 
 
-// Register - You should define one instance of this class for each register in
-// the target machine.
-//
-class Register {
+// Register - You should define one instance of this class for each register
+// in the target machine.  String n will become the "name" of the register.
+class RegisterBase<string n> {
   string Namespace = "";
-  string Name = "";
+  string Name = n;
 
   // SpillSize - If this value is set to a non-zero value, it is the size in
   // bits of the spill slot required to hold this register.  If this value is
@@ -62,21 +61,17 @@ class Register {
   int SpillAlignment = 0;
 }
 
-// NamedReg - If the name for the 'def' of the register should not become the
-// "name" of the register, you can use this to specify a custom name instead.
-//
-class NamedReg<string n> : Register {
-  let Name = n;
+class Register<string n> : RegisterBase<n> {
+  list<RegisterBase> Aliases = [];
 }
 
-// RegisterAliases - You should define instances of this class to indicate which
-// registers in the register file are aliased together.  This allows the code
-// generator to be careful not to put two values with overlapping live ranges
-// into registers which alias.
-//
-class RegisterAliases<Register reg, list<Register> aliases> {
-  Register Reg = reg;
-  list<Register> Aliases = aliases;
+// RegisterGroup - This can be used to define instances of Register which
+// need to specify aliases.
+// List "aliases" specifies which registers are aliased to this one.  This
+// allows the code generator to be careful not to put two values with 
+// overlapping live ranges into registers which alias.
+class RegisterGroup<string n, list<Register> aliases> : Register<n> {
+  let Aliases = aliases;
 }
 
 // RegisterClass - Now that all of the registers are defined, and aliases
@@ -135,8 +130,11 @@ class Instruction {
   bit isBranch     = 0;     // Is this instruction a branch instruction?
   bit isBarrier    = 0;     // Can control flow fall through this instruction?
   bit isCall       = 0;     // Is this instruction a call instruction?
+  bit isLoad       = 0;     // Is this instruction a load instruction?
+  bit isStore      = 0;     // Is this instruction a store instruction?
   bit isTwoAddress = 0;     // Is this a two address instruction?
   bit isTerminator = 0;     // Is this part of the terminator for a basic block?
+  bit hasDelaySlot = 0;     // Does this instruction have an delay slot?
 }
 
 
@@ -190,6 +188,14 @@ class AsmWriter {
   // InstFormatName - AsmWriters can specify the name of the format string to
   // print instructions with.
   string InstFormatName = "AsmString";
+
+  // Variant - AsmWriters can be of multiple different variants.  Variants are
+  // used to support targets that need to emit assembly code in ways that are
+  // mostly the same for different targets, but have minor differences in
+  // syntax.  If the asmstring contains {|} characters in them, this integer
+  // will specify which alternative to use.  For example "{x|y|z}" with Variant
+  // == 1, will expand to "y".
+  int Variant = 0;
 }
 def DefaultAsmWriter : AsmWriter;
 
@@ -209,8 +215,8 @@ class Target {
   // InstructionSet - Instruction set description for this target.
   InstrInfo InstructionSet;
 
-  // AssemblyWriter - The AsmWriter instance to use for this target.
-  AsmWriter AssemblyWriter = DefaultAsmWriter;
+  // AssemblyWriters - The AsmWriter instances available for this target.
+  list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
 }