Add initial support for global variables, and fix a bug in addr mode selection

[oota-llvm.git] / lib / Target / Target.td

diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index 3ce329f9f768a8121aaf12504a4491529d9f35ab..69b6baf28e9051b2f53682f746cecfb9abb910dc 100644 (file)
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -31,13 +31,20 @@ def i8     : ValueType<8  ,  2>;   // 8-bit integer value
 def i16    : ValueType<16 ,  3>;   // 16-bit integer value
 def i32    : ValueType<32 ,  4>;   // 32-bit integer value
 def i64    : ValueType<64 ,  5>;   // 64-bit integer value
-def i128   : ValueType<128,  5>;   // 128-bit integer value
+def i128   : ValueType<128,  6>;   // 128-bit integer value
 def f32    : ValueType<32 ,  7>;   // 32-bit floating point value
 def f64    : ValueType<64 ,  8>;   // 64-bit floating point value
 def f80    : ValueType<80 ,  9>;   // 80-bit floating point value
 def f128   : ValueType<128, 10>;   // 128-bit floating point value
 def FlagVT : ValueType<0  , 11>;   // Condition code or machine flag
 def isVoid : ValueType<0  , 12>;   // Produces no value
+def Vector : ValueType<0  , 13>;   // Abstract vector value
+def v16i8  : ValueType<128, 14>;   // 16 x i8  vector value
+def v8i16  : ValueType<128, 15>;   //  8 x i16 vector value
+def v4i32  : ValueType<128, 16>;   //  4 x i32 vector value
+def v2i64  : ValueType<128, 17>;   //  2 x i64 vector value
+def v4f32  : ValueType<128, 18>;   //  4 x f32 vector value
+def v2f64  : ValueType<128, 19>;   //  2 x f64 vector value
 
 //===----------------------------------------------------------------------===//
 // Register file description - These classes are used to fill in the target
@@ -83,19 +90,22 @@ class RegisterGroup<string n, list<Register> aliases> : Register<n> {
 // register classes.  This also defines the default allocation order of
 // registers by register allocators.
 //
-class RegisterClass<string namespace, ValueType regType, int alignment,
+class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
                     list<Register> regList> {
   string Namespace = namespace;
 
   // RegType - Specify the ValueType of the registers in this register class.
   // Note that all registers in a register class must have the same ValueType.
   //
-  ValueType RegType = regType;
+  list<ValueType> RegTypes = regTypes;
+
+  // Size - Specify the spill size in bits of the registers.  A default value of
+  // zero lets tablgen pick an appropriate size.
+  int Size = 0;
 
   // Alignment - Specify the alignment required of the registers when they are
   // stored or loaded to memory.
   //
-  int Size = RegType.Size;
   int Alignment = alignment;
 
   // MemberList - Specify which registers are in this class.  If the
@@ -117,6 +127,7 @@ class RegisterClass<string namespace, ValueType regType, int alignment,
 //
 include "../TargetSchedule.td"
 
+class Predicate; // Forward def
 
 //===----------------------------------------------------------------------===//
 // Instruction set description - These classes correspond to the C++ classes in
@@ -139,6 +150,10 @@ class Instruction {
   list<Register> Uses = []; // Default to using no non-operand registers
   list<Register> Defs = []; // Default to modifying no non-operand registers
 
+  // Predicates - List of predicates which will be turned into isel matching
+  // code.
+  list<Predicate> Predicates = [];
+
   // These bits capture information about the high-level semantics of the
   // instruction.
   bit isReturn     = 0;     // Is this instruction a return instruction?
@@ -153,10 +168,20 @@ class Instruction {
   bit isTerminator = 0;     // Is this part of the terminator for a basic block?
   bit hasDelaySlot = 0;     // Does this instruction have an delay slot?
   bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
+  bit hasCtrlDep   = 0;     // Does this instruction r/w ctrl-flow chains?
   
   InstrItinClass Itinerary; // Execution steps used for scheduling. 
 }
 
+/// Predicates - These are extra conditionals which are turned into instruction
+/// selector matching code. Currently each predicate is just a string.
+class Predicate<string cond> {
+  string CondString = cond;
+}
+
+class Requires<list<Predicate> preds> {
+  list<Predicate> Predicates = preds;
+}
 
 /// ops definition - This is just a simple marker used to identify the operands
 /// list for an instruction.  This should be used like this:
@@ -171,9 +196,10 @@ def variable_ops;
 /// by a target.  Targets can optionally provide their own operand types as
 /// needed, though this should not be needed for RISC targets.
 class Operand<ValueType ty> {
-  int NumMIOperands = 1;
   ValueType Type = ty;
   string PrintMethod = "printOperand";
+  int NumMIOperands = 1;
+  dag MIOperandInfo = (ops);
 }
 
 def i1imm  : Operand<i1>;
@@ -252,12 +278,20 @@ class Target {
 //===----------------------------------------------------------------------===//
 // SubtargetFeature - A characteristic of the chip set.
 //
-class SubtargetFeature<string n, string d> {
+class SubtargetFeature<string n, string t, string a, string d> {
   // Name - Feature name.  Used by command line (-mattr=) to determine the
   // appropriate target chip.
   //
   string Name = n;
   
+  // Type - Type of attribute to be set by feature.
+  //
+  string Type = t;
+  
+  // Attribute - Attribute to be set by feature.
+  //
+  string Attribute = a;
+  
   // Desc - Feature description.  Used by command line (-mattr=) to display help
   // information.
   //