Treat common as distinct from weak global on Darwin x86.

[oota-llvm.git] / lib / Target / Target.td

diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index d155e713c0db95987971c2f00d0c26b48ccaf419..6e2ba91b95ff8ef6c8868ee7ea8d7f72e7b2f381 100644 (file)
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -25,6 +25,7 @@ class RegisterClass; // Forward def
 // in the target machine.  String n will become the "name" of the register.
 class Register<string n> {
   string Namespace = "";
+  string AsmName = n;
   string Name = n;
 
   // SpillSize - If this value is set to a non-zero value, it is the size in
@@ -192,7 +193,6 @@ class Instruction {
   bit isSimpleLoad = 0;     // Is this just a load instruction?
   bit mayLoad      = 0;     // Is it possible for this inst to read memory?
   bit mayStore     = 0;     // Is it possible for this inst to write memory?
-  bit isImplicitDef = 0;    // Is this instruction an implicit def instruction?
   bit isTwoAddress = 0;     // Is this a two address instruction?
   bit isConvertibleToThreeAddress = 0;  // Can this 2-addr instruction promote?
   bit isCommutable = 0;     // Is this 3 operand instruction commutable?
@@ -262,6 +262,10 @@ def variable_ops;
 /// flags. But currently we have but one flag.
 def ptr_rc;
 
+/// unknown definition - Mark this operand as being of unknown type, causing
+/// it to be resolved by inference in the context it is used.
+def unknown;
+
 /// Operand Types - These provide the built-in operand types that may be used
 /// by a target.  Targets can optionally provide their own operand types as
 /// needed, though this should not be needed for RISC targets.
@@ -277,6 +281,9 @@ def i16imm : Operand<i16>;
 def i32imm : Operand<i32>;
 def i64imm : Operand<i64>;
 
+def f32imm : Operand<f32>;
+def f64imm : Operand<f64>;
+
 /// zero_reg definition - Special node to stand for the zero register.
 ///
 def zero_reg;
@@ -334,21 +341,43 @@ def INLINEASM : Instruction {
 }
 def LABEL : Instruction {
   let OutOperandList = (ops);
-  let InOperandList = (ops i32imm:$id);
+  let InOperandList = (ops i32imm:$id, i32imm:$flavor);
   let AsmString = "";
   let Namespace = "TargetInstrInfo";
   let hasCtrlDep = 1;
 }
-def EXTRACT_SUBREG : Instruction {
-        let OutOperandList = (ops variable_ops);
+def DECLARE : Instruction {
+  let OutOperandList = (ops);
   let InOperandList = (ops variable_ops);
   let AsmString = "";
   let Namespace = "TargetInstrInfo";
+  let hasCtrlDep = 1;
+}
+def EXTRACT_SUBREG : Instruction {
+  let OutOperandList = (ops unknown:$dst);
+  let InOperandList = (ops unknown:$supersrc, i32imm:$subidx);
+  let AsmString = "";
+  let Namespace = "TargetInstrInfo";
   let neverHasSideEffects = 1;
 }
 def INSERT_SUBREG : Instruction {
-        let OutOperandList = (ops variable_ops);
-  let InOperandList = (ops variable_ops);
+  let OutOperandList = (ops unknown:$dst);
+  let InOperandList = (ops unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
+  let AsmString = "";
+  let Namespace = "TargetInstrInfo";
+  let neverHasSideEffects = 1;
+  let Constraints = "$supersrc = $dst";
+}
+def IMPLICIT_DEF : Instruction {
+  let OutOperandList = (ops unknown:$dst);
+  let InOperandList = (ops);
+  let AsmString = "";
+  let Namespace = "TargetInstrInfo";
+  let neverHasSideEffects = 1;
+}
+def SUBREG_TO_REG : Instruction {
+  let OutOperandList = (ops unknown:$dst);
+  let InOperandList = (ops unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
   let AsmString = "";
   let Namespace = "TargetInstrInfo";
   let neverHasSideEffects = 1;