Classes need to have a prefix name, so that they can be tacked on to the pieces

[oota-llvm.git] / lib / Target / Target.td

diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index c05d3faaad58f323608de01c0bcb1fcd73f88e2f..6fada3452e6068ca5171613b181ad579db9a34f8 100644 (file)
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -1,4 +1,4 @@
-//===- Target.td - Target Independent TableGen interface --------*- C++ -*-===//
+//===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
 // 
 //                     The LLVM Compiler Infrastructure
 //
@@ -105,30 +105,32 @@ class RegisterClass<ValueType regType, int alignment, list<Register> regList> {
 // Instruction set description - These classes correspond to the C++ classes in
 // the Target/TargetInstrInfo.h file.
 //
-
 class Instruction {
-  string Name;          // The opcode string for this instruction
+  string Name = "";         // The opcode string for this instruction
   string Namespace = "";
+  string ClassPrefix = "";
+
+  dag OperandList;          // An dag containing the MI operand list.
+  string AsmString = "";    // The .s format to print the instruction with.
+
+  // Pattern - Set to the DAG pattern for this instruction, if we know of one,
+  // otherwise, uninitialized.
+  list<dag> Pattern;
+
+  // The follow state will eventually be inferred automatically from the
+  // instruction pattern.
 
-  list<Register> Uses = [];  // Default to using no non-operand registers
-  list<Register> Defs = [];  // Default to modifying no non-operand registers
+  list<Register> Uses = []; // Default to using no non-operand registers
+  list<Register> Defs = []; // Default to modifying no non-operand registers
 
   // These bits capture information about the high-level semantics of the
   // instruction.
   bit isReturn     = 0;     // Is this instruction a return instruction?
   bit isBranch     = 0;     // Is this instruction a branch instruction?
+  bit isBarrier    = 0;     // Can control flow fall through this instruction?
   bit isCall       = 0;     // Is this instruction a call instruction?
   bit isTwoAddress = 0;     // Is this a two address instruction?
   bit isTerminator = 0;     // Is this part of the terminator for a basic block?
-
-  // Pattern - Set to the DAG pattern for this instruction, if we know of one,
-  // otherwise, uninitialized.
-  dag Pattern;
-}
-
-class Expander<dag pattern, list<dag> result> {
-  dag Pattern      = pattern;
-  list<dag> Result = result;
 }
 
 
@@ -146,6 +148,14 @@ class InstrInfo {
   list<int>    TSFlagsShifts = [];
 }
 
+/// ops definition - This is just a simple marker used to identify the operands
+/// list for an instruction.  This should be used like this:
+///     (ops R32:$dst, R32:$src) or something similar.
+def ops;
+def i8imm;
+def i16imm;
+def i32imm;
+def i64imm;
 
 //===----------------------------------------------------------------------===//
 // Target - This class contains the "global" target information
@@ -165,8 +175,16 @@ class Target {
 
 
 //===----------------------------------------------------------------------===//
-// DAG node definitions used by the instruction selector...
+// DAG node definitions used by the instruction selector.
 //
+// NOTE: all of this is a work-in-progress and should be ignored for now.
+//
+
+class Expander<dag pattern, list<dag> result> {
+  dag Pattern      = pattern;
+  list<dag> Result = result;
+}
+
 class DagNodeValType;
 def DNVT_any   : DagNodeValType;  // No constraint on tree node
 def DNVT_void  : DagNodeValType;  // Tree node always returns void