-//===- Target.td - Target Independent TableGen interface --------*- C++ -*-===//
+//===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
//
// This file defines the target-independent interfaces which should be
// implemented by each target which is using a TableGen based code generator.
int Value = value;
}
+def OtherVT: ValueType<0 , 0>; // "Other" value
def i1 : ValueType<1 , 1>; // One bit boolean value
def i8 : ValueType<8 , 2>; // 8-bit integer value
def i16 : ValueType<16 , 3>; // 16-bit integer value
// Instruction set description - These classes correspond to the C++ classes in
// the Target/TargetInstrInfo.h file.
//
-
class Instruction {
- string Name; // The opcode string for this instruction
+ string Name = ""; // The opcode string for this instruction
string Namespace = "";
+ string ClassPrefix = "";
+
+ dag OperandList; // An dag containing the MI operand list.
+ string AsmString = ""; // The .s format to print the instruction with.
+
+ // Pattern - Set to the DAG pattern for this instruction, if we know of one,
+ // otherwise, uninitialized.
+ list<dag> Pattern;
+
+ // The follow state will eventually be inferred automatically from the
+ // instruction pattern.
- list<Register> Uses = []; // Default to using no non-operand registers
- list<Register> Defs = []; // Default to modifying no non-operand registers
+ list<Register> Uses = []; // Default to using no non-operand registers
+ list<Register> Defs = []; // Default to modifying no non-operand registers
// These bits capture information about the high-level semantics of the
// instruction.
bit isReturn = 0; // Is this instruction a return instruction?
bit isBranch = 0; // Is this instruction a branch instruction?
+ bit isBarrier = 0; // Can control flow fall through this instruction?
bit isCall = 0; // Is this instruction a call instruction?
bit isTwoAddress = 0; // Is this a two address instruction?
bit isTerminator = 0; // Is this part of the terminator for a basic block?
-
- // Pattern - Set to the DAG pattern for this instruction, if we know of one,
- // otherwise, uninitialized.
- dag Pattern;
-}
-
-class Expander<dag pattern, list<dag> result> {
- dag Pattern = pattern;
- list<dag> Result = result;
}
list<int> TSFlagsShifts = [];
}
+/// ops definition - This is just a simple marker used to identify the operands
+/// list for an instruction. This should be used like this:
+/// (ops R32:$dst, R32:$src) or something similar.
+def ops;
+def i8imm;
+def i16imm;
+def i32imm;
+def i64imm;
//===----------------------------------------------------------------------===//
// Target - This class contains the "global" target information
//===----------------------------------------------------------------------===//
-// DAG node definitions used by the instruction selector...
+// DAG node definitions used by the instruction selector.
+//
+// NOTE: all of this is a work-in-progress and should be ignored for now.
//
+
+class Expander<dag pattern, list<dag> result> {
+ dag Pattern = pattern;
+ list<dag> Result = result;
+}
+
class DagNodeValType;
def DNVT_any : DagNodeValType; // No constraint on tree node
def DNVT_void : DagNodeValType; // Tree node always returns void