bit isSimpleLoad = 0; // Is this just a load instruction?
bit mayLoad = 0; // Is it possible for this inst to read memory?
bit mayStore = 0; // Is it possible for this inst to write memory?
- bit isImplicitDef = 0; // Is this instruction an implicit def instruction?
bit isTwoAddress = 0; // Is this a two address instruction?
bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
bit isCommutable = 0; // Is this 3 operand instruction commutable?
bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
+ bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
// Side effect flags - When set, the flags have these meanings:
//
// hasSideEffects - The instruction has side effects that are not
// captured by any operands of the instruction or other flags.
+ //
// mayHaveSideEffects - Some instances of the instruction can have side
// effects. The virtual method "isReallySideEffectFree" is called to
// determine this. Load instructions are an example of where this is
// useful. In general, loads always have side effects. However, loads from
// constant pools don't. Individual back ends make this determination.
+ //
// neverHasSideEffects - Set on an instruction with no pattern if it has no
// side effects.
bit hasSideEffects = 0;
bit mayHaveSideEffects = 0;
bit neverHasSideEffects = 0;
-
+
InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
/// flags. But currently we have but one flag.
def ptr_rc;
+/// unknown definition - Mark this operand as being of unknown type, causing
+/// it to be resolved by inference in the context it is used.
+def unknown;
+
/// Operand Types - These provide the built-in operand types that may be used
/// by a target. Targets can optionally provide their own operand types as
/// needed, though this should not be needed for RISC targets.
let hasCtrlDep = 1;
}
def EXTRACT_SUBREG : Instruction {
- let OutOperandList = (ops variable_ops);
- let InOperandList = (ops variable_ops);
+ let OutOperandList = (ops unknown:$dst);
+ let InOperandList = (ops unknown:$supersrc, i32imm:$subidx);
let AsmString = "";
let Namespace = "TargetInstrInfo";
let neverHasSideEffects = 1;
}
def INSERT_SUBREG : Instruction {
- let OutOperandList = (ops variable_ops);
- let InOperandList = (ops variable_ops);
+ let OutOperandList = (ops unknown:$dst);
+ let InOperandList = (ops unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
+ let AsmString = "";
+ let Namespace = "TargetInstrInfo";
+ let neverHasSideEffects = 1;
+ let Constraints = "$supersrc = $dst";
+}
+def IMPLICIT_DEF : Instruction {
+ let OutOperandList = (ops unknown:$dst);
+ let InOperandList = (ops);
+ let AsmString = "";
+ let Namespace = "TargetInstrInfo";
+ let neverHasSideEffects = 1;
+}
+def SUBREG_TO_REG : Instruction {
+ let OutOperandList = (ops unknown:$dst);
+ let InOperandList = (ops unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
let AsmString = "";
let Namespace = "TargetInstrInfo";
let neverHasSideEffects = 1;