Disable x86 fastcc from passing args in registers

[oota-llvm.git] / lib / Target / Target.td

diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index 46a1b470c492c0909617e1aa95fcf059e661a564..a82cb6c4e42e2ed8711ba56ba86485c61735d9cb 100644 (file)
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -12,39 +12,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-
-//===----------------------------------------------------------------------===//
-//
-// Value types - These values correspond to the register types defined in the
-// ValueTypes.h file.  If you update anything here, you must update it there as
-// well!
-//
-class ValueType<int size, int value> {
-  string Namespace = "MVT";
-  int Size = size;
-  int Value = value;
-}
-
-def OtherVT: ValueType<0  ,  0>;   // "Other" value
-def i1     : ValueType<1  ,  1>;   // One bit boolean value
-def i8     : ValueType<8  ,  2>;   // 8-bit integer value
-def i16    : ValueType<16 ,  3>;   // 16-bit integer value
-def i32    : ValueType<32 ,  4>;   // 32-bit integer value
-def i64    : ValueType<64 ,  5>;   // 64-bit integer value
-def i128   : ValueType<128,  6>;   // 128-bit integer value
-def f32    : ValueType<32 ,  7>;   // 32-bit floating point value
-def f64    : ValueType<64 ,  8>;   // 64-bit floating point value
-def f80    : ValueType<80 ,  9>;   // 80-bit floating point value
-def f128   : ValueType<128, 10>;   // 128-bit floating point value
-def FlagVT : ValueType<0  , 11>;   // Condition code or machine flag
-def isVoid : ValueType<0  , 12>;   // Produces no value
-def Vector : ValueType<0  , 13>;   // Abstract vector value
-def v16i8  : ValueType<128, 14>;   // 16 x i8  vector value
-def v8i16  : ValueType<128, 15>;   //  8 x i16 vector value
-def v4i32  : ValueType<128, 16>;   //  4 x i32 vector value
-def v2i64  : ValueType<128, 17>;   //  2 x i64 vector value
-def v4f32  : ValueType<128, 18>;   //  4 x f32 vector value
-def v2f64  : ValueType<128, 19>;   //  2 x f64 vector value
+include "llvm/CodeGen/ValueTypes.td"
 
 //===----------------------------------------------------------------------===//
 // Register file description - These classes are used to fill in the target
@@ -127,6 +95,7 @@ class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
 //
 include "../TargetSchedule.td"
 
+class Predicate; // Forward def
 
 //===----------------------------------------------------------------------===//
 // Instruction set description - These classes correspond to the C++ classes in
@@ -149,6 +118,10 @@ class Instruction {
   list<Register> Uses = []; // Default to using no non-operand registers
   list<Register> Defs = []; // Default to modifying no non-operand registers
 
+  // Predicates - List of predicates which will be turned into isel matching
+  // code.
+  list<Predicate> Predicates = [];
+
   // These bits capture information about the high-level semantics of the
   // instruction.
   bit isReturn     = 0;     // Is this instruction a return instruction?
@@ -163,10 +136,21 @@ class Instruction {
   bit isTerminator = 0;     // Is this part of the terminator for a basic block?
   bit hasDelaySlot = 0;     // Does this instruction have an delay slot?
   bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
+  bit hasCtrlDep   = 0;     // Does this instruction r/w ctrl-flow chains?
+  bit noResults    = 0;     // Does this instruction produce no results?
   
-  InstrItinClass Itinerary; // Execution steps used for scheduling. 
+  InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
+}
+
+/// Predicates - These are extra conditionals which are turned into instruction
+/// selector matching code. Currently each predicate is just a string.
+class Predicate<string cond> {
+  string CondString = cond;
 }
 
+class Requires<list<Predicate> preds> {
+  list<Predicate> Predicates = preds;
+}
 
 /// ops definition - This is just a simple marker used to identify the operands
 /// list for an instruction.  This should be used like this:
@@ -197,8 +181,6 @@ def i64imm : Operand<i64>;
 // which are global to the the target machine.
 //
 class InstrInfo {
-  Instruction PHIInst;
-
   // If the target wants to associate some target-specific information with each
   // instruction, it should provide these two lists to indicate how to assemble
   // the target specific information into the 32 bits available.
@@ -213,6 +195,16 @@ class InstrInfo {
   bit isLittleEndianEncoding = 0;
 }
 
+// Standard Instructions.
+def PHI : Instruction {
+  let OperandList = (ops variable_ops);
+  let AsmString = "PHINODE";
+}
+def INLINEASM : Instruction {
+  let OperandList = (ops variable_ops);
+  let AsmString = "";
+}
+
 //===----------------------------------------------------------------------===//
 // AsmWriter - This class can be implemented by targets that need to customize
 // the format of the .s file writer.
@@ -263,20 +255,20 @@ class Target {
 //===----------------------------------------------------------------------===//
 // SubtargetFeature - A characteristic of the chip set.
 //
-class SubtargetFeature<string n, string t, string a, string d> {
+class SubtargetFeature<string n, string a,  string v, string d> {
   // Name - Feature name.  Used by command line (-mattr=) to determine the
   // appropriate target chip.
   //
   string Name = n;
   
-  // Type - Type of attribute to be set by feature.
-  //
-  string Type = t;
-  
   // Attribute - Attribute to be set by feature.
   //
   string Attribute = a;
   
+  // Value - Value the attribute to be set to by feature.
+  //
+  string Value = v;
+  
   // Desc - Feature description.  Used by command line (-mattr=) to display help
   // information.
   //