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[oota-llvm.git] / lib / Target / Target.td

diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index 57046b826ee9d7b7ea7a0e2ae651cb2e9353d0f0..b1ef5c935798b3d7f90a4b22c07523c07441acb8 100644 (file)
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -39,7 +39,7 @@ class Register<string n> {
   int SpillAlignment = 0;
 
   // Aliases - A list of registers that this register overlaps with.  A read or
-  // modification of this register can potentially read or modifie the aliased
+  // modification of this register can potentially read or modify the aliased
   // registers.
   //
   list<Register> Aliases = [];
@@ -118,7 +118,7 @@ class DwarfRegNum<int N> {
 //===----------------------------------------------------------------------===//
 // Pull in the common support for scheduling
 //
-include "../TargetSchedule.td"
+include "TargetSchedule.td"
 
 class Predicate; // Forward def
 
@@ -147,6 +147,9 @@ class Instruction {
   // code.
   list<Predicate> Predicates = [];
 
+  // Code size.
+  int CodeSize = 0;
+
   // Added complexity passed onto matching pattern.
   int AddedComplexity  = 0;
 
@@ -162,12 +165,26 @@ class Instruction {
   bit isConvertibleToThreeAddress = 0;  // Can this 2-addr instruction promote?
   bit isCommutable = 0;     // Is this 3 operand instruction commutable?
   bit isTerminator = 0;     // Is this part of the terminator for a basic block?
+  bit isReMaterializable = 0; // Is this instruction re-materializable?
   bit hasDelaySlot = 0;     // Does this instruction have an delay slot?
   bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
   bit hasCtrlDep   = 0;     // Does this instruction r/w ctrl-flow chains?
   bit noResults    = 0;     // Does this instruction produce no results?
   
   InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
+
+  string Constraints = "";  // OperandConstraint, e.g. $src = $dst.
+  
+  /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
+  /// be encoded into the output machineinstr.
+  string DisableEncoding = "";
+}
+
+/// Imp - Helper class for specifying the implicit uses/defs set for an
+/// instruction.
+class Imp<list<Register> uses, list<Register> defs> {
+  list<Register> Uses = uses;
+  list<Register> Defs = defs;
 }
 
 /// Predicates - These are extra conditionals which are turned into instruction
@@ -189,13 +206,18 @@ def ops;
 /// of operands.
 def variable_ops;
 
+/// ptr_rc definition - Mark this operand as being a pointer value whose
+/// register class is resolved dynamically via a callback to TargetInstrInfo.
+/// FIXME: We should probably change this to a class which contain a list of
+/// flags. But currently we have but one flag.
+def ptr_rc;
+
 /// Operand Types - These provide the built-in operand types that may be used
 /// by a target.  Targets can optionally provide their own operand types as
 /// needed, though this should not be needed for RISC targets.
 class Operand<ValueType ty> {
   ValueType Type = ty;
   string PrintMethod = "printOperand";
-  int NumMIOperands = 1;
   dag MIOperandInfo = (ops);
 }
 
@@ -205,6 +227,17 @@ def i16imm : Operand<i16>;
 def i32imm : Operand<i32>;
 def i64imm : Operand<i64>;
 
+
+/// PredicateOperand - This can be used to define a predicate operand for an
+/// instruction.  OpTypes specifies the MIOperandInfo for the operand, and
+/// AlwaysVal specifies the value of this predicate when set to "always
+/// execute".
+class PredicateOperand<dag OpTypes, dag AlwaysVal> : Operand<OtherVT> {
+  let MIOperandInfo = OpTypes;
+  dag ExecuteAlways = AlwaysVal;
+}
+
+
 // InstrInfo - This class should only be instantiated once to provide parameters
 // which are global to the the target machine.
 //
@@ -234,6 +267,12 @@ def INLINEASM : Instruction {
   let AsmString = "";
   let Namespace = "TargetInstrInfo";
 }
+def LABEL : Instruction {
+  let OperandList = (ops i32imm:$id);
+  let AsmString = "";
+  let Namespace = "TargetInstrInfo";
+  let hasCtrlDep = 1;
+}
 
 //===----------------------------------------------------------------------===//
 // AsmWriter - This class can be implemented by targets that need to customize
@@ -267,14 +306,6 @@ def DefaultAsmWriter : AsmWriter;
 // Target - This class contains the "global" target information
 //
 class Target {
-  // CalleeSavedRegisters - As you might guess, this is a list of the callee
-  // saved registers for a target.
-  list<Register> CalleeSavedRegisters = [];
-  
-  // PointerType - Specify the value type to be used to represent pointers in
-  // this target.  Typically this is an i32 or i64 type.
-  ValueType PointerType;
-
   // InstructionSet - Instruction set description for this target.
   InstrInfo InstructionSet;
 
@@ -325,6 +356,11 @@ class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
 }
 
 //===----------------------------------------------------------------------===//
-// Pull in the common support for DAG isel generation
+// Pull in the common support for calling conventions.
+//
+include "TargetCallingConv.td"
+
+//===----------------------------------------------------------------------===//
+// Pull in the common support for DAG isel generation.
 //
-include "../TargetSelectionDAG.td"
+include "TargetSelectionDAG.td"