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[oota-llvm.git] / lib / Target / Target.td

diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index eeda4f9fe06e7f5e42464781b5282ca4eeb29f88..b2dbb5b9b923f7ac125d40c91b45d05e3190e89a 100644 (file)
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -90,19 +90,22 @@ class RegisterGroup<string n, list<Register> aliases> : Register<n> {
 // register classes.  This also defines the default allocation order of
 // registers by register allocators.
 //
-class RegisterClass<string namespace, ValueType regType, int alignment,
+class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
                     list<Register> regList> {
   string Namespace = namespace;
 
   // RegType - Specify the ValueType of the registers in this register class.
   // Note that all registers in a register class must have the same ValueType.
   //
-  ValueType RegType = regType;
+  list<ValueType> RegTypes = regTypes;
+
+  // Size - Specify the spill size in bits of the registers.  A default value of
+  // zero lets tablgen pick an appropriate size.
+  int Size = 0;
 
   // Alignment - Specify the alignment required of the registers when they are
   // stored or loaded to memory.
   //
-  int Size = RegType.Size;
   int Alignment = alignment;
 
   // MemberList - Specify which registers are in this class.  If the
@@ -124,6 +127,7 @@ class RegisterClass<string namespace, ValueType regType, int alignment,
 //
 include "../TargetSchedule.td"
 
+class Predicate; // Forward def
 
 //===----------------------------------------------------------------------===//
 // Instruction set description - These classes correspond to the C++ classes in
@@ -146,6 +150,10 @@ class Instruction {
   list<Register> Uses = []; // Default to using no non-operand registers
   list<Register> Defs = []; // Default to modifying no non-operand registers
 
+  // Predicates - List of predicates which will be turned into isel matching
+  // code.
+  list<Predicate> Predicates = [];
+
   // These bits capture information about the high-level semantics of the
   // instruction.
   bit isReturn     = 0;     // Is this instruction a return instruction?
@@ -160,10 +168,21 @@ class Instruction {
   bit isTerminator = 0;     // Is this part of the terminator for a basic block?
   bit hasDelaySlot = 0;     // Does this instruction have an delay slot?
   bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
+  bit hasCtrlDep   = 0;     // Does this instruction r/w ctrl-flow chains?
+  bit noResults    = 0;     // Does this instruction produce no results?
   
-  InstrItinClass Itinerary; // Execution steps used for scheduling. 
+  InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
 }
 
+/// Predicates - These are extra conditionals which are turned into instruction
+/// selector matching code. Currently each predicate is just a string.
+class Predicate<string cond> {
+  string CondString = cond;
+}
+
+class Requires<list<Predicate> preds> {
+  list<Predicate> Predicates = preds;
+}
 
 /// ops definition - This is just a simple marker used to identify the operands
 /// list for an instruction.  This should be used like this:
@@ -194,8 +213,6 @@ def i64imm : Operand<i64>;
 // which are global to the the target machine.
 //
 class InstrInfo {
-  Instruction PHIInst;
-
   // If the target wants to associate some target-specific information with each
   // instruction, it should provide these two lists to indicate how to assemble
   // the target specific information into the 32 bits available.
@@ -210,6 +227,16 @@ class InstrInfo {
   bit isLittleEndianEncoding = 0;
 }
 
+// Standard Instructions.
+def PHI : Instruction {
+  let OperandList = (ops variable_ops);
+  let AsmString = "PHINODE";
+}
+def INLINEASM : Instruction {
+  let OperandList = (ops variable_ops);
+  let AsmString = "";
+}
+
 //===----------------------------------------------------------------------===//
 // AsmWriter - This class can be implemented by targets that need to customize
 // the format of the .s file writer.
@@ -260,20 +287,20 @@ class Target {
 //===----------------------------------------------------------------------===//
 // SubtargetFeature - A characteristic of the chip set.
 //
-class SubtargetFeature<string n, string t, string a, string d> {
+class SubtargetFeature<string n, string a,  string v, string d> {
   // Name - Feature name.  Used by command line (-mattr=) to determine the
   // appropriate target chip.
   //
   string Name = n;
   
-  // Type - Type of attribute to be set by feature.
-  //
-  string Type = t;
-  
   // Attribute - Attribute to be set by feature.
   //
   string Attribute = a;
   
+  // Value - Value the attribute to be set to by feature.
+  //
+  string Value = v;
+  
   // Desc - Feature description.  Used by command line (-mattr=) to display help
   // information.
   //