rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.

[oota-llvm.git] / lib / Target / Target.td

diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index c7aaed969e47a0d0e8285c83fc959003bc50cc5c..b64f65ea4007c256c94ff88fecf61b381d4c4db9 100644 (file)
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -2,8 +2,8 @@
 // 
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 // 
 //===----------------------------------------------------------------------===//
 //
@@ -53,7 +53,8 @@ class Register<string n> {
   // These values can be determined by locating the <target>.h file in the
   // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES.  The
   // order of these names correspond to the enumeration used by gcc.  A value of
-  // -1 indicates that the gcc number is undefined.
+  // -1 indicates that the gcc number is undefined and -2 that register number
+  // is invalid for this mode/flavour.
   list<int> DwarfNumbers = [];
 }
 
@@ -138,7 +139,8 @@ class DwarfRegNum<list<int> Numbers> {
   // These values can be determined by locating the <target>.h file in the
   // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES.  The
   // order of these names correspond to the enumeration used by gcc.  A value of
-  // -1 indicates that the gcc number is undefined.
+  // -1 indicates that the gcc number is undefined and -2 that register number is 
+  // invalid for this mode/flavour.
   list<int> DwarfNumbers = Numbers;
 }
 
@@ -185,10 +187,12 @@ class Instruction {
   // instruction.
   bit isReturn     = 0;     // Is this instruction a return instruction?
   bit isBranch     = 0;     // Is this instruction a branch instruction?
+  bit isIndirectBranch = 0; // Is this instruction an indirect branch?
   bit isBarrier    = 0;     // Can control flow fall through this instruction?
   bit isCall       = 0;     // Is this instruction a call instruction?
-  bit isLoad       = 0;     // Is this instruction a load instruction?
-  bit isStore      = 0;     // Is this instruction a store instruction?
+  bit isSimpleLoad = 0;     // Is this just a load instruction?
+  bit mayStore     = 0;     // Can this instruction modify memory?
+  bit isImplicitDef = 0;    // Is this instruction an implicit def instruction?
   bit isTwoAddress = 0;     // Is this a two address instruction?
   bit isConvertibleToThreeAddress = 0;  // Can this 2-addr instruction promote?
   bit isCommutable = 0;     // Is this 3 operand instruction commutable?
@@ -199,6 +203,20 @@ class Instruction {
   bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
   bit hasCtrlDep   = 0;     // Does this instruction r/w ctrl-flow chains?
   bit isNotDuplicable = 0;  // Is it unsafe to duplicate this instruction?
+
+  // Side effect flags - If neither of these flags is set, then the instruction
+  // *always* has side effects. When set, the flags have these meanings:
+  //
+  //  neverHasSideEffects - The instruction has no side effects that are not
+  //    captured by any operands of the instruction or other flags, and when
+  //    *all* instances of the instruction of that opcode have no side effects.
+  //  mayHaveSideEffects  - Some instances of the instruction can have side
+  //    effects. The virtual method "isReallySideEffectFree" is called to
+  //    determine this. Load instructions are an example of where this is
+  //    useful. In general, loads always have side effects. However, loads from
+  //    constant pools don't. Individual back ends make this determination.
+  bit neverHasSideEffects = 0;
+  bit mayHaveSideEffects = 0;
   
   InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.