-//===- Target.td - Target Independent TableGen interface --------*- C++ -*-===//
+//===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// description classes in llvm/Target/MRegisterInfo.h
-// Register - You should define one instance of this class for each register in
-// the target machine.
-//
-class Register {
+// Register - You should define one instance of this class for each register
+// in the target machine. String n will become the "name" of the register.
+class RegisterBase<string n> {
string Namespace = "";
- string Name = "";
+ string Name = n;
+
+ // SpillSize - If this value is set to a non-zero value, it is the size in
+ // bits of the spill slot required to hold this register. If this value is
+ // set to zero, the information is inferred from any register classes the
+ // register belongs to.
+ int SpillSize = 0;
+
+ // SpillAlignment - This value is used to specify the alignment required for
+ // spilling the register. Like SpillSize, this should only be explicitly
+ // specified if the register is not in a register class.
+ int SpillAlignment = 0;
}
-// NamedReg - If the name for the 'def' of the register should not become the
-// "name" of the register, you can use this to specify a custom name instead.
-//
-class NamedReg<string n> : Register {
- let Name = n;
+class Register<string n> : RegisterBase<n> {
+ list<RegisterBase> Aliases = [];
}
-// RegisterAliases - You should define instances of this class to indicate which
-// registers in the register file are aliased together. This allows the code
-// generator to be careful not to put two values with overlapping live ranges
-// into registers which alias.
-//
-class RegisterAliases<Register reg, list<Register> aliases> {
- Register Reg = reg;
- list<Register> Aliases = aliases;
+// RegisterGroup - This can be used to define instances of Register which
+// need to specify aliases.
+// List "aliases" specifies which registers are aliased to this one. This
+// allows the code generator to be careful not to put two values with
+// overlapping live ranges into registers which alias.
+class RegisterGroup<string n, list<Register> aliases> : Register<n> {
+ let Aliases = aliases;
}
// RegisterClass - Now that all of the registers are defined, and aliases
// Methods - This member can be used to insert arbitrary code into a generated
// register class. The normal usage of this is to overload virtual methods.
code Methods = [{}];
-
- // isDummyClass - If this is set to true, this register class is not really
- // part of the target, it is just used for other purposes.
- bit isDummyClass = 0;
}
// Instruction set description - These classes correspond to the C++ classes in
// the Target/TargetInstrInfo.h file.
//
-
class Instruction {
- string Name; // The opcode string for this instruction
+ string Name = ""; // The opcode string for this instruction
string Namespace = "";
- list<Register> Uses = []; // Default to using no non-operand registers
- list<Register> Defs = []; // Default to modifying no non-operand registers
+ dag OperandList; // An dag containing the MI operand list.
+ string AsmString = ""; // The .s format to print the instruction with.
+
+ // Pattern - Set to the DAG pattern for this instruction, if we know of one,
+ // otherwise, uninitialized.
+ list<dag> Pattern;
+
+ // The follow state will eventually be inferred automatically from the
+ // instruction pattern.
+
+ list<Register> Uses = []; // Default to using no non-operand registers
+ list<Register> Defs = []; // Default to modifying no non-operand registers
// These bits capture information about the high-level semantics of the
// instruction.
bit isReturn = 0; // Is this instruction a return instruction?
bit isBranch = 0; // Is this instruction a branch instruction?
+ bit isBarrier = 0; // Can control flow fall through this instruction?
bit isCall = 0; // Is this instruction a call instruction?
+ bit isLoad = 0; // Is this instruction a load instruction?
+ bit isStore = 0; // Is this instruction a store instruction?
bit isTwoAddress = 0; // Is this a two address instruction?
+ bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
+ bit isCommutable = 0; // Is this 3 operand instruction commutable?
bit isTerminator = 0; // Is this part of the terminator for a basic block?
-
- // Pattern - Set to the DAG pattern for this instruction, if we know of one,
- // otherwise, uninitialized.
- dag Pattern;
+ bit hasDelaySlot = 0; // Does this instruction have an delay slot?
}
-class Expander<dag pattern, list<dag> result> {
- dag Pattern = pattern;
- list<dag> Result = result;
+
+/// ops definition - This is just a simple marker used to identify the operands
+/// list for an instruction. This should be used like this:
+/// (ops R32:$dst, R32:$src) or something similar.
+def ops;
+
+/// Operand Types - These provide the built-in operand types that may be used
+/// by a target. Targets can optionally provide their own operand types as
+/// needed, though this should not be needed for RISC targets.
+class Operand<ValueType ty> {
+ int NumMIOperands = 1;
+ ValueType Type = ty;
+ string PrintMethod = "printOperand";
}
+def i1imm : Operand<i1>;
+def i8imm : Operand<i8>;
+def i16imm : Operand<i16>;
+def i32imm : Operand<i32>;
+def i64imm : Operand<i64>;
// InstrInfo - This class should only be instantiated once to provide parameters
// which are global to the the target machine.
//
list<string> TSFlagsFields = [];
list<int> TSFlagsShifts = [];
+
+ // Target can specify its instructions in either big or little-endian formats.
+ // For instance, while both Sparc and PowerPC are big-endian platforms, the
+ // Sparc manual specifies its instructions in the format [31..0] (big), while
+ // PowerPC specifies them using the format [0..31] (little).
+ bit isLittleEndianEncoding = 0;
+}
+
+//===----------------------------------------------------------------------===//
+// AsmWriter - This class can be implemented by targets that need to customize
+// the format of the .s file writer.
+//
+// Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
+// on X86 for example).
+//
+class AsmWriter {
+ // AsmWriterClassName - This specifies the suffix to use for the asmwriter
+ // class. Generated AsmWriter classes are always prefixed with the target
+ // name.
+ string AsmWriterClassName = "AsmPrinter";
+
+ // InstFormatName - AsmWriters can specify the name of the format string to
+ // print instructions with.
+ string InstFormatName = "AsmString";
+
+ // Variant - AsmWriters can be of multiple different variants. Variants are
+ // used to support targets that need to emit assembly code in ways that are
+ // mostly the same for different targets, but have minor differences in
+ // syntax. If the asmstring contains {|} characters in them, this integer
+ // will specify which alternative to use. For example "{x|y|z}" with Variant
+ // == 1, will expand to "y".
+ int Variant = 0;
}
+def DefaultAsmWriter : AsmWriter;
//===----------------------------------------------------------------------===//
// this target. Typically this is an i32 or i64 type.
ValueType PointerType;
- // InstructionSet - Instruction set description for this target
+ // InstructionSet - Instruction set description for this target.
InstrInfo InstructionSet;
+
+ // AssemblyWriters - The AsmWriter instances available for this target.
+ list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
}
//===----------------------------------------------------------------------===//
-// DAG node definitions used by the instruction selector...
+// DAG node definitions used by the instruction selector.
+//
+// NOTE: all of this is a work-in-progress and should be ignored for now.
//
+/*
+class Expander<dag pattern, list<dag> result> {
+ dag Pattern = pattern;
+ list<dag> Result = result;
+}
+
class DagNodeValType;
def DNVT_any : DagNodeValType; // No constraint on tree node
def DNVT_void : DagNodeValType; // Tree node always returns void
bit BuiltIn = 0;
}
+*/
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